JP4466070B2 - Information processing board and information processing system - Google Patents

Description

The present invention relates to an information processing board and an information processing system, and particularly relates to an information processing board and an information processing system that can facilitate optimization of a bus.

  For example, in a mother board such as a PC (Personal Computer) on which a plurality of boards that can be inserted and removed are mounted, a bus that connects the boards is provided in a form integrated with the mother board.

  FIG. 1 shows an example of the configuration of a conventional mother board (main board) 10.

  1 is provided with a connector 12-1 into which the board 11-1 is inserted, a connector 12-2 into which the board 11-2 is inserted, and a bus controller 14. The motherboard 10 is provided with a bus 13 for connecting the connector 12-1 and the connector 12-2. The bus 13 is also disposed between the connector 12-2 and the bus controller 14.

  On the board 11-1 and the board 11-2, for example, a CPU (Central Processing Unit) for performing various processes is mounted. The board | substrate 11-1 and the board | substrate 11-2 are mounted | worn with the motherboard 10 by being inserted in the connector 12-1 and the connector 12-2, respectively. Hereinafter, processing performed by a CPU or the like mounted on a board is referred to as a board function.

  The connectors 12-1 and 12-2 are connected to the bus controller 14 via the bus 13.

  The bus 13 is a data communication path between the connector 12-1 and the bus controller 14, and between the connector 12-2 and the bus controller 14, and is an electrical connection. In the bus 13, electrical characteristics such as drive voltage and impedance, pin assignment, and the like are almost common between the connector 12-1 and the bus controller 14 and between the connector 12-2 and the bus controller 14. . In FIG. 1, the bus 13 includes eight connection lines. That is, the bus width of the bus 13 is 8 bits.

  The bus controller 14 controls communication between the board 11-1 and the board 11-2 performed via the bus 13.

  Note that the data may be directly exchanged between the board 11-1 and the board 11-2 without providing the bus controller 14.

Here, there is a data processing device in which each module notifies a certain module of necessary bus width information set in each module, and the module adjusts the bus width for each module based on the information. (For example, refer to Patent Document 1).
JP 2002-073533 A

  However, in the motherboard 10 shown in FIG. 1, the bus 13 conforms to a predetermined standard. For example, even if the board 11-1 is changed to a high-performance board and the function of the board 11-1 is upgraded, the board 11-1 The communication speed between 11-1 and the board | substrate 11-2 does not change. Therefore, for example, when the upgraded board 11-1 requires higher-speed communication than the board 11-1 before the upgrade, it is difficult to sufficiently exhibit the performance of the upgraded board 11-1.

  Further, in order to sufficiently perform the performance of the upgraded board 11-1, when the bus 13 is changed in its bus width to enable high-speed communication, the motherboard 10 is replaced with a new motherboard 10 and the board 11- It was necessary to replace 1 with the new substrate 11-1 and the substrate 11-2 with the new substrate 11-2.

  As described above, it is difficult to optimize the bus 13 so that the performance of the upgraded board 11-1 can be sufficiently exhibited.

  The present invention has been made in view of such a situation, and in particular, enables a bus to be easily optimized.

The information processing board of the present invention is an IC (Integrated Circuit) that determines a connection line used for communication with the second information processing board from among a plurality of connection lines that connect itself to the second information processing board. and determining IC is provided with a compensation IC is IC to compensate for the electrical characteristics of the determined connecting lines as being used for communication with the second information processing substrate by determining IC, determine IC and compensation IC is It is a different IC and is characterized by being detachable .

This compensation IC can compensate the electrical characteristics of the connection line by performing impedance matching of the connection line determined to be used for communication with the second information processing board by the determination IC .

The determination IC can determine the connection line used for communication with the second information processing board in accordance with the control from the third information processing board that controls the bus.

According to another information processing board of the present invention, a connection line used for communication between the first information processing board and the second information processing board is determined from the plurality of connection lines of the bus, and the first information processing board is used. Management IC that manages the connection between the board and the second information processing board, and a compensation IC that compensates for the electrical characteristics of the bus . The management IC and the compensation IC are different ICs and are detachable It is said that it is said.

This compensation IC can compensate the electrical characteristics of the bus by performing impedance matching of the bus .

In the information processing system of the present invention, the first information processing board determines a connection line used for communication between the second information processing board and the third information processing board from the plurality of connection lines, and the second information processing board Means for managing the connection between the information processing board and the board of the third information processing board, compensation means for compensating the electrical characteristics of the bus, and the second information processing board and the third information processing by the management means A transmission unit that transmits bus information representing a connection line determined to be used for communication with the board to the third information processing board, and the management unit and the transmission unit are realized by a single detachable IC. The compensation means is realized by a detachable IC different from the IC, and the third information processing board can select the first information from the plurality of bus connection lines based on the bus information transmitted from the transmission means. Determine the connection line used for communication with the information processing board 2 And determining IC, and a compensation IC is IC to compensate for the electrical characteristics of the determined connecting lines as being used for communication with the second information processing substrate by determining IC, determine IC and compensation IC is different IC It is characterized by being detachable .

In the information processing board of the present invention, a connection line used for communication with the second information processing board is selected from among a plurality of connection lines that connect itself and the second information processing board with a detachable determination IC. The electrical characteristic of the connection line determined to be used for communication with the second information processing board is compensated by the compensation IC which is determined and is a detachable IC different from the determined IC .

In another information processing board of the present invention, a connection line used for communication between the first information processing board and the second information processing board is determined from a plurality of bus connection lines by a removable management IC. The connection between the first information processing board and the second information processing board is managed , and the electrical characteristics of the bus are compensated by a compensation IC which is a detachable IC different from the management IC .

Oite to the information processing system of the present invention, in the first information processing substrate, by the management unit of the management unit and transmitting means is realized by removable one IC, from among a plurality of connection lines, the A connection line used for communication between the second information processing board and the third information processing board is determined, and a connection between the second information processing board and the third information processing board is managed ; The electrical characteristics of the bus are compensated by compensation means realized by a detachable IC different from the IC realizing the transmission means, and used for communication between the second information processing board and the third information processing board by the transmission means . Bus information representing the connection line determined as being is transmitted to the third information processing board. Then, in the third information processing board, the detachable determination IC determines a connection line used for communication with the second information processing board from the plurality of connection lines of the bus based on the bus information . An electrical characteristic of the connection line determined to be used for communication with the second information processing board is compensated by the compensation IC which is a detachable IC different from the determined IC .

  According to the present invention, the bus can be easily optimized.

  Embodiments of the present invention will be described below. Correspondences between constituent elements described in the claims and specific examples in the embodiments of the present invention are exemplified as follows. This description is to confirm that specific examples supporting the invention described in the claims are described in the embodiments of the invention. Therefore, even if there are specific examples that are described in the embodiment of the invention but are not described here as corresponding to the configuration requirements, the specific examples are not included in the configuration. It does not mean that it does not correspond to a requirement. On the contrary, even if a specific example is described here as corresponding to a configuration requirement, this means that the specific example does not correspond to a configuration requirement other than the configuration requirement. not.

  Further, this description does not mean that all the inventions corresponding to the specific examples described in the embodiments of the invention are described in the claims. In other words, this description is an invention corresponding to the specific example described in the embodiment of the invention, and the existence of an invention not described in the claims of this application, that is, in the future, a divisional application will be made. Nor does it deny the existence of an invention added by amendment.

The information processing board according to claim 1 (for example, the board 21-1 in FIG. 2) is a first information processing board (for example, a bus 23 in FIG. 2) having a plurality of connection lines (for example, the bus 23 in FIG. 2). For example, in the information processing board mounted on the mother board 20) of FIG. 2 and communicating with the second information processing board (for example, the board 21-2 of FIG. 2) mounted on the first information processing board, A decision IC (Integrated Circuit) that decides a connection line used for communication with the second information processing board from among the plurality of connection lines that connect itself to the second information processing board. for example, a logical connection modules 32-1) of FIG. 2, the determined IC by the second compensation IC is IC to compensate for the electrical characteristics of the determined connecting lines as being used for communication with the information processing board (For example, the electrical characteristics of FIG. Comprising a amortization module 33-1) and the compensation IC and said determining IC is different IC, characterized in that it is detachable.

The information processing board according to claim 3 , wherein the determination IC is configured to respond to control from a third information processing board (for example, the mother board 20 in FIG. 2) that controls the bus. A connection line used for communication with the mobile phone is determined.

The information processing board (for example, the mother board 20 in FIG. 2) according to claim 4 is provided with a bus (for example, the bus 23 in FIG. 2) including a plurality of connection lines, and the first information processing board (for example, the bus 20 in FIG. 2). In the information processing board that controls the bus that connects the board 21-1) in FIG. 2 and a second information processing board (for example, the board 21-2 in FIG. 2), among the connection lines of the bus To determine a connection line used for communication between the first information processing board and the second information processing board, and manage a connection between the first information processing board and the second information processing board. A management IC (for example, the logical connection module 42 in FIG. 2) and a compensation IC that compensates for the electrical characteristics of the bus. The management IC and the compensation IC are different ICs, and are attached and detached. It is possible to do this.

The information processing system according to claim 6 includes a first information processing board (for example, a mother board in FIG. 2) on which a bus (for example, the bus 23 in FIG. 2) including a plurality of connection lines is disposed, and the first information processing board. A third information processing board (for example, the first information processing board) that communicates with the second information processing board (for example, the board 21-2 in FIG. 2) mounted on the first information processing board. In the information processing system including the substrate 21-1) in FIG. 2, the first information processing substrate includes the second information processing substrate and the third information processing substrate out of the plurality of connection lines. Management means for determining a connection line to be used for the communication of the second information processing board and managing the connection between the second information processing board and the third information processing board (for example, executing the process of step S115 in FIG. 17) a logical connection module 42), the conductive of the bus And compensating means for compensating for characteristics, the bus information representative of the determined connecting lines as being used for communication with the third information processing board and the second information processing substrate by the management unit, the third A transmission means for transmitting to the information processing board (for example, the logical connection module of FIG. 2 for executing the processing of step S116 of FIG. 17), and the management means and the transmission means are realized by one detachable IC The compensation means is realized by a detachable IC different from the IC, and the third information processing board is configured to connect the plurality of connections of the bus based on bus information transmitted from the transmission means. from the line, the second decision IC that determines the connecting line to be used for communication with the information processing substrate (e.g., a logical connection modules 32 of FIG. 2), the second information processing by the determining IC Base And a compensation IC is IC to compensate for the electrical characteristics of the determined connecting lines as being used for communication with, the compensation IC and said determining IC is different IC, characterized in that it is detachable And

  Hereinafter, specific embodiments to which the present invention is applied will be described in detail with reference to the drawings.

  FIG. 2 shows a configuration example of an embodiment of a mother board (main board) 20 to which the present invention is applied.

  2 is provided with a bus controller 22, a connector 24-1 into which the board 21-1 is inserted, and a connector 24-2 into which the board 21-2 is inserted. The motherboard 20 is provided with a bus 23 for connecting the connector 24-1 and the connector 24-2. The bus 23 is also disposed between the connector 24-2 and the bus controller 22.

  A functional module 31-1, a logical connection module 32-1, and an electrical characteristic compensation module 33-1 are mounted on the board 21-1. A functional module 31-2, a logical connection module 32-2, and an electrical characteristic compensation module 33-2 are mounted on the board 21-2. The board 21-1 can be attached to the mother board 20 by being inserted into the connector 24-1 or 24-2. The same applies to the substrate 21-2. Here, it is assumed that the board 21-1 is attached to the connector 24-1 and the board 21-2 is attached to the connector 24-2.

  The functional module 31-1, the logical connection module 32-1, and the electrical characteristic compensation module 33-1 are configured by, for example, an IC (Integrated Circuit) and can be attached to and detached from the substrate 21-1. ing. In addition, the functional module 31-2, the logical connection module 32-2, and the electrical characteristic compensation module 33-2 are also composed of, for example, an IC and can be attached to and detached from the substrate 21-2.

  The bus controller 22 is equipped with a bus function module 41, a logical connection module 42, and an electrical characteristic compensation module 43. Note that the bus function module 41, the logical connection module 42, and the electrical characteristic compensation module 43 are configured by, for example, an IC and are detachable from the mother board 20.

  Thus, since each module can be attached to and detached from each board (motherboard 20), the function of each board 21 can be easily changed by replacing the modules.

  The bus 23 is an electrical connection that is a data communication path between the board 21-1 and the bus controller 22 and between the board 21-2 and the bus controller 22. The bus 23 electrically connects the board 21-1 attached to the connector 24-1, the board 21-2 attached to the connector 24-2, and the bus controller 22. Data and the like are transmitted and received between the board 21-1, the board 21-2, and the bus controller 22 via the bus 23.

  The connector 24-1 and the connector 24-2 are connected to the bus controller 22 via the bus 23.

  FIG. 3 is a block diagram illustrating a configuration of the mother board 20 of FIG. 2 in a state where the board 21-1 and the board 21-2 are respectively attached to the connector 24-1 and the connector 24-2.

  The functional module 31-1 of the board 21-1 executes the function of the board 21-1. For example, the functional module 31-1 executes graphic processing such as GUI (Graphical User Interface), packet transmission / reception processing, and the like.

  A protocol such as a bus cycle is mounted on the logical connection module 32-1 of the board 21-1. The logical connection module 32-1 determines a connection line used for communication with the board 21-2 from the plurality of connection lines of the bus 23 in accordance with control from the bus controller 22 described later.

  The electrical property compensation module 33-1 of the board 21-1 is configured by a circuit for compensating electrical properties of the bus 23 such as bus drive voltage and impedance. The electrical characteristic compensation module 33-1 changes the electrical characteristics of the connection line of the bus 23 used for communication with the board 21-2 using a variable resistor or a capacitor. For example, the electrical characteristic compensation module 33-1 performs impedance matching and the like.

  As described above, the logical connection module 32-1 determines the connection by the bus 23, and the electrical characteristic compensation module 33-1 compensates the determined electrical characteristic of the bus 23. The functional module 31-1 performs data processing corresponding to the function of the board 21-1 while performing data communication via the bus 23 in which such management is performed.

  The functional module 31-2, the logical connection module 32-2 and the electrical characteristic compensation module 33-2 of the board 21-2 are the functional module 31-1, the logical connection module 32-1 of the board 21-1, Since it is the same as that of the electrical characteristic compensation module 33-1, the description thereof is omitted.

  In addition, hereinafter, the substrates 21-1 to 21-i (i = 1, 2, 3,...), Functional modules 31-1 to 31-i, logical modules 32-1 to 32-i, electrical characteristics When it is not necessary to distinguish between the compensation modules 33-1 to 33-i, the boards 21-1 to 21-i, the functional modules 31-1 to 31-i, the logical modules 32-1 to 32-i, and the electrical characteristics The compensation modules 33-1 to 33-i are collectively referred to as a substrate 21, a functional module 31, a logical module 32, and an electrical characteristic module 33, respectively.

  The bus function module 41 of the bus controller 22 controls communication between the board 21-1 and the board 21-2 performed via the bus 23.

  The logical connection module 42 of the bus controller 22 sets the topology of the bus 23. Specifically, the logical connection module 42 determines (assigns) a connection line used for communication between the board 21-1 and the board 21-2 from among the plurality of connection lines of the bus 23. The topology of the bus 23 is set, and the connection between the board 21-1 and the board 21-2 is logically managed. Further, the logical connection module 42 is a connection line determined to be used for communication between the board 21-1 and the board 21-2, that is, the board 21-1 and the board 21-2 obtained as a result of the assignment. By transmitting bus information representing the logical connection between the two to the board 21, the logical connection module 32 of the board 21 is controlled.

  The electrical characteristic compensation module 43 of the bus controller 22 is configured by a circuit for compensating electrical characteristics of the bus 23 in the same manner as the electrical characteristic compensation module 33 of the substrate 21. The electrical characteristic compensation module 43 changes the electrical characteristic of the connection line of the bus 23 used for communication between the board 21-1 and the board 21-2 using a variable resistor, a capacitor, or the like.

  The impedance of the connection line itself of the bus 23 is a sufficiently small value. The electrical characteristic compensation module 33 of the board 21 and the electrical characteristic compensation module 43 of the bus controller 22 change the electrical characteristics of the connection line of the bus 23 used for communication between the board 21-1 and the board 21-2. Thus, the impedance of the connection line of the bus 23 is changed to an optimum impedance for communication between the board 21-1 and the board 21-2.

  Also, the bus width of the bus 23 is sufficiently wide (the number of connection lines of the bus 23 is sufficiently large), and the logical connection module 42 of the bus controller 22 determines the allocated amount of the bus 23 (board 21-1). By changing the number of connection lines used for communication between the board 21-2 and the board 21-2, the bus width for communication between the board 21-1 and the board 21-2 is set to an optimum width.

  As described above, in the bus 23, the impedance of the connection line is changed to an optimum impedance for communication between the board 21-1 and the board 21-2, and the bus width is changed to the board 21-1 and the board 21-2. The bus 23 can be easily optimized by setting the optimum width for communication between the two.

  4 to 6 show examples of the topology of the bus 23. FIG. These topologies are set by, for example, the logical connection module 42 of the bus controller 22. 4 to 6, four substrates 21-1 to 21-4 are connected to the bus 23. The board | substrate 21-3 and the board | substrate 21-4 are comprised similarly to the board | substrate 21-1 of FIG.

  In FIG. 4, all of the boards 21-1 to 21-4 are connected on one bus 23. This topology is called a bus type in terms of network connection.

  In FIG. 5, among the boards 21-1 to 21-4, the board 21-2 and the board 21-1, the board 21-3, or the board 21-4 are connected via the bus 23. Yes. This topology is called a star type in terms of network connection.

  In FIG. 6, the boards 21-1 to 21-4 are directly connected to each other via the bus 23. That is, the substrate 21-1 is the substrate 21-2 to the substrate 21-4, the substrate 21-2 is the substrate 21-1, the substrate 21-3, the substrate 21-4, and the substrate 21-3 is the substrate. The board 21-1, the board 21-2, the board 21-4, and the board 21-4 are directly connected to each of the boards 21-1 to 21-3 via the bus 23. This topology is called a mesh type in terms of network connection.

  FIG. 7 shows a specific example of the bus width in the bus type topology shown in FIG. 4, and FIG. 8 shows a specific example of the bus width in the mesh type topology shown in FIG.

  7 and 8, the bus width of the bus 23 is, for example, 64 bits (bit). That is, the bus 23 is composed of 64 connection lines. In FIGS. 7 and 8, three substrates 21-1 to 21-3 are connected via the bus 23.

  In FIG. 7, all of the boards 21-1 to 21-3 are connected to 64 connection lines of the bus 23. That is, the bus width of the bus 23 used for communication between the board 21-1 and the board 21-2, between the board 21-2 and the board 21-3, and between the board 21-1 and the board 21-3. Is 64 bits.

  In the topology of the bus 23 illustrated in FIG. 7, data communication is performed between one board 21-i and another board 21-j (i ≠ j) using all 64 bits that are the bus width of the bus 23. It can be performed. Therefore, it is possible to perform communication efficiently and is suitable for communication between the board 21-i and the board 21-j having a function that requires high-speed communication. However, when communication is performed from one board 21-i among the boards 21-1 to 21-3 to one other board 21-j, the bus 23 is occupied for communication. Therefore, communication from one board 21-i to the other board 21-j is performed in a time division manner. For this reason, responsiveness may be sacrificed.

  In FIG. 8, the bus 23 is divided into six 8-bit buses 23-1 to 23-6. The bus 23-1 is for data transmission from the board 21-1 to the board 21-2, the bus 23-2 is for data transmission from the board 21-2 to the board 21-3, and the bus 23-3 is , For transmitting data from the board 21-1 to the board 21-3. The bus 23-4 is for data transmission from the board 21-2 to the board 21-1, and the bus 23-5 is for data transmission from the board 21-3 to the board 21-2. Are for data transmission from the board 21-3 to the board 21-1.

  Since the bus width of each of the buses 23-1 to 23-6 is 8 bits, data cannot be transmitted at a higher speed than the bus 23 shown in FIG. Communication between the substrates 21 can be performed simultaneously, and responsiveness can be improved.

  FIG. 9 shows a configuration example of another embodiment of the mother board 60 to which the present invention is applied. In FIG. 9, parts corresponding to those in FIG. 2 are denoted by the same reference numerals.

  On the mother board 60 in FIG. 9, four boards 21-1 to 21-4 and a bus controller 22 are mounted. The motherboard 60 is provided with a bus 61.

  The bus 61 includes a clock bus 61-1 composed of one connection line, an address bus 61-2 composed of 16 connection lines, and a data bus 61-3 composed of 64 connection lines. Accordingly, the bus widths of the clock bus 61-1, the address bus 61-2, and the data bus 61-3 are 1 bit, 16 bits, and 64 bits, respectively.

  FIG. 10 is a diagram illustrating the bus 61 in FIG. 9 when performing high-speed communication.

  In FIG. 10, in order to perform high-speed communication between the two boards 21, the bus controller 22 sets the bus 61 to 2 so that the bus width of the data bus 61-3 connecting the two boards 21 is the maximum 64 bits. By allocating for communication between the two substrates 21, the topology of the bus 61 is set to the bus type described with reference to FIGS. In this case, among the substrates 21-1 to 21-4, data can be communicated at high speed from one substrate 21-i to the other substrate 21-j. However, when data is communicated from one board 21-i to another board 21-j among the boards 21-1 to 21-4 via the data bus 61-3, the communication is data. Occupies the bus 61-3. That is, while communication of data from one board 21-i to the other board 21-j is performed via the data bus 61-3, communication other than the communication is performed on the data bus 61-3. Can not be done through. Therefore, data communication between the board 21-i and the board 21-j is performed in a time division manner.

  FIG. 11 is a diagram illustrating the timing of communication performed between the boards 21 in FIG. 10 via the bus 61.

  In FIG. 11, in synchronization with the first clock on the clock bus 61-1 of the bus 61, the board 21-1 and the board 21-2 are connected via the data bus 61-3 having a bus width of 64 bits. The communication between the board 21-2 and the board 21-3 is performed via the data bus 61-3 in synchronization with the second clock.

  Then, communication between the board 21-3 and the board 21-4 is performed via the data bus 61-3 in synchronization with the third clock, and the data bus 61-3 is synchronized with the fourth clock. The communication between the board 21-4 and the board 21-1 is performed via the.

  Further, communication between the board 21-1 and the board 21-2 is performed via the data bus 61-3 in synchronization with the fifth clock, and the data bus 61-3 is synchronized with the sixth clock. Communication is performed between the board 21-2 and the board 21-3.

  That is, in FIG. 11, while synchronizing with the clock on the clock bus 61-1 of the bus 61, between the board 21-1 and the board 21-2, between the board 21-2 and the board 21-3, and between the board 21 and FIG. -3 and the substrate 21-4, and communication between the substrate 21-4 and the substrate 21-1 is performed in a time-sharing manner.

  That is, in FIG. 11, the occupying entity of the data bus 61-3 is switched every clock. Therefore, when it is time to occupy the data bus 61-3, the board 21-i and the board 21-j can communicate via the data bus 61-3 having a bus width of 64 bits. It is possible to transmit / receive data of up to 64 bits at high speed.

  Note that the occupying entity of the data bus 61-3 may be switched every plural clocks instead of every one clock.

  In FIG. 11, although 64-bit data can be communicated at high speed, the cycle of communication between the board 21-i and the board 21-j is four times the clock, and the responsiveness is lowered.

  FIG. 12 is a diagram illustrating the bus 61 in FIG. 9 when performing highly responsive communication.

  In FIG. 12, in order to perform highly responsive communication, the bus controller 22 connects the data bus 61-3 of the bus 61 between the board 21-1 and the board 21-2, and between the board 21-2 and the board 21-3. , Between the board 21-3 and the board 21-4, between the board 21-4 and the board 21-1, for communication between the four boards, and for communication between the boards 21 By assigning the bus 61 for communication between the boards 21 so that the bus width of the data bus 61-3 is 16 (= 64/4) bits, the topology described in FIG. 6 and FIG. Set.

  In FIG. 12, communication between each of the substrates 21-1 to 21-4 can be performed simultaneously, and responsiveness can be improved. However, since the bus width between the boards 21 of the data bus 61-3 is 16 (= 64/4) bits, communication is performed via the data bus 61-3 having a bus width of 64 bits shown in FIG. The amount of data that can be transmitted / received at one time is smaller than that of.

  FIG. 13 is a diagram for explaining the timing of communication performed via the bus 61 between the boards 21 in FIG.

  In FIG. 13, while synchronizing with the clock on the clock bus 61-1 of the bus 61, between the board 21-1 and the board 21-2, between the board 21-2 and the board 21-3, and between the board 21-3. And the board 21-4, and the communications between the board 21-4 and the board 21-1 can be simultaneously performed via the data bus 61-3 having a bus width of 16 bits. That is, communication can be performed at one clock cycle between one substrate 21-i and the other substrate 21-j. Therefore, when the data required for one communication between one board 21-i and the other board 21-j is 16 bits or less and responsiveness is important, the space between the plurality of boards 21 Thus, responsiveness can be improved by performing communication simultaneously.

  Here, in FIGS. 12 and 13, since the communication between the board 21-i and the board 21-j is performed via the data bus 61-3 having a bus width of 16 bits, FIG. 10 and FIG. As shown, the transfer rate per 4 clocks is the same as when communication between the board 21-i and the board 21-j is performed via the data bus 61-3 having a bus width of 64 bits. . However, in FIGS. 12 and 13, since communication can be performed simultaneously between the plurality of substrates 21 in one clock, responsiveness can be improved.

  The topology of the bus 100 will be further described with reference to FIG.

  In FIG. 14, four substrates 21-1, 21-2, 21-3, and 21-4 are connected via a bus 100. The bus width of the bus 100 is, for example, 32 bits. That is, the bus 100 is composed of 32 connection lines.

  In FIG. 14, 16 of the 32 connection lines of the bus 100 are determined for communication between the board 21-1 and the board 21-2. That is, of the bus 100 having a bus width of 32 bits, 16 bits are allocated for communication between the board 21-1 and the board 21-2. The other 8 bits of the bus 100 are allocated for communication between the board 21-2 and the board 21-3, and the remaining 8 bits are allocated for broadcasting.

  FIG. 15 is a diagram for explaining the topology setting process of the bus controller 22 for setting the topology of the bus 100 of FIG.

  Hereinafter, the i-th of the 32 connection lines of the 32-bit bus 100 will be referred to as the (i-1) th bit as appropriate.

  As shown in the upper part of FIG. 15, the boards 21-1 to 21-4 are connected to the bus controller 22 via the bus 100 having a bus width of 32 bits (BUS [31: 0] in the figure). ing. As indicated by the tip of the white arrow, the bus 100 has a bus width assigned for communication between the boards 21.

  That is, the bus controller 22 (logical connection module 42 thereof) allocates, for example, a total of 8 bits from the 0th bit to the 7th bit among the 32 bits of the bus 100 (BUS [7 in the figure). : 0]). Also, the bus controller 22 transfers, for example, a total of 8 bits (BUS [15: 8] in the figure) from the 8th bit to the 15th bit of the bus 100 between the board 21-2 and the board 21-3. For example, a total of 16 bits from the 16th bit to the 31st bit (BUS [31:16] in the figure) of the bus 100 are communicated between the board 21-1 and the board 21-2. Assign for use.

  FIG. 16 is a flowchart for describing the topology setting processing of the bus 100 performed by the bus controller 22. This topology setting process is started, for example, when the board 21 requests to change the topology of the bus 100. The bus controller 22 (the logical connection module 42) stores in advance the bus width of the bus 100 necessary for the board 21 to communicate with the other board 21.

  In step S <b> 11, the bus controller 22 is necessary for communication between the board 21-1 and the board 21-2 from the bus width required for the board 21 stored in advance for communication with the other board 21. Recognizing that the bus width is 16 bits, of the 32 bits of the bus 100, a total of 16 bits from the 16th bit to the 31st bit are used for communication between the board 21-1 and the board 21-2. Assign to. The bus controller 22 transmits bus information representing the logical connection between the board 21-1 and the board 21-2 obtained as a result of the assignment to the board 21-1.

  In step S31, the board 21-1 receives the bus information transmitted from the bus controller 22, and among the 32 bits of the bus 100, the 16th to 31st bits represented by the bus information are regarded as the board 21-2. Decide for communication.

  In step S12, the bus controller 22 transmits to the board 21-2 bus information representing the result of assigning the bus 100 for communication between the board 21-1 and the board 21-2 in step S11.

  In step S51, the board 21-2 receives the bus information transmitted from the bus controller 22, and among the 32 bits of the bus 100, the 16th to 31st bits represented by the bus information are regarded as the board 21-1. Decide for communication.

  In step S13, the bus controller 22 transmits to the board 21-3 bus information representing the result of assigning the bus 100 for communication between the board 21-1 and the board 21-2 in step S11.

  In step S71, the board 21-3 receives the bus information transmitted from the bus controller 22, and among the 32 bits of the bus 100, the 16th to 31st bits represented by the bus information are regarded as the board 21-1. Open to substrate 21-2. For example, the electrical compensation module 33-3 of the board 21-3 has 16 connection lines corresponding to the 16th to 31st bits of the bus 100 (impedance seen from the bus 100 side of the terminals connected to the bus 100). Is set to high impedance so that the connection line is not used, so that the 16th to 31st bits of the bus 100 are opened.

  In step S14, the bus controller 22 transmits to the board 21-4 bus information indicating the result of assigning the bus 100 for communication between the board 21-1 and the board 21-2 in step S11.

  In step S91, the board 21-4 receives the bus information transmitted from the bus controller 22, and out of the 32 bits of the bus 100, the 16th to 31st bits represented by the bus information are replaced with the board 21-3. In the same manner, the substrate 21-1 and the substrate 21-2 are opened.

  As described above, the bus controller 22 completes the setting (assignment) of the bus 100 for communication between the board 21-1 and the board 21-2.

  In step S15, the bus controller 22 is necessary for communication between the board 21-2 and the board 21-3 from the bus width required for the board 21 stored in advance to communicate with the other board 21. Recognizing that the bus width is 8 bits, of the 32 bits of the bus 100, 8 bits from the 8th bit to the 15th bit are used for communication between the board 21-2 and the board 21-3. Assign to. The bus controller 22 transmits bus information representing a logical connection between the board 21-2 and the board 21-3 obtained as a result of the assignment to the board 21-2.

  In step S52, the board 21-2 receives the bus information transmitted from the bus controller 22, and among the 32 bits of the bus 100, the 8th to 15th bits represented by the bus information are set as the board 21-3. Decide for communication.

  In step S16, the bus controller 22 transmits to the board 21-3 bus information representing the result of assigning the bus 100 for communication between the board 21-2 and the board 21-3 in step S15.

  In step S72, the board 21-3 receives the bus information transmitted from the bus controller 22, and among the 32 bits of the bus 100, the 8th to 15th bits represented by the bus information are the board 21-2. Decide for communication.

  In step S17, the bus controller 22 transmits to the board 21-1 bus information representing the result of assigning the bus 100 for communication between the board 21-2 and the board 21-3 in step S15.

  In step S32, the board 21-1 receives the bus information transmitted from the bus controller 22, and among the 32 bits of the bus 100, the 8th to 15th bits represented by the bus information are regarded as the board 21-2. Open to substrate 21-3.

  In step S18, the bus controller 22 transmits to the board 21-4 bus information indicating the result of assigning the bus 100 for communication between the board 21-2 and the board 21-3 in step S15.

  In step S92, the board 21-4 receives the bus information transmitted from the bus controller 22, and among the 32 bits of the bus 100, the 8th to 15th bits represented by the bus information are regarded as the board 21-2. Open to substrate 21-3.

  As described above, the bus controller 22 completes the setting of the bus 100 for communication between the board 21-2 and the board 21-3.

  In step S19, the bus controller 22 recognizes that the bus width required for broadcasting is 8 bits from the bus width required for the communication of the board 21 stored in advance with the other board 21, and the bus The topology of the bus 100 is set by allocating a total of 8 bits from the 0th bit to the 7th bit out of 100 32 bits for broadcast communication. The bus controller 22 transmits bus information representing a logical connection for broadcast communication obtained as a result of the assignment to the board 21-1.

  In step S33, the board 21-1 receives the bus information transmitted from the bus controller 22, and among the 32 bits of the bus 100, determines from the 0th bit to the 7th bit represented by the bus information for broadcasting. .

  In step S20, the bus controller 22 transmits to the board 21-2 bus information representing the result of assigning the bus 100 for broadcast communication in step S19.

  In step S53, the board 21-2 receives the bus information transmitted from the bus controller 22, and among the 32 bits of the bus 100, determines from the 0th bit to the 7th bit represented by the bus information for broadcasting. .

  In step S21, the bus controller 22 transmits bus information representing the result of assigning the bus 100 for broadcast communication in step S19 to the board 21-3.

  In step S73, the board 21-3 receives the bus information transmitted from the bus controller 22, and among the 32 bits of the bus 100, determines from the 0th bit to the 7th bit represented by the bus information for broadcasting. .

  In step S22, the bus controller 22 transmits to the board 21-4 bus information representing the result of assigning the bus 100 for broadcasting in step S19.

  In step S93, the board 21-4 receives the bus information transmitted from the bus controller 22, and among the 32 bits of the bus 100, determines from the 0th bit to the 7th bit represented by the bus information for broadcasting. .

  As described above, the bus controller 22 completes the setting of the broadcast bus 100.

  Then, the bus controller 22 assigns all 32 bits of the bus 100 for communication between the boards 21, thereby setting the topology of the bus 100 and finishing the topology setting process of the bus 100.

  FIG. 17 is a flowchart for describing the topology setting processing of the bus 100 performed by the logical connection module 42 of the bus controller 22. The bus topology setting process is started when, for example, a power supply of a mother board (not shown) on which the bus 100 is provided is turned on. Also, the boards 21 connected to the bus controller 22 via the bus 100 are numbered in order from 0, and the board 21 with the number j is referred to as board #j.

  In step S111, the logical connection module 42 initializes a value n representing the board number to 0, and proceeds to step S112.

  In step S112, the logical connection module 42 determines whether or not a topology change request for the bus 100 has been received from the board 21, and waits until a topology change request is received.

  In step S112, when the logical connection module 42 determines that the request for changing the topology of the bus 100 from the board 21 has been received, the process proceeds to step S113, where the logical connection module 42 determines the logical connection module 32 of the board 21. Stop the bus cycle. Note that when the bus cycle is stopped, the logical connection module 42 cancels the assignment of the bus 100 so far. That is, all the bits of the bus 100 are bits that are not allocated for communication between the boards 21.

  In step S114, the logical connection module 42 determines whether or not bus resources remain. That is, the logical connection module 42 determines whether there is a bit that is not allocated for communication between the boards 21 among the 32 bits that are the bus width of the bus 100. This determination is made by referring to a management table described later.

  In step S114, when the logical connection module 42 determines that the bus resource remains, the logical connection module 42 proceeds to step S115 and assigns the bus 100 to the board #n.

  For example, when the board #n is the board 21-1, as shown in step S11 of FIG. 16, the logical connection module 42 requires the board 21 stored in advance for communication with other boards 21. It is recognized from the bus width of the bus 100 that the bus width necessary for communication between the board 21-1 and the board 21-2 is 16 bits, and the bus 100 Of the 32 bits that are the width, for example, 16 bits from the unassigned 16th bit to the 31st bit are assigned for communication with the board 21-2. Then, the logical connection module 42 uses a management table for managing that the 16th to 31st bits of the bus 100 have already been allocated for communication between the board 21-1 and the board 21-2. Remember me. The logical connection module 42 manages the bus 100 by storing in the management table that all the bits of the bus 100 are not allocated even when the allocation of the bus 100 is released (step S113). .

  Here, in the board #n, when the bus widths necessary for communication with the plurality of other boards 21 are respectively stored, the logical connection module 42 is connected to the board #n. Each bus 100 is assigned for communication with the substrate 21.

  When assigning the bus 100 for communication between the board #n and the board # n + 1, the logical connection module 42, for example, assigns the board #n to the board #n when assigning to the board #n. The bus 100 may be assigned for communication with # n + 1, or when assigning to the board # n + 1, the bus 100 may be assigned for communication between the board #n and # n + 1. You may go. Furthermore, even when the bus 100 is assigned for broadcasting in step S115, the logical connection module 42 can assign the bus 100 for broadcasting when assigning to any of the boards 21. . The logical connection module 42 does not allocate the bus 100 for communication to which the bus 100 has already been allocated.

  In step S116, the logical connection module 42 transmits bus information representing the result of the assignment of the bus 100 in step S115 to all the boards 21 connected via the bus 100, and the process proceeds to step S117.

  In step S117, the logical connection module 42 increments the value n by 1 and proceeds to step S118.

  In step S118, the logical connection module 42 determines whether or not the assignment of the bus 100 to all the boards 21 has been completed. That is, the logical connection module 42 determines whether or not the value n incremented in step S118 is equal to or greater than the number of boards 21 connected to the bus controller 22.

  If the logical connection module 42 determines in step S118 that the assignment of the bus 100 to all the boards 21 has not been completed, the logical connection module 42 returns to step S114 and repeats the above-described processing.

  If the logical connection module 42 determines in step S118 that the assignment of the bus 100 to all the boards 21 has been completed, the process proceeds to step S120.

  On the other hand, in step S114, if the logical connection module 42 determines that no bus resource remains, the logical connection module 42 proceeds to step S119 and performs an arbitrary error process because the bus width is insufficient.

  Here, the logical connection module 42 assigns the bus 100 to the boards 21 in the order of higher priority as error processing, for example, in common for communication between the boards 21 with lower priority, for example, 8 A process is performed such as assigning bits and not assigning the bus 100 to a certain board 21.

  In step S120, the logical connection module 42 restarts the bus cycle of the logical connection module 32 of the substrate 21, returns to step S111, and repeats the above-described processing.

  In step S114 described above, the logical connection module 42 assigns the bus 100 to all the boards 21 based on the bus width required for the board 21 to communicate with the other boards 21, and the topology of the bus 100 is determined. Set. Therefore, for example, when the manufacturer that manufactures the motherboard 20 and the board 21 changes the board 21 to the new board 21 and upgrades, the topology of the bus 100 is set according to the nature of communication required by the new board 21. The bus 100 allocation can be dynamically changed by changing the bus width of the bus 100 required for communication between the board 21 and the other board 21 in accordance with the topology. Thereby, the optimal bus width and responsiveness for each substrate 21 can be easily obtained.

  In the above description, the bus controller 22 performs the topology setting process of the bus 100 when the board 21 requests the topology change of the bus 100. However, the user operates the input unit (not shown) to change the topology. A change may be requested.

  In the above description, the topology setting process of the bus 100 is performed by the logical connection module 42 of the bus controller 22, but may be performed by the bus function module 41.

  FIG. 18 is a flowchart for explaining the bus determination processing of the logical connection module 32 of the board 21 performed corresponding to the processing of the bus controller 22 of FIG. The bus determination process is started when, for example, a power supply of a mother board (not shown) on which the bus 100 is provided is turned on.

  In step S141, the logical connection module 32 determines whether or not the bus information transmitted from the logical connection module 42 of the bus controller 22 has been received in the process of step S116 in FIG. stand by.

  In step S141, when the logical connection module 32 determines that the bus information has been received, the logical connection module 32 proceeds to step S142, and based on the bus information, performs communication with the board from a plurality of bits that are the bus width of the bus 100. A bit to be used is determined, and the process returns to step S141 to repeat the above-described processing.

  For example, in the logical connection module 32 of the board 21-1, the bus assigned by the bus controller 22 for communication with the board 21-2 is the 16th bit out of the 32 bits of the bus width of the bus 100. To the 31st bit, the 16th to 31st bits of the bus 100 are determined to be used for communication with the board 21-2.

  As described above, in the motherboard 20 provided with the bus 23 composed of a plurality of connection lines, the logical connection module 42 of the bus controller 22 is mounted on the motherboard 20 from the plurality of connection lines of the bus 23. A connection line used for communication between the board 21-1 and the board 21-2 is determined, and connection between the board 21-1 and the board 21-2 is managed. In addition, the logical connection module 42 transmits bus information representing a connection line determined to be used for communication between the board 21-1 and the board 21-2 to the board 21-1. Then, the logical connection module 42-1 of the board 21-1 mounted on the motherboard 20 uses the connection line used for communication with the board 21-2 from among the plurality of connection lines of the bus 23 based on the bus information. To decide. Further, the electrical connection module 42-1 of the board 21-1 compensates for the electrical characteristics of the connection line used for communication with the board 21-2. Accordingly, the bus 23 can be easily optimized.

  The bus controller 22 can be provided on each substrate 21 instead of being provided independently on the mother board 20. At this time, for example, one of the bus controllers 22 provided on each board 21 operates to manage the topology of the bus 23.

  Further, in the above description, the case where the bus 23 is optimized according to the change of the board 21 has been described. However, an example in which the board 21 and the bus controller 22 are changed according to the upgrade of the bus 23 is illustrated in FIG. Explanation will be made with reference to FIG.

  FIG. 19 is a diagram illustrating changes in the board 21 and the bus controller 22 when the bus 23 is upgraded. Here, the bus 23 before the upgrade can be, for example, a bus 23 that conforms to the ISA (Industrial Standard Architecture) standard, and the bus 23 after the upgrade conforms to, for example, the PCI (Peripheral Components Interconnect) 66 standard Bus 23.

  As described above, when the bus 23 is upgraded, the bus width, pin assignment, and the like change. In this case, for example, the manufacturer that manufactures the mother board 20 and the board 21 has the modules detachable as described above. Therefore, the logic of the board 21 corresponding to the bus width and the pin assignment conforming to the ISA standard. The logical connection module 32 and the logical connection module 42 of the bus controller 22 are exchanged for the logical connection module 32 and the logical connection module 42 corresponding to the bus width and pin assignment of the bus 23 compliant with the PCI66 standard.

  In addition, when the electrical characteristics of the bus 23 change greatly due to the upgrade of the bus 23, the manufacturer that manufactures the motherboard 20 and the board 21 determines the electrical characteristics of the board 21 corresponding to the electrical characteristics of the bus 23 in accordance with the ISA standard. The characteristic compensation module 33 and the electrical characteristic compensation module 43 of the bus controller 22 are replaced with a new electrical characteristic module 33 corresponding to the electrical characteristics of the bus 23 conforming to the PCI66 standard and the electrical characteristic compensation module 43, respectively. To do.

  Note that when the bus 23 is upgraded, the function of the board 21 and the processing performed by the bus controller 22 do not change, so the function module 31 and the bus function module 41 do not need to be changed. In general, changing the function module 31 and the bus function module 41 requires a lot of human and time costs, but it can be avoided.

  Further, in the mother board 20 and the board 21, only the logical connection module 42 and the electrical characteristic compensation module 43 of the bus controller 22 and the logical connection module 32 and the electrical characteristic compensation module 33 of the board 21 are replaced. Can support upgrades. In other words, resources can be used efficiently with minimal changes due to the upgrade of the bus 23. Therefore, it is possible to construct the mother board 20 and the substrate 21 which are resource-saving and can be flexibly adapted to changes in the bus width, pin assignment, etc., and are robust to the structure of the bus 23.

  Conventionally, the pin assignment of the bus 23 is electrically fixed, which is a limitation when the bus 23 is upgraded. That is, when the bus 23 is upgraded while maintaining backward compatibility, the pin assignment of the bus 23 after the upgrade is restricted to the pin assignment of the bus 23 before the upgrade.

  However, in the mother board 20 and the board 21 having the above configuration, the logical connection module 42 of the bus controller 22 and the logical connection module 32 of the board 21 are replaced, and the electrical characteristic compensation module 43 and the board 21 of the bus controller 22 are replaced. By exchanging the electrical characteristic compensation module 33, it is possible to easily cope with changes in the pin assignment and the like of the bus 23, and the performance of the bus 23 after the upgrade can be fully exhibited.

It is a figure which shows the structure of an example of the conventional motherboard. It is a figure which shows the structural example of one Embodiment of the motherboard to which this invention is applied. It is a block diagram explaining the structure of the motherboard of FIG. 2 of the state in which the board | substrate 21-1 and the board | substrate 21-2 are each mounted | worn with the connector 24-1 and the connector 24-2. It is a figure which shows the example of the topology of a bus | bath. It is a figure which shows the example of the topology of a bus | bath. It is a figure which shows the example of the topology of a bus | bath. FIG. 5 is a diagram showing a specific example of the bus type topology shown in FIG. 4. It is a figure which shows the specific example of the mesh type topology shown in FIG. It is a figure which shows the structural example of other one Embodiment of the motherboard to which this invention is applied. It is a figure explaining the bus | bath in the case of communicating at high speed. It is a figure explaining the period of the communication performed via a bus | bath between the board | substrates of FIG. It is a figure explaining the bus | bath in the case of performing communication with high responsiveness. It is a figure explaining the period of the communication performed via a bus | bath between the board | substrates of FIG. It is a figure explaining the topology of a bus. It is a figure explaining the topology setting process of the bus controller which sets the topology of the bus | bath of FIG. It is a flowchart explaining the bus | bath topology setting process which a bus controller performs. It is a flowchart explaining the bus | bath topology setting process which the logical connection module of a bus controller performs. It is a flowchart explaining the bus determination process which the logical connection module of a board | substrate performs. It is a figure explaining the change point of a board | substrate and a bus controller in the case of upgrading the bus | bath 23. FIG.

Explanation of symbols

  20 Motherboard, 21 Board, 22 Bus Controller, 23 Bus, 31 Functional Module, 32 Logical Connection Module, 33 Electrical Characteristics Compensation Module, 41 Bus Functional Module, 42 Logical Connection Module, 43 Electrical Characteristics Compensation Module, 61 Bus

Claims (6)

In an information processing board that is mounted on a first information processing board provided with a bus composed of a plurality of connection lines and communicates with a second information processing board that is mounted on the first information processing board,
A decision IC that is an IC (Integrated Circuit) for deciding a connection line to be used for communication with the second information processing board from among the plurality of connection lines that connect itself to the second information processing board; ,
A compensation IC, which is an IC that compensates the electrical characteristics of the connection line determined to be used for communication with the second information processing board by the determination IC ,
The information processing board, wherein the decision IC and the compensation IC are different ICs and are detachable . The compensation IC compensates the electrical characteristics of the connection line by performing impedance matching of the connection line determined to be used for communication with the second information processing board by the determination IC. The information processing board according to claim 1. The said determination IC determines the connection line used for communication with a said 2nd information processing board according to control from the 3rd information processing board which controls the said bus | bath. Information processing board. In an information processing board that controls a bus that is connected to a first information processing board and a second information processing board, wherein a bus composed of a plurality of connection lines is provided,
A connection line used for communication between the first information processing board and the second information processing board is determined from the plurality of connection lines of the bus, and the first information processing board and the second information processing board are determined. A management IC that manages the connection between the information processing boards ;
A compensation IC, which is an IC for compensating the electrical characteristics of the bus ,
The information processing board according to claim 1, wherein the management IC and the compensation IC are different ICs and are detachable . 5. The information processing board according to claim 4, wherein the compensation IC compensates for electrical characteristics of the bus by performing impedance matching of the bus . A first information processing board on which a bus composed of a plurality of connection lines is disposed, and a second information processing board mounted on the first information processing board and communicating with the second information processing board In an information processing system comprising a third information processing board for performing
The first information processing board includes:
A connection line used for communication between the second information processing board and the third information processing board is determined from the plurality of connection lines, and the second information processing board and the third information processing board are determined. Management means for managing the connection between the substrates of
Compensation means for compensating electrical characteristics of the bus;
Transmitting means for transmitting to the third information processing board bus information representing a connection line determined to be used for communication between the second information processing board and the third information processing board by the management means; With
The management means and the transmission means are realized by one detachable IC, and the compensation means is realized by a detachable IC different from the IC,
The third information processing board includes:
A determination IC for determining a connection line used for communication with the second information processing board from the plurality of connection lines of the bus based on the bus information transmitted from the transmission unit ;
A compensation IC, which is an IC that compensates the electrical characteristics of the connection line determined to be used for communication with the second information processing board by the determination IC ,
The information processing system, wherein the determination IC and the compensation IC are different ICs and are detachable .

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