KR20070008914A - Cmos image sensor - Google Patents

Abstract

A CMOS image sensor is provided to reduce optical crosstalk by using as a diffusion barrier layer a material with a good optical absorption characteristic. A diffusion barrier layer having a thickness of 200~1100 angstroms is formed on a first insulation layer pattern and a first metal interconnection pattern, avoiding diffusion of a metal material of the first metal interconnection pattern. An interlayer dielectric(270) is formed on the diffusion barrier layer. An etch stop layer(272) having a thickness of 200~1100 angstroms is formed on the interlayer dielectric. A second insulation layer pattern is formed on the etch stop layer, having a second unevenness part exposing the upper surface of the etch stop layer. The second unevenness part is filled with a second metal interconnection pattern. The diffusion barrier layer or the etch stop layer is made of a silicon oxynitride layer. The first and the second metal interconnection patterns are made of copper.

Description

CMOS Image Sensor

1 is a cross-sectional view illustrating an optical crosstalk phenomenon of a CMOS image sensor according to the prior art;

2 is a cross-sectional view of a double film for explaining ideal conditions of the anti-reflection film;

3A to 3I are cross-sectional views illustrating a method of manufacturing a CMOS image sensor according to an exemplary embodiment of the present invention;

4A and 4B are graphs showing the refractive index and the absorption coefficient of the diffusion barrier covering the metal wiring of the CMOS image sensor according to the prior art and the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a CMOS image sensor including a metal wiring and a method for manufacturing the same.

CMOS Image Sensor (CIS) is a device that converts optical images into electrical signals using CMOS manufacturing technology. Recently, demand for image sensors such as digital still cameras, mobile phone cameras, and door phone cameras has exploded, and demand for CMOS image sensor devices has also increased exponentially.

The CMOS image sensor is composed of a transistor, a resistor, a capacitor, and the like, and wiring is indispensable for implementing the CMOS image sensor on a semiconductor substrate. Because wiring plays a role in transmitting electrical signals, electrical resistance must be low, economical and reliable.

As CMOS image sensors become more integrated, the width and thickness of wiring become thinner and the size of contact holes becomes smaller. As the size of the device becomes smaller, the metal wiring resistance increases. In the CMOS image sensor device having a small pattern of 0.13 μm or less, it is difficult to form a metal wiring using aluminum (Al). Therefore, it is preferable to use copper (Cu) having a relatively low resistivity and good electromigration characteristics as the metal wiring material.

On the other hand, since copper diffuses very quickly with respect to silicon (Si) and silicon oxide (SiO ₂ ), a barrier metal film and a diffusion barrier layer for preventing copper diffusion should be formed on the surface of the copper pattern. The barrier metal film is formed on the side and bottom of the copper pattern, and the diffusion barrier film is formed on the upper surface of the copper pattern.

1 is a cross-sectional view illustrating a phenomenon in which light incident on a general CMOS image sensor causes optical crosstalk due to multiple reflections.

Referring to FIG. 1, photodiodes 110a and 110b, a floating diffusion region 111, a gate oxide film 112, and a transfer gate 114 are disposed on a semiconductor substrate 100. The lower insulating layer 120 covering the entire semiconductor substrate 100 is disposed, and the first diffusion barrier layer 134 is disposed on the lower insulating layer 120. A contact (not shown) for electrical connection is disposed between the transfer gate 114 and the first copper wiring pattern 150a.

A first insulating layer pattern 140a having a first trench for electrically connecting a contact is disposed on the first diffusion barrier layer 134 and is disposed along a profile of an inner surface of the first trench. The barrier metal film pattern 144a is disposed. The first copper wiring pattern 150a is disposed in the first barrier metal film pattern 144a.

The second diffusion barrier 164 and the interlayer insulating layer 170 are sequentially disposed on the first insulating layer pattern 140a and the first copper wiring pattern 150a, and the etch stop layer 172 is disposed on the interlayer insulating layer 170. Is placed. A via contact (not shown) for electrical connection is disposed between the first copper wiring pattern 150a and the second copper wiring pattern 190a.

The second insulating layer pattern 180a having the trench is disposed on the etch stop layer 172, and the second barrier metal layer pattern 184a is disposed along the profile of the inner surface of the second trench. The second copper wiring pattern 190a is disposed in the second barrier metal film pattern 184a.

The second diffusion barrier 164 and the etch stop layer 172 have a high etching selectivity with respect to the first insulating layer pattern 140a, the interlayer insulating layer 170, and the second insulating layer pattern 180a, and can prevent diffusion of copper. Silicon nitride (SiN). The second diffusion barrier 164 and the etch stop layer 172 made of silicon nitride are formed to have a thickness of about 300 to 1000 kPa in order to prevent copper from diffusing and to function normally as an etch stop layer. It is preferable.

However, since silicon nitride is good as an etch stopper film, but optically has low absorption rate and does not transmit light well, light enters between the first copper wiring pattern 150a and the second copper wiring pattern 190a. In this case, the plurality of photodiodes 110b enter the neighboring photodiode 110b through multiple reflections of the second diffusion barrier 164 and the etch stop layer 172. As optical crosstalk due to such multiple reflections occurs, it causes confusion in the reproduction of the optical image by the CMOS image sensor.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a metal wiring, a method of forming the same, a CMOS image sensor, and a method of manufacturing the same, which can minimize optical crosstalk.

In order to achieve the above technical problem, the present invention provides a metal wiring. The metal wiring is formed on a lower insulating film formed on a substrate, a first insulating film pattern formed on the lower insulating film, and having at least one first recessed portion, a first metal wiring pattern filling the first recessed portion, a first insulating film pattern, and a first metal. A diffusion barrier layer formed on the interconnection pattern to prevent diffusion of the metal material of the first metal interconnection pattern, an interlayer insulating layer formed on the diffusion barrier layer, an etch stop layer formed on the interlayer insulation layer, and an etch stop layer formed on the etch stop layer And a second insulating film pattern having a second recessed portion exposing the top surface of the film, and a second metal wiring pattern filling the second recessed portion. The diffusion barrier or etch stop layer may be a silicon oxynitride layer.

The first and second metal interconnection patterns may be made of copper, and include a diffusion barrier layer and an etch stop layer for etching prevention and diffusion prevention. The diffusion barrier and the etch stop layer may be formed to a thickness of 200 to 1100 kPa.

The present invention provides a CMOS image sensor. The CMOS image sensor comprises a substrate on which semiconductor elements including optical elements are formed, a first insulating film pattern formed on the substrate and having at least one first recess, a first metal wiring pattern filling the first recess, and a first metal wiring pattern An interlayer insulating film formed on the interlayer insulating film, a second insulating film pattern formed on the interlayer insulating film, and having at least one second recessed portion, a second metal wiring pattern filling the second recessed portion, and an upper surface of the first metal wiring pattern and a lower surface of the interlayer insulating film It is formed at the interface between, and may include a diffusion barrier film made of silicon oxynitride.

The first and second metal wiring patterns may be made of copper, and may further include an etch stop layer formed at an interface between the bottom surface of the second metal wiring pattern and the top surface of the interlayer insulating layer. The etch stop layer may be made of silicon oxynitride.

The present invention provides a method of forming a metal wiring. The method includes forming a lower insulating film on a semiconductor substrate, forming a first insulating film having a first recessed portion on the lower insulating film, forming a first metal wiring pattern filling the first recessed portion, and first metal wiring. Forming a diffusion barrier layer on the pattern and the first insulating layer pattern, forming an interlayer dielectric layer on the diffusion barrier layer, forming an etch stop layer on the interlayer dielectric layer, exposing an etch stop layer upper surface on the etch stop layer Forming a second insulating film having a second recessed portion, and forming a second metal wiring pattern filling the second recessed portion. The diffusion barrier or etch stop layer may be a silicon oxynitride layer.

The first and second metal wiring patterns may be made of copper.

The present invention provides a method of manufacturing a CMOS image sensor. The method comprises the steps of: forming a semiconductor device comprising an optical element on a semiconductor substrate; forming a first insulating film having at least one first recess on the semiconductor substrate; forming a first metal wiring pattern filling the first recess; Forming an interlayer insulating film on the first metal wiring pattern, forming a second insulating film having at least one second recessed portion on the interlayer insulating film, and forming a second metal wiring pattern filling the second recessed portion. And forming a diffusion barrier layer formed at an interface between an upper surface of the first metal wiring pattern and a lower surface of the interlayer insulating layer, the diffusion barrier layer having an etch selectivity with the interlayer insulating layer. The diffusion barrier layer may be a silicon oxynitride layer.

The first and second metal wiring patterns may be made of copper.

The diffusion barrier layer made of silicon oxynitride has a high light absorption coefficient, thereby minimizing the multiple reflection of external light by the diffusion barrier layer to reduce optical crosstalk in the CMOS image sensor.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided so that the disclosure may be made thorough and complete, and to fully convey the spirit of the invention to those skilled in the art. In the drawings, the thicknesses of films and regions are exaggerated for clarity. Also, if it is mentioned that the film is on another film or substrate, it may be formed directly on the other film or substrate or a third film may be interposed therebetween.

2 is a cross-sectional view of a double film for explaining the antireflection film conditions.

Referring to FIG. 2, when light 50 in the air is incident on a double film in which the first film material 52 and the second film material 54 are bonded, the first film material 52 may serve as an anti-reflection film. The following [Equation 1] and [Equation 2] must be satisfied.

[Equation 1]

n ₁ d = 1/4 λ

[Equation 2]

n ₁ = (n ₂ ) ^1/2

[Equation 1] is for obtaining the thickness of the first film quality 52 which is an anti-reflection film for the incident light 50, and [Equation 2] is for obtaining an appropriate refractive index of the first film quality 52. n ₁ is the refractive index of the first film 52, n ₂ is the refractive index of the second film 54, d is the thickness of the first film 52 and λ is the wavelength of the incident light 50.

The refractive index of the first film 52 coated on the second film 54 by the above formulas is an ideal refractive index when it is an approximation of the square root of the refractive index of the second film 54 in the lower layer. The thickness of the first film 52 is a value obtained by dividing the refractive index of the first film 52 by a value corresponding to 1/4 of the wavelength of the incident light 50. As shown in [Equation 1], The wavelength of the light 50 is changed.

The wavelength range of visible light varies depending on the person, but is generally 380 to 770 nm. In the embodiment of the present invention, the wavelength of incident light 50 is set to 250 to 850 nm which is slightly wider than visible light. The second film 54 is copper, and the refractive index n ₂ is 0.14.

When copper is used as the second film 54, the refractive index and thickness of the first film 52, which is ideal for visible light, are 0.37 and 2,568 to 5,203 kPa, respectively. However, this thickness has a problem that is too thick to be applied to a semiconductor device.

However, if the first film 52 has a suitable thickness and is replaced with a film having an ideal refractive index, optical crosstalk, which is a problem of the prior art, may be completely eliminated. On the other hand, the first film 52 should be a film containing nitrogen (nitride) to solve the optical crosstalk, and also serve as an etch stop film like silicon nitride. Therefore, a silicon oxynitride film having a refractive index n ₁ of 1.89 to 2.46 in the wavelength range of 250 to 850 nm may be considered as the first film 52 that can replace the silicon nitride film.

In the embodiment of the present invention, the refractive index of the silicon oxynitride used as the first film 52 is very large compared to the ideal refractive index, but has a thickness of about 254 to 1,124 빛 for light in the wavelength range of 250 to 850 nm. It is appropriate. That is, by covering the copper metal wiring, which is the second film quality, with silicon oxynitride, reflection of the incident light 50 can be reduced. Accordingly, optical crosstalk of the CMOS image sensor can be suppressed.

3A to 3I are cross-sectional views illustrating a metal wiring forming method of a CMOS image sensor according to an exemplary embodiment of the present invention.

Referring to FIG. 3A, an isolation layer (not shown) is formed on the semiconductor substrate 200 to define an active region. The photodiode 210 and the floating diffusion region 211 are formed on a predetermined portion of the surface of the active region, and a transistor is formed on the semiconductor substrate 200 between the photodiode 210 and the floating diffusion region 211. The transistor includes a gate oxide film 212 and a transfer gate 214 formed on the semiconductor substrate 200.

Referring to FIG. 3B, a lower insulating film 220 is formed to cover the semiconductor substrate 200 on which the transistor is formed. The lower insulating film 220 is preferably formed of a transparent material. Examples of the transparent material that can be used for the lower insulating film 220 include silicon oxide-based materials.

Meanwhile, a contact hole (not shown) is formed in the lower insulating layer 220 to expose a portion of the upper surface of the transfer gate 214 of the transistor by a general photoresist (PR) process. A lower barrier metal film (not shown) is formed to a thickness of 100 to 500 Å along the profile of the side and bottom of the contact hole and the upper surface of the lower insulating film 220. The lower barrier metal film is a film formed to prevent the metal from diffusing into the lower insulating film 220 during the metal deposition process. The lower barrier metal film may be formed of, for example, a tantalum nitride film (TaN) or a titanium nitride film (TiN).

The lower metal layer is formed by depositing titanium (Ti) or tungsten (W) on the lower barrier metal layer to fill the contact hole. Titanium or tungsten can be formed using a chemical vapor deposition method or a sputtering method.

The lower metal layer and the lower barrier metal film are polished by a chemical mechanical polishing method until the surface of the lower insulating film 220 is exposed to form a lower contact (not shown) filling the contact hole.

Referring to FIG. 3C, a first metal oxide film 232 is formed on the lower insulating film 220. The first metal antioxidant layer 232 may be formed of, for example, silicon nitride or silicon carbide (SiC). The first metal antioxidant film 232 is a film formed to prevent the upper surface of the lower contact from being oxidized during the subsequent oxygen (O ₂ ) inflow process. The first metal oxide film 232 is preferably formed thinner than 30 kPa. Since the first metal anti-oxidation film 232 is formed of a material having low light transmittance, when it is formed too thick, it is difficult for light to reach the photodiode 210 interposed on the semiconductor substrate 200, so that the performance of the image sensor device is improved. Worse

A first diffusion barrier 234 may be formed on the first metal oxide layer 232 and used as an etch stop layer in a subsequent etching process to prevent the metal from diffusing into the interlayer insulating layer. The first diffusion barrier 234 may be silicon oxynitride. The first diffusion barrier layer 234 is deposited to a thickness of about 200 to 1,100 Å. More preferably, the first diffusion barrier 234 is deposited to a thickness of 500 to 700 kPa.

Conventionally, a silicon nitride film is used for the purpose of diffusion prevention and etch stop, and at this time, the silicon nitride film should be deposited at about 1,000 GPa or more. However, in the present invention, even when the silicon oxynitride film is deposited with a thickness of about 60% (that is, about 600 GPa) than the silicon nitride film, the purpose of diffusion prevention and etching prevention can be achieved in the same manner.

As described above in FIG. 2, the silicon oxynitride film is a material having a high light absorption coefficient. However, the light absorption coefficient of the silicon oxynitride film is not only dependent on the thickness of the film, but also closely related to the film quality. That is, in the case of forming the silicon oxynitride film with the same thickness, the silicon oxynitride film having a good chemical composition ratio and having a low content of impurities (Carbon, Hydrogen, etc.) has less reflection and has a high absorption coefficient.

On the other hand, since the silicon oxynitride is formed to a lower thickness than the silicon nitride used as a conventional etch stop film, there is also an effect of reducing parasitic capacitance (parasitic capacitance). In addition, since most of the light is absorbed, optical crosstalk reaching neighboring photodiodes through multiple reflections is also reduced. Thus, the performance of the CMOS image sensor is improved.

A first insulating film (not shown) is formed on the first diffusion barrier film 234. The first insulating film may be formed of a silicon oxide-based material. Predetermined portions of the first insulating layer, the first diffusion barrier 234, and the first metal oxide layer 232 are etched to form a first trench 242 that exposes an upper surface of a lower contact (not shown).

A first barrier metal film 244 is formed to a thickness of 100 to 500 kV along the profile of the inner surface of the first trench 242 and the upper surface of the first insulating film pattern 240a. The first barrier metal film 244 is a film formed to prevent diffusion of the copper component into the first insulating film pattern 240a during the copper deposition process.

Referring to FIG. 3D, a first copper layer 250 is formed on the first barrier metal film 244 to fill the first trench 242. The first copper layer 250 may be formed by first depositing a copper seed by a sputtering method and then by an electroplating method. Alternatively, it may be formed by an electroless plating method.

Referring to FIG. 3E, the first barrier metal layer 244 existing on the upper surface of the first copper layer 250 and the first insulating layer pattern 240a may be exposed so that the upper surface of the first insulating layer pattern 240a is exposed. Is polished by a chemical mechanical polishing method to form a first copper wiring pattern 250a electrically connected to the lower contact. In this case, the first barrier metal layer 244 remains on the sidewalls and the bottom of the first trench 242 to form the first barrier metal layer pattern 244a. That is, since the first barrier metal film pattern 244a is formed between the first copper wiring pattern 250a and the first insulating film pattern 240a, the copper used as the first copper wiring pattern 250a is the first. Diffusion to the insulating film pattern 240a can be prevented.

A second metal oxide film 262 and a second diffusion barrier 264 are sequentially formed on the first insulating film pattern 240a and the first copper wiring pattern 250a. The second metal oxide film 262 is formed to prevent the surface of the first copper wiring pattern 250a from being oxidized. The second metal oxide film 262 is formed by depositing silicon nitride or silicon carbide to a thickness of 30 GPa or less. In addition, the second diffusion barrier layer 264 is formed by depositing silicon oxynitride to a thickness of 200 to 1,100 GPa. Preferably, it is formed by depositing to a thickness of 500 to 700Å.

Referring to FIG. 3F, an interlayer insulating layer 270 is formed on the second diffusion barrier layer 264. The interlayer insulating layer 270 may be formed of a silicon oxide material.

An etch stop layer 272 is formed on the interlayer insulating layer 270. The etch stop layer 272 may be formed of a silicon oxynitride layer. The etch stop layer 272 is formed to a thickness of 300 to 1,000 kPa, preferably 500 to 700 kPa. The second insulating layer 280 is formed on the etch stop layer 272. The second insulating layer 280 may be formed of a silicon oxide material.

Referring to FIG. 3G, a first preliminary portion in which the second diffusion barrier layer 264 is exposed by continuing to etch predetermined portions of the second insulating layer 280, the etch stop layer 272, and the interlayer insulating layer 270 by a general photoresist process. Form a via hole (not shown).

The second insulating layer 280 is etched to expose the etch stop layer 272 to pattern the second preliminary trench (not shown) and the second insulating layer pattern 280a via the first preliminary via hole. The etch stop layer 272 and the second diffusion barrier layer 264 exposed to the bottom surfaces of the second preliminary trench and the first preliminary via hole, respectively, are etched, and then the second metal oxide layer 262 is etched. By the etching process, a first via hole (not shown) partially exposing the top surface of the first copper wiring pattern 250a and a first trench 282 passing through the first via hole are formed.

In the present embodiment, a via first damascene process has been described as an example, but generally, a process of forming the first via hole and the second trench 282 may be included in the present embodiment.

Referring to FIG. 3H, a second barrier metal layer 284 is formed along the profile of the first via hole, the second trench 282, and the second insulating layer pattern 280a. The second barrier metal film 284 is a film for preventing the copper component from diffusing into the second insulating film pattern 280a and the interlayer insulating film 270 during the subsequent copper deposition process. The second barrier metal film 284 may be formed of, for example, a composite film in which a tantalum nitride film is deposited on a tantalum film Ta, a tantalum nitride film, or a tantalum film.

Copper is deposited to fill the second trench 282 and the first via hole to form a second copper layer 290. The second copper layer 290 may be formed by first depositing a copper seed by a sputtering method and then by an electroplating method.

Referring to FIG. 3I, the second copper layer 290 and the second barrier metal layer 284 are polished by a chemical mechanical polishing method until the upper surface of the second insulating layer pattern 280a is exposed to form a second trench ( 282 and a copper wiring (not shown) filled with copper are formed only in the first via hole. That is, the copper wiring includes a first via contact (not shown) electrically connected to the first copper wiring pattern 250a and a second copper wiring pattern 290a connecting the first via contact to each other.

In this case, the second barrier metal film 284 remains on the sidewalls and the bottom of the second trench 282 to form the second barrier metal film pattern 284a. That is, since the second barrier metal film pattern 284a is formed between the second copper wiring pattern 290a, the second insulating film pattern 280a, and the interlayer insulating film 270, the second copper wiring pattern 290a is used. The copper material used may be prevented from diffusing into the second insulating film pattern 280a and the interlayer insulating film 270.

The processes of FIGS. 3E to 3I are repeatedly performed to fabricate a CMOS image sensor having a multilayer copper interconnection structure consisting of contacts and interconnections.

4A and 4B are graphs showing refractive indexes and absorption coefficients of a second diffusion barrier layer 264 covering an upper portion of a copper wiring of a CMOS image sensor manufactured according to the related art and an embodiment of the present invention. The thickness of the plasma-enhanced (PE) -silicon nitride of the conventional film is 900 kPa, and the thickness of the silicon oxynitride according to the embodiment of the present invention is 600 kPa.

Referring to FIG. 4A, the refractive index of the light incident on PE-silicon nitride and silicon oxynitride (50 in FIG. 2) is shown. Comparing the materials of the two films, the refractive index of silicon oxynitride is lower than that of PE-silicon nitride over the full wavelength of incident light. Accordingly, the use of silicon oxynitride reduces the degree of refraction of incident light than that of PE-silicon nitride, thereby reducing the probability of multiple reflections by the incident light.

Referring to FIG. 4B, absorption coefficients according to wavelengths of light (50 in FIG. 2) incident on PE-silicon nitride and silicon oxynitride are illustrated. Comparing the materials of the two films, it can be seen that the absorption coefficient of silicon oxynitride is higher over the propagation field of incident light compared to PE-silicon nitride. Accordingly, the use of silicon oxynitride reduces the probability of multiple reflections by the incident light as it absorbs more incident light than using PE-silicon nitride.

As described above, according to the present invention, the CMOS image sensor having a characteristic of reducing optical crosstalk by replacing a material of a film covering the lower and upper surfaces of the metal wiring of the CMOS image sensor with a material that is less likely to reflect multiple reflections by light. Can be provided.

Claims (12)

A lower insulating film formed on the substrate; A first insulating film pattern formed on the lower insulating film and having at least one first recessed portion; A first metal wiring pattern filling the first recess; A diffusion barrier layer formed on the first insulating layer pattern and the first metal interconnection pattern and preventing diffusion of a metal material of the first metal interconnection pattern; An interlayer insulating film formed on the diffusion barrier film; An etch stop layer formed on the interlayer insulating layer; A second insulating layer pattern formed on the etch stop layer and having a second recessed portion exposing an upper surface of the etch stop layer; And And a second metal wiring pattern filling the second recess, The diffusion barrier layer or the etch stop layer is a metal wiring, characterized in that the silicon oxynitride film. The method of claim 1, The diffusion barrier has a thickness of 200 to 1,100 kPa. The method of claim 1, And the first and second metal wiring patterns are made of copper. The method of claim 1, The etch stop layer is metal wiring, characterized in that the thickness of 200 to 1,100Å. A substrate on which semiconductor devices, including an optical device, are formed; A first insulating film pattern formed on the substrate and having at least one first recessed portion; A first metal wiring pattern filling the first recess; An interlayer insulating film formed on the first metal wiring pattern; A second insulating film pattern formed on the interlayer insulating film and having at least one second recessed portion; A second metal wiring pattern filling the second recess; And And a diffusion barrier layer formed at an interface between the upper surface of the first metal wiring pattern and the lower surface of the interlayer insulating layer, wherein the diffusion barrier layer is formed of silicon oxynitride. The method of claim 5, And the first and second metal wiring patterns are made of copper. The method of claim 5, And an etch stop layer formed at an interface between the lower surface of the second metal wiring pattern and the upper surface of the interlayer insulating layer. The method of claim 7, wherein The etch stop layer is CMOS image sensor, characterized in that made of silicon oxynitride. Forming a lower insulating film on the semiconductor substrate; Forming a first insulating film having a first recessed portion on the lower insulating film; Forming a first metallization pattern filling the first recess; Forming a diffusion barrier on the first metal wiring pattern and the first insulating layer pattern; Forming an interlayer insulating film on the diffusion barrier film; Forming an etch stop layer on the interlayer insulating layer; Forming a second insulating layer on the etch stop layer, the second insulating layer having a second recessed portion exposing the top surface of the etch stop layer; And And forming a second metal wiring pattern filling the second recess, wherein the diffusion barrier layer or the etch stop layer is a silicon oxynitride layer. The method of claim 9, And the first and second metal wiring patterns are made of copper. Forming a semiconductor device including an optical device on the semiconductor substrate; Forming a first insulating film having at least one first recessed portion on the semiconductor substrate; Forming a first metallization pattern filling the first recess; Forming an interlayer insulating film on the first metal pattern; Forming a second insulating film having at least one second recessed portion on the interlayer insulating film; And And forming a second metal wiring pattern filling the second recess, wherein the diffusion barrier layer is formed at an interface between an upper surface of the first metal pattern and a lower surface of the interlayer insulating layer and has an etch selectivity. And forming the diffusion barrier layer, wherein the diffusion barrier layer is a silicon oxynitride layer. The method of claim 11, And the first and second metal wiring patterns are made of copper.

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