KR20070003051A - Vpp and vbb pump control circuit of low power semiconductor device - Google Patents

Abstract

A high voltage and base voltage pump control circuit of a low power semiconductor device is provided to solve a latch-up problem caused by increase of a base voltage(VBB) due to coupling capacitance between a high voltage(VPP) and the base voltage, by operating a high voltage pump after decreasing the base voltage enough by operating a low voltage pump in advance during the exit of a power-up operation and K power down mode. A base voltage detector(110) generates a first base voltage enable signal by receiving a power-up signal. An operation detection part(120) generates a second base voltage enable signal having the same voltage level as the first base voltage enable signal when a short power-up operation and a K power down mode are concluded, by receiving the power-up signal and the first base voltage enable signal. A high voltage pump enable control part(130) generates a high voltage enable control signal by receiving the second base voltage enable signal and the power-up signal. A high voltage detector(140) generates a high voltage enable signal by receiving the high voltage enable control signal.

Description

VPP AND VBB PUMP CONTROL CIRCUIT OF LOW POWER SEMICONDUCTOR DEVICE

1 is a circuit diagram of a base voltage (VBB) pump control circuit according to the prior art.

2 is a block diagram of a high voltage (VPP) detector according to the prior art.

3 is a block diagram of the VPP and VBB pump control circuit of the low power semiconductor device according to the present invention.

4 is a circuit diagram of the VPP pump enable controller 130 shown in FIG. 3.

<Description of Major Symbols in Drawing>

110: VBB detector 120: motion detection unit

130: VPP pump enable control unit 140: VPP detector

The present invention relates to a high voltage (VPP) and a base voltage (VBB) pump control circuit of a low power semiconductor device, in particular, VBB voltage by the operation of the VPP pump at the completion of the K Power Down (DPD) mode (Exit) The present invention relates to a high voltage and base voltage pump control circuit of a low power semiconductor device capable of preventing latch-up from occurring as the level rises together.

In general, in a low-power semiconductor device that supplies the core voltage Vcore with the high voltage VPP signal enabled, the power at the time of power-up In the -up period, the high voltage (VPP) is floated (floating), the base voltage (VBB) pump is enabled, and the high-voltage (VPP) pump is operated at the end of the power-up period. In this case, even when the high voltage VPP operates the pump and the base voltage VBB rises due to the coupling capacitance Coupling, the base voltage VBB is already at a low voltage level. The voltage does not go high.

Typically, when the high voltage (VPP) capacitance has more than twice the capacitance of the base voltage (VBB), the base voltage (VBB) is affected by the high voltage (VPP), but the high voltage (VPP) capacitance is the base voltage (VBB) When the size is less than twice the capacitance of, the potential difference is small, and thus is not affected much.

However, when exiting the K power down mode, it is not a long time power-up operation such as power-up, but a short power-up operation of about 1 ms. The high voltage (VPP) pump operates immediately after exiting the K power-down (DPD) mode before the low voltage level reaches the low enough voltage level so that the high voltage (VBB) is raised to a certain level. This is likely to cause latch-up.

Next, the VPP and VBB pump control circuits of the conventional low power semiconductor device will be described with reference to the accompanying drawings and the problems thereof will be described.

1 is a circuit diagram of a VBB pump control circuit according to the prior art.

As shown in FIG. 1, the conventional VBB pump control circuit receives the power-up signal pwrup, inverts the node Nd1, and outputs the inverted node Nd1 by the power-up signal pwrup. The node Nd3 receives a VBB detector 10 generating a first base voltage enable signal VBB_enableb, a signal obtained by receiving a signal of the node Nd1 and the first base voltage enable signal VBB_enableb, and performing a NAND operation. NAND gate (G2) output to the output terminal and the inverter (G3) for inverting the signal of the node (Nd3) and outputs a second ground voltage enable signal (VBB_enableb) to the node (Nd4).

In the power-up period, the power-up signal pwrup has a 'high' state, and the first base voltage enable signal VBB_enableb, which is an output signal of the VBB detector 10, is the power-up signal pwrup. Has a 'low' state. Therefore, the VBB pump control circuit generates the second base voltage enable signal VBB_enableb having a 'low' state in the power-up period, thereby operating the VBB pump.

On the other hand, when exiting the K power-down (DPD) mode, the power-up signal pwrup has a 'low' state, and the first base voltage enable signal, which is an output signal of the VBB detector 10, VBB_enableb) has a 'high' state by the power-up signal pwrup. Accordingly, the VBB pump control circuit generates a second base voltage enable signal VBB_enableb having a 'high' state when exiting the K power down mode, thereby controlling the VBB pump from being operated.

2 is a block diagram of a VPP detector 20 according to the prior art.

As shown in FIG. 2, the conventional VPP detector 20 receives a power-up signal pwrup and generates a high voltage enable signal VPP_enable. In this case, the VPP detector 20 generates a high voltage enable signal VPP_enable having a 'high' state by the power-up signal pwrup having a 'high' state in a power-up period. ) Control the pump from running.

In addition, when exiting the K power down mode, the high-voltage enable signal VPP_enable is generated by the power-up signal pwrup having the low state, thereby generating a high voltage. (VPP) to operate the pump.

However, the VPP and VBB pump control circuits of the conventional low-power semiconductor device having the above-described configuration have the high voltage VPP and the base voltage VBB while the high voltage VPP pump operates when exiting the K power down mode. There is a problem that the latch-up occurs as the voltage level of the base voltage VBB rises due to the coupling capacitance between the circuits.

Therefore, the technical problem to be achieved by the present invention is to operate the ground voltage (VBB) pump first during power-up operation and exit of the K power down mode (DPD) mode to sufficiently satisfy the ground voltage (VBB). By operating the high voltage (VPP) pump after lowering the voltage level, the latch-up generated when the voltage level of the base voltage (VBB) is raised by the coupling capacitance between the high voltage (VPP) and the base voltage (VBB). To solve the problem is to provide a VPP and VBB pump control circuit of a low power semiconductor device.

In order to achieve the above technical problem, the present invention includes a base voltage detector for receiving a power-up signal to generate a first base voltage enable signal; A second base having the same voltage level as the first base voltage enable signal upon receiving the power-up signal and the first base voltage enable signal and completing a short power-up operation and a K power down mode; An operation detector for generating a low voltage enable signal; A high voltage pump enable control unit configured to receive the second base voltage enable signal and the power-up signal to generate a high voltage enable control signal; The present invention provides a high voltage and base voltage pump control circuit for a low power semiconductor device including a high voltage detector for receiving the high voltage enable control signal and generating a high voltage enable signal.

In the present invention, during the power-up operation, the power-up signal has a first voltage level, the first and second base voltage enable signals have a second voltage level, and the high voltage enable signal has a first voltage level. It is characterized by having a voltage level.

In the present invention, upon completion of the K power down (DPD) mode, the power-up signal has a second voltage level, and the first and second base voltage enable signals have a first voltage level, and the high voltage The enable signal has a second voltage level.

In the present invention, the motion detection unit and a first buffer for buffering the power-up signal; A logic unit configured to receive an output signal of the first inverter and the first base voltage enable signal and output a logic operation signal; It is preferable to include a second buffer for buffering the output signal of the logic unit.

In the present invention, the logic unit preferably performs a negative logical operation.

In the present invention, the first buffer and the second buffer is preferably an inverting buffer.

In the present invention, the high voltage pump enable control unit includes a third buffer for inverting and outputting the second base voltage enable signal; A pull-up element for switching the supply voltage to the first node when the output signal of the third buffer has a first voltage level; A first pull-down element for switching the voltage of the first node to a ground voltage when the output signal of the third buffer has a second voltage level; A second pull-down element forming a current path between the first pull-down element and a ground voltage when the power-up signal has a second voltage level; And inverting the signal of the first node to output the high voltage enable control signal and latching the high voltage enable control signal until a next signal is received.

In the present invention, the third buffer is preferably an inverting buffer.

In the present invention, it is preferable that the first pull-down device is a PMOS transistor, and the first and second pull-down devices are NMOS transistors.

In the present invention, the latch unit includes a first inverter connected between the first node and an output terminal for outputting the high voltage enable control signal; It is preferable to include a second inverter for inverting the signal of the output terminal to feed back to the first node.

Hereinafter, the present invention will be described in more detail with reference to Examples. These examples are only for illustrating the present invention, and the scope of protection of the present invention is not limited by these examples.

3 is a block diagram of the VPP and VBB pump control circuit of the low power semiconductor device according to the present invention.

As shown in FIG. 3, the VPP and VBB pump control circuits of the low power semiconductor device according to the present invention receive a power-up signal pwrup and generate a base voltage VBB_enableb to generate a base voltage enable signal VBB_enableb. Receiving the detector 110, the power-up signal pwrup, and the first base voltage enable signal VBB_enableb, the short power-up operation and the completion of the K power-down (DPD) mode are completed. An operation detector 120 generating a second base voltage enable signal VBB_enableb1 having the same voltage level as the first base voltage enable signal VBB_enableb, and the second base voltage enable signal VBB_enableb1. And a high voltage (VPP) pump enable control unit (130) for receiving the power-up signal (pwrup) and generating a high voltage (VPP) enable control signal (pwrup_VPP), and the high voltage (VPP) enable control signal (pwrup_VPP). ) To generate a high voltage enable signal (VPP_enable) And a voltage (VPP) detector 140.

Here, the operation detector 120 receives an inverter G11 for inverting and outputting the power-up signal pwrup, an output signal of the inverter G11, and the first base voltage enable signal VBB_enableb. NAND gate G12 for outputting a logically calculated signal and an inverter G13 for inverting the output signal of the NAND gate G12 and outputting the second base voltage enable signal VBB_enableb1.

First, in the power-up period, the power-up signal pwrup has a 'high' state, and a first base voltage enable signal VBB_enableb, which is an output signal of the VBB detector 110, is the power-up signal ( pwrup) has a 'low' state. In this case, the VBB pump operates because the first base voltage enable signal VBB_enableb is 'low'.

Since the power-up signal pwrup is transmitted through the inverter G11, the signal of the node Nd2 is 'low', and the first base voltage enable signal VBB_enableb is 'low'. The signal of the output node Nd4 of the NAND gate G12 has a 'high' state. Therefore, the second base voltage enable signal VBB_enableb1 output through the inverter G13 becomes 'low'.

In addition, the VPP pump enable control unit 130 is the high voltage (VPP) of the 'high' state because the second base voltage enable signal (VBB_enableb1) is 'low' and the power-up signal (pwrup) is 'high' Generate the enable control signal pwrup_VPP. As a result, the VPP detector 140 generates a high voltage VPP enable signal pwrup_VPP in a 'low' state to control the VPP pump from operating.

On the other hand, when exiting the K power down mode, the power-up signal pwrup has a 'low' state, and the first base voltage enable signal, which is an output signal of the VBB detector 110, VBB_enableb) has a 'high' state by the power-up signal pwrup. At this time, the VBB pump does not operate because the first base voltage enable signal VBB_enableb is 'high'.

Since the power-up signal pwrup is transmitted through the inverter G11, the signal of the node Nd2 is 'high' and the first base voltage enable signal VBB_enableb is 'high'. The signal of the output node Nd4 of the NAND gate G12 has a 'low' state. Therefore, the second base voltage enable signal VBB_enableb1 output through the inverter G13 becomes 'high'.

In addition, the VPP pump enable control unit 130 has a high voltage enable state of 'low' because the second base voltage enable signal VBB_enableb1 is 'high' and the power-up signal pwrup is 'low'. The control signal pwrup_VPP is generated. As a result, the VPP detector 140 generates a high voltage enable signal VPP_enable in a 'high' state to operate the VPP pump.

4 is a circuit diagram of the VPP pump enable controller 130 shown in FIG. 3.

As shown in FIG. 4, the VPP pump enable control unit 130 includes an inverter G21 for inverting and outputting the second base voltage enable signal VBB_enableb1 and an output node Nd12 of the inverter G21. Signal of the output node Nd12 of the inverter G21 and the PMOS transistor MP which switches the power supply voltage VDD to the node Nd13 when the signal of the signal has the first voltage level 'low'. Has a second voltage level 'high', the NMOS transistor MN1 for switching the voltage of the node Nd3 to the ground voltage Vss, and the power-up signal pwrup has a second voltage level. When the signal is 'high', the signals of the node Nd13 and the NMOS transistor MN2 which form a current path between the NMOS transistor MN1 and the ground voltage Vss are inverted. Outputs the high voltage (VPP) enable control signal (pwrup_VPP) and enables the high voltage (VPP) enable agent until a next signal is input; And a latch section (G22 and G23) for latching the signal (pwrup_VPP).

Here, the latch unit receives an inverter G22 connected between the node Nd13 and an output node Nd14 that outputs the high voltage VPP enable control signal pwrup_VPP, and a signal of the output node Nd14. The inverter G23 inverts and feeds back to the node Nd13.

Since the power-up signal pwrup is 'high' and the second base voltage enable signal VBB_enableb1 is 'low' in the power-up period, the VPP pump enable control unit 130 having the above configuration may be configured as the inverter. Since the signal of the node Nd12 through G21 becomes 'high', the PMOS transistor MP is turned off, and all of the NMOS transistors MN1 and MN2 are turned on so that the signal is turned high. Make the signal of node Nd13 'low'. Accordingly, the high voltage VPP enable control signal pwrup_VPP, which is an output signal of the VPP pump enable control unit 130, has a 'high' to control the VPP pump not to operate.

On the other hand, when the power-up signal pwrup is 'low' and the second base voltage enable signal VBB_enableb1 is 'high' at the time of completion of the K power-down (DPD) mode, the inverter ( Since the signal of the node Nd12 through G21 becomes 'low', the PMOS transistor MP is turned on, and all of the NMOS transistors MN1 and MN2 are turned off so that the node is turned off. Make signal of (Nd13) 'high'. Accordingly, the high voltage VPP enable control signal pwrup_VPP, which is an output signal of the VPP pump enable control unit 130, has a 'low' to operate the VPP pump.

In conclusion, the present invention lowers the base voltage (VBB) to a sufficient voltage level by first operating the base voltage (VBB) pump at the time of exiting the power-up operation and the K power-down (DPD) mode. By operating the high voltage (VPP) pump afterwards, the latch-up problem that occurs when the voltage level of the base voltage VBB increases due to the coupling capacitance between the high voltage VPP and the base voltage VBB is solved. It was.

The present invention relates to a DRAM (DRAM) and K power down (DPD) mode scheme using a VDDCLP structure (Scheme for seeing and supplying the VPP signal of the power supply voltage VDD of the core voltage Vcore). It can be used in a semiconductor memory device having a scheme.

As described above, according to the VPP and VBB pump control circuit of the low-power semiconductor device according to the present invention, the base voltage VBB at the time of power-up operation and exit of the K power-down (DPD) mode. ) By first operating the pump to lower the base voltage (VBB) to a sufficient voltage level and then operating the high voltage (VPP) pump, the voltage of the base voltage (VBB) by the coupling capacitance between the high voltage (VPP) and the base voltage (VBB). This can solve the latch-up problem that occurs as the level goes up.

Claims (10)

A base voltage detector for receiving a power-up signal to generate a first base voltage enable signal; A second base having the same voltage level as the first base voltage enable signal upon receiving the power-up signal and the first base voltage enable signal and completing a short power-up operation and a K power down mode; An operation detector for generating a low voltage enable signal; A high voltage pump enable control unit configured to receive the second base voltage enable signal and the power-up signal to generate a high voltage enable control signal; And a high voltage detector configured to receive the high voltage enable control signal and to generate a high voltage enable signal. The method of claim 1, In the power-up operation, the power-up signal has a first voltage level, the first and second base voltage enable signals have a second voltage level, and the high voltage enable signal has a first voltage level. A high voltage and base voltage pump control circuit of a low power semiconductor device, characterized in that. The method of claim 1, Upon completion of the K power down mode, the power up signal has a second voltage level, the first and second base voltage enable signals have a first voltage level, and the high voltage enable signal has a second voltage level. A high voltage and base voltage pump control circuit for a low power semiconductor device, characterized by having two voltage levels. The method of claim 1, The motion detection unit A first buffer for buffering the power-up signal; A logic unit configured to receive an output signal of the first inverter and the first base voltage enable signal and output a logic operation signal; A high voltage and base voltage pump control circuit of a low power semiconductor device comprising a second buffer for buffering the output signal of the logic unit. The method of claim 4, wherein The logic unit is a high voltage and base voltage pump control circuit of a low power semiconductor device performing a negative logic operation. The method of claim 4, wherein The high voltage and base voltage pump control circuit of the low power semiconductor device, wherein the first buffer and the second buffer are inverting buffers. The method of claim 1, The high voltage pump enable control unit A third buffer for inverting and outputting the second base voltage enable signal; A pull-up element for switching the supply voltage to the first node when the output signal of the third buffer has a first voltage level; A first pull-down element for switching the voltage of the first node to a ground voltage when the output signal of the third buffer has a second voltage level; A second pull-down element forming a current path between the first pull-down element and a ground voltage when the power-up signal has a second voltage level; And a latch unit configured to invert the signal of the first node to output the high voltage enable control signal and to latch the high voltage enable control signal until a next signal is received. The method of claim 7, wherein The third buffer is a high voltage and base voltage pump control circuit of the low power semiconductor device which is an inverting buffer. The method of claim 7, wherein Wherein said first pull-down device is a PMOS transistor and said first and second pull-down devices are NMOS transistors. The method of claim 7, wherein The latch unit comprises: a first inverter connected between the first node and an output terminal for outputting the high voltage enable control signal; A high voltage and base voltage pump control circuit for a low power semiconductor device comprising a second inverter for inverting the signal of the output terminal and feeding back to the first node.

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