KR100728555B1 - Apparatus for Supplying Power-up Signal in Semiconductor Integrated Circuit - Google Patents

Abstract

The present invention provides a power up signal supply apparatus of a semiconductor integrated circuit for separately supplying a power up signal to a register block and an internal block.

The power up signal supply apparatus of the semiconductor integrated circuit of the present invention generates the resistor power up signal from an external voltage and supplies the resistor power up signal supply means to the register block and the external voltage and the internal power according to whether the device enters the deep power down mode. And an internal power up signal supply means for sensing a voltage and generating an internal power up signal according to the result and supplying the internal power up signal to the internal block.

According to the present invention, the power consumption is reduced while the deep power down mode of the semiconductor integrated circuit has the advantage that the data of the register block is maintained.

Semiconductor Integrated Circuits, Deep Power-Down, Power-Up Signals

Description

Apparatus for Supplying Power-up Signal in Semiconductor Integrated Circuit

1 is a block diagram of a power up signal supply apparatus according to the prior art;

2 is a block diagram of a power up signal supply device power up signal supply device of a semiconductor integrated circuit according to the present invention;

3 is a configuration diagram of a power-up signal supply apparatus of a semiconductor integrated circuit according to an embodiment of the present invention;

4 is a block diagram of a register power-up signal supply means according to another embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

2/210/312: External Voltage Sense 2/302: External Voltage Driver

10/310: voltage detector 14/314: ambient voltage detector

16/316: core voltage detector 20/320: power-up signal generator

200/201: resistor power-up signal supply means

220: delay 300: internal power-up signal supply means

The present invention relates to a power up signal supply device for a semiconductor integrated circuit, and more particularly, to a power up signal supply device for a semiconductor integrated circuit for separately supplying a power up signal to a register block and an internal block.

In general, a semiconductor memory device is divided into an active state and a stand-by state to operate. When the semiconductor memory device is in an active state, circuits inside the chip output or output necessary information to the outside. On the other hand, when the semiconductor memory device is in the standby state, all current paths are cut off except for the minimum circuit that can enter the active state in order to minimize the power consumption inside the chip. However, if the semiconductor memory device maintains the standby state for a long time, unnecessary power is consumed because current is continuously consumed by the circuit which is enabled to enter the active state. Therefore, in the related art, a method of entering a deep power down mode that cuts off most current paths of the chip to minimize standby current in order to reduce standby current consumption is used. Also, in deep power down mode, a method of sinking all power supplies of the internal circuits to ground voltage (VSS) is used to prevent unnecessary operation by power remaining in the internal circuits of the chip.

The power up signal is a signal instructing supply of power in the semiconductor integrated circuit. At the beginning of the operation of the semiconductor integrated circuit, internal voltages such as peripheral circuit operating voltage (Vperi, hereinafter peripheral voltage), core circuit operating voltage (core Vcore and below), and high potential voltage (VPP) are in the generation stage and thus reach a desired level. You are in an unsuccessful state. At this time, if the internal voltages are used for the operation of the circuit, there is a risk of malfunction. Therefore, a general semiconductor integrated circuit uses the internal voltages to ensure a stable power supply after enabling the power up signal.

Hereinafter, a power up signal supply apparatus according to the related art will be described with reference to FIG. 1.

1 is a block diagram of a power up signal supply apparatus according to the related art, and shows an example in which a peripheral voltage Vperi and a core voltage Vcore are used as internal voltages.

As shown, the power up signal supply apparatus according to the related art has an external voltage driver 2 for driving an external voltage Vext only when an input deep power down signal DPD is disabled, and the external voltage ( The output signal of the voltage sensing unit 10 and the voltage sensing unit 10 which detects Vext, the peripheral voltage Vperi, and the core voltage Vcore and outputs the result as a level signal is inputted with a power-up signal pwrup. ) Is configured with a power-up signal generator 20 for generating and outputting.

At this time, the voltage detector 10 detects the voltage driven by the external voltage driver 2 and outputs the result as a level signal, and detects the peripheral voltage Vperi and A peripheral voltage detector 14 outputting a result as a level signal and a core voltage detector 16 for sensing the core voltage Vcore and outputting the result as a level signal.

In addition, the power-up signal generator 20 may output each level signal output from the external voltage detector 12, the peripheral voltage detector 14, and the core voltage detector 16 of the voltage detector 10. From the NAND gate 22 and the NAND gate 22 which output a low level signal only when all three signals are high level as input, and output a high level signal in other cases. And an inverter 24 which inverts the level of the input signal and outputs the power-up signal pwrup.

The operation of the power-up signal supply device configured as described above is as follows. The external voltage Vext may be implemented by an external supply power source VDD and the like, and is set to mean that the external voltage Vext is not limited to any one of power applied to the outside of the semiconductor integrated circuit.

The peripheral voltage detector 14 of the voltage detector 10 outputs a high level signal when the peripheral voltage Vperi of a predetermined value or more is input. Similarly, the core voltage detector 16 outputs a high level signal when the core voltage Vcore of a predetermined value or more is input. When the deep power down signal DPD is disabled, the external voltage driver 2 drives the external voltage Vext and transfers the external voltage detector 12 to the external voltage detector 12. Thereafter, the external voltage detector 12 outputs a high level signal when the voltage input from the external voltage driver 2 is greater than or equal to a predetermined value.

In this case, a high level signal is input to all three input terminals of the NAND gate 22 of the power-up signal generator 20. The NAND gate 22 then outputs a low level signal. The inverter 24 then inverts the low level signal and outputs a high level power up signal pwrup.

The high level of the power up signal pwrup means that power is supplied to a semiconductor integrated circuit to which the power up signal supply device belongs. That is, since the peripheral voltage Vperi and the core voltage Vcore have a predetermined value or more out of an initial state, the power-up signal pwrup is enabled, and thus the semiconductor integrated circuit is brought into an operating state. .

At this time, when the semiconductor integrated circuit reaches the deep power down mode and the deep power down signal DPD is enabled and input to the external voltage driver 2, the external voltage driver 2 blocks the external voltage Vext. . Accordingly, the external voltage detector 12 outputs a low level signal, and the power up signal pwrup output from the power up signal generator 20 is disabled.

That is, when the semiconductor integrated circuit enters a deep power down mode for minimizing power consumption, the power-up signal supply device disables the power-up signal pwrup to stop the power supply inside the semiconductor integrated circuit. It is to make it.

As described above, all current paths in the semiconductor integrated circuit are blocked in the deep power down mode. Therefore, when the semiconductor integrated circuit enters the deep power down mode, all data stored in the register block that stores the initial data of the semiconductor integrated circuit chip, such as a mode register set, is lost. However, data of register blocks such as the mode register set (MRS) must be maintained. According to the related art, there is a problem in that the deep power down mode cannot be used to hold the data of the register block, and the register data cannot be held to prevent power consumption of the semiconductor integrated circuit.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and there is a technical problem to provide a power-up signal supply apparatus for a semiconductor integrated circuit capable of maintaining data of a register even in a deep power-down mode.

In accordance with one aspect of the present invention, there is provided a power up signal supply apparatus for a semiconductor integrated circuit, including: a register power up signal supply means for generating a resistor power up signal from an external voltage and supplying the resistor power up signal to a register block; And an internal power up signal supply means for sensing the external voltage and the internal voltage according to whether the device enters the deep power down mode and generating an internal power up signal according to the result and supplying the internal power up signal to the internal block. .

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

2 is a block diagram of a power up signal supply apparatus of a semiconductor integrated circuit according to the present invention.

The power up signal supply apparatus of the semiconductor integrated circuit of the present invention generates a resistor power up signal pwrup_r from an external voltage and senses the resistor power up signal supply means 200 for supplying the resistor power up signal to the register block and the external voltage and the internal voltage. As a result, the internal power-up signal supply means 300 generates an internal power-up signal pwrup_i and supplies it to the internal block.

The register power up signal supply means 200 generates and supplies the register power up signal pwrup_r to the register block regardless of entry or exit of the deep power down mode. However, the internal power up signal supply means 300 disables the internal power up signal pwrup_i when entering the deep power down mode, and enables the internal power up signal pwrup_i when exiting the deep power down mode. Supply to the inner block.

In this case, the register block means at least one register that stores initial data of the semiconductor integrated circuit chip, including a mode register set (MRS).

3 is a configuration diagram of a power-up signal supply apparatus of a semiconductor integrated circuit according to an exemplary embodiment of the present disclosure, and illustrates an example in which a peripheral voltage Vperi and a core voltage Vcore are used as internal voltages. The internal voltage is not limited to the peripheral voltage Vperi and the core voltage Vcore as shown, and a high potential voltage VPP may be used, but for convenience of description, only the peripheral voltage Vperi and the core voltage Vcore are shown. It was. In addition, as in the related art, the external voltage Vext may be realized by an external supply power source VDD, but it may be realized by any voltage applied from the outside of the semiconductor.

The power-up signal supply device of the present invention generates a resistor power-up signal pwrup_r from an external voltage Vext and supplies the resistor power-up signal supply means 200 and the external voltage Vext to the peripheral block. And an internal power up signal supply means 300 for sensing the voltage Vperi and the core voltage Vcore and generating the internal power up signal pwrup_i and supplying the internal power up signal pwrup_i to the internal block.

Here, the resistor power up signal supply means 200 includes an external voltage detector 210 that detects the external voltage Vext, generates a resistor power up signal pwrup_r, and delivers the resistor power up signal to the register block.

In addition, the internal power-up signal supply means 300 is an external voltage driver 302 for driving the external voltage Vext only when the input deep power down signal is disabled, the external voltage Vext, The internal power-up signal pwrup_i receives the output signal of the voltage detector 310 and the voltage detector 310 that detects the peripheral voltage Vperi and the core voltage Vcore and outputs the result as a level signal. ) Is configured to generate and output a power up signal generator 320.

The voltage detector 310 detects the voltage driven by the external voltage driver 302 and detects the external voltage detector 312 and the peripheral voltage Vperi that output the result as a level signal. A peripheral voltage detector 314 outputs a level signal and a core voltage detector 316 for detecting the core voltage Vcore and outputting the result as a level signal.

In addition, the power-up signal generator 320 is a level signal output from the external voltage detector 312, the peripheral voltage detector 314, and the core voltage detector 316 of the voltage detector 310. The NAND gate 322 outputs a low level signal only when all three signals are at a high level, and the NAND gate 322 outputs a high level signal, and the level of the signal input from the NAND gate 322. The inverter 324 is inverted and output as the internal power-up signal pwrup_i.

The operation of the power-up signal supply device configured as described above is as follows.

The external voltage detector 210 of the register power-up signal supplying means 200 outputs a high level register power-up signal pwrup_r to the register block when the external voltage Vext of a predetermined value or more is input. The register power-up signal pwrup_r transmitted to the register block supplies the signal constantly regardless of the state in which the semiconductor integrated circuit to which the power-up signal supply device belongs, that is, the active mode, the standby mode, or the deep power-down mode. Accordingly, data is maintained in the register block as long as the external voltage Vext is applied to the power-up signal supply device.

However, the internal power up signal supply means 300 is affected by the deep power down signal DPD. The peripheral voltage detector 314 of the voltage detector 310 outputs a high level signal when the peripheral voltage Vperi of a predetermined value or more is input. Similarly, the core voltage detector 316 outputs a high level signal when the core voltage Vcore above a predetermined value is input. When the deep power down signal DPD is disabled, the external voltage driver 302 drives the external voltage Vext and transfers the external voltage detector 312 to the external voltage detector 312. Thereafter, the external voltage detector 312 outputs a high level signal when the voltage input from the external voltage driver 302 is greater than or equal to a predetermined value.

In this case, a high level signal is input to all three input terminals of the NAND gate 322 of the power-up signal generator 320. The NAND gate 322 then outputs a low level signal. Thereafter, the inverter 324 inverts the low level signal and outputs a high level internal power up signal pwrup_i to the internal block.

However, when the semiconductor integrated circuit reaches the deep power down mode and the deep power down signal DPD is enabled and input to the external voltage driver 302, the external voltage driver 302 blocks the external voltage Vext. Accordingly, the external voltage detector 312 outputs a low level signal, and the internal power up signal pwrup_i output from the power up signal generator 320 is disabled.

As such, when the semiconductor integrated circuit enters a deep power down mode for minimizing power consumption, the internal power up signal supplying means 300 disables the internal power up signal pwrup_i, thereby preventing the internal power up signal of the semiconductor integrated circuit. The power supply made in the inner block is stopped to reduce power consumption of the semiconductor integrated circuit. However, the register power up signal supply means 200 supplies the register power up signal pwrup_r to the register block to maintain the data of the register block regardless of whether the semiconductor integrated circuit enters the deep power down mode. will be.

4 is a block diagram of a register power-up signal supply means according to another embodiment of the present invention.

The illustrated resistor power up signal supply means 201 is configured by adding a delay 220 for delaying the resistor power up signal pwrup_r output from the external voltage detector 210 shown in FIG.

Since the circuit configuration of the register power up signal supply means 200 of FIG. 2 is simpler than the internal power up signal supply means 300, the time for which the register power up signal pwrup_r is input to the register block is increased. The power-up signal pwrup_i may be faster than the time input to the inner block, and thus the circuit operation may not be performed normally. As such, when the enable time of the register power-up signal pwrup_r is earlier than the enable time of the internal power-up signal pwrup_i, the register power-up signal pwrup_r is transferred to the register block. The delayer 200 may synchronize the register power up signal pwrup_r and the internal power up signal pwrup_i by delaying the register power up signal pwrup_r for a predetermined time.

As such, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without changing the technical spirit or essential features thereof. Therefore, the above-described embodiments are to be understood as illustrative in all respects and not as restrictive. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

The power up signal supply apparatus of the semiconductor integrated circuit of the present invention described above includes means for supplying a power up signal to a register block and a means for supplying a power up signal to an internal block, respectively, thereby reducing power consumption in the deep power down mode. While maintaining the data of the register block.

Claims (10)

Register power up signal supply means for generating a resistor power up signal from an external voltage and supplying it to a register block; And Internal power up signal supply means for detecting the external voltage and the internal voltage according to whether or not to enter the deep power down mode, and generating and supplying an internal power up signal to an internal block according to the result; Power up signal supply apparatus of a semiconductor integrated circuit comprising a. The method of claim 1, The register power up signal supply means is An external voltage detector configured to sense the external voltage and generate and output a resistor power up signal; Power up signal supply apparatus of a semiconductor integrated circuit comprising a. The method of claim 1, And the internal voltage is at least one of an ambient voltage (Vperi), a core voltage (Vcore), and a high potential voltage (VPP). The method according to claim 1 or 2, The register power up signal supply means is A delay unit for delaying a resistor power-up signal output from the external voltage detector for a predetermined time; Apparatus for supplying power up signals to a semiconductor integrated circuit further comprising. Register power up signal supply means for generating a resistor power up signal using an external voltage and supplying the resistor power up signal to the register block; And Internal power up signal supply means for sensing the external voltage and the internal voltage and generating an internal power up signal according to the result and supplying the internal power up signal to the internal block; And a resistor power up signal output from the resistor power up signal supply means is always enabled when the external voltage is supplied regardless of entry or exit of the deep power down mode. Signal supply. The method according to claim 1 or 5, The internal power up signal supply means generates and outputs an disabled internal power up signal when entering the deep power down mode, and generates and outputs an enabled internal power up signal when exiting the deep power down mode. A power up signal supply device for a semiconductor integrated circuit. The method of claim 5, The register power up signal supply means is An external voltage detector configured to sense the external voltage and generate and output a resistor power up signal; Power up signal supply apparatus of a semiconductor integrated circuit comprising a. The method according to claim 5 or 7, The register power up signal supply means is A delay unit for delaying a resistor power-up signal output from the external voltage detector for a predetermined time; Apparatus for supplying power up signals to a semiconductor integrated circuit further comprising. The method according to claim 1 or 5, And the register block comprises at least one register for storing initial data of the semiconductor integrated circuit. The method according to claim 1 or 5, And the register block comprises a mode register set (MRS).

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