KR20070003035A - Method for fabricating semiconductor device - Google Patents
Method for fabricating semiconductor device Download PDFInfo
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- KR20070003035A KR20070003035A KR1020050058761A KR20050058761A KR20070003035A KR 20070003035 A KR20070003035 A KR 20070003035A KR 1020050058761 A KR1020050058761 A KR 1020050058761A KR 20050058761 A KR20050058761 A KR 20050058761A KR 20070003035 A KR20070003035 A KR 20070003035A
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- gate insulating
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- 238000000034 method Methods 0.000 title claims abstract description 40
- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 26
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 26
- 238000004519 manufacturing process Methods 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 4
- 238000000059 patterning Methods 0.000 claims abstract description 3
- 229910018072 Al 2 O 3 Inorganic materials 0.000 claims description 16
- 239000007789 gas Substances 0.000 claims description 16
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 13
- 239000002131 composite material Substances 0.000 claims description 6
- 238000000231 atomic layer deposition Methods 0.000 claims description 5
- 239000000203 mixture Substances 0.000 claims description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 4
- 125000004430 oxygen atom Chemical group O* 0.000 claims description 4
- 229920002120 photoresistant polymer Polymers 0.000 claims description 4
- 239000002994 raw material Substances 0.000 claims description 4
- 239000012495 reaction gas Substances 0.000 claims description 4
- 150000004706 metal oxides Chemical class 0.000 claims description 3
- 229910003902 SiCl 4 Inorganic materials 0.000 claims description 2
- 229910002367 SrTiO Inorganic materials 0.000 claims description 2
- 229910010413 TiO 2 Inorganic materials 0.000 claims description 2
- 229910052782 aluminium Inorganic materials 0.000 claims description 2
- VOITXYVAKOUIBA-UHFFFAOYSA-N triethylaluminium Chemical compound CC[Al](CC)CC VOITXYVAKOUIBA-UHFFFAOYSA-N 0.000 claims 1
- 239000010408 film Substances 0.000 description 70
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 4
- 230000002093 peripheral effect Effects 0.000 description 3
- 238000000151 deposition Methods 0.000 description 2
- 230000009977 dual effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 230000005641 tunneling Effects 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 230000005465 channeling Effects 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 125000000753 cycloalkyl group Chemical group 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- ZFAYZXMSTVMBLX-UHFFFAOYSA-J silicon(4+);tetrachloride Chemical compound [Si+4].[Cl-].[Cl-].[Cl-].[Cl-] ZFAYZXMSTVMBLX-UHFFFAOYSA-J 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- LXEXBJXDGVGRAR-UHFFFAOYSA-N trichloro(trichlorosilyl)silane Chemical compound Cl[Si](Cl)(Cl)[Si](Cl)(Cl)Cl LXEXBJXDGVGRAR-UHFFFAOYSA-N 0.000 description 1
- JLTRXTDYQLMHGR-UHFFFAOYSA-N trimethylaluminium Chemical compound C[Al](C)C JLTRXTDYQLMHGR-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28194—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Chemical & Material Sciences (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
도1 내지 도4는 본 발명의 바람직한 반도체 장치의 제조방법을 나타내는 공정단면도.1 to 4 are process cross-sectional views showing a preferred method of manufacturing a semiconductor device of the present invention.
* 도면의 주요부분에 대한 부호설명 ** Explanation of Signs of Major Parts of Drawings *
31 : 기판 32 : 제1 게이트절연막31
33 : 감광막 34 : 제2 게이트절연막33: photosensitive film 34: second gate insulating film
본 발명은 반도체 장치의 제조방법에 관한 것으로, 특히 반도체 장치의 듀얼게이트 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a dual gate of a semiconductor device.
최근 반도체 집적도의 증가로 원하는 트랜지스터의 성능을 얻기 위해서는 게이트절연막의 두께가 얇아야 한다.Recently, in order to obtain a desired transistor performance due to an increase in semiconductor integration, the thickness of the gate insulating layer must be thin.
그러나, 게이트절연막의 두께가 너무 얇아지게 되면 게이트절연막을 통해 터 널링(tunneling)에 의한 누설전류가 커지는 문제가 발생한다.However, when the thickness of the gate insulating film becomes too thin, a problem arises in that the leakage current due to tunneling through the gate insulating film becomes large.
종래에는 반도체 장치의 트랜지스터를 제조할 때에 게이트 유전물질로 실리콘산화막을 사용하고 있다. 그런데 반도체 집적도의 증가로 원하는 트랜지스터 성능을 얻기 위해서는 게이트절연막의 두께가 얇아야 한다. Conventionally, a silicon oxide film is used as a gate dielectric material when manufacturing a transistor of a semiconductor device. However, in order to obtain desired transistor performance due to an increase in semiconductor integration, the thickness of the gate insulating layer must be thin.
즉, 트랜지스터의 구동전류 확보, 쇼트채널(short channel) 영향의 감소, 적절한 문턱전압의 확보를 위해서는 Tox 가 작아야 한다. 그러기 위해서는 게이트절연막의 두께를 줄이는 것이 유일한 방안이다.That is, Tox must be small to secure the driving current of the transistor, to reduce the influence of a short channel, and to secure an appropriate threshold voltage. The only way to do this is to reduce the thickness of the gate insulating film.
그러나, 게이트절연막으로 사용되는 산화막의 두께가 35Å 이하로 얇아지게 되면 터널링 현상에 이한 누설전류가 증가하며, 물리적인 두께의 감소로 인해 게이트 산화막의 신뢰성 문제가 발생하게 된다.However, when the thickness of the oxide film used as the gate insulating film becomes thinner than 35 kV, the leakage current due to the tunneling phenomenon increases and the reliability of the gate oxide film occurs due to the decrease in the physical thickness.
즉, 게이트 패턴으로 생기는 캐패시터가 원하는 전하량을 확보할 수 있어야 하는데, 게이트절연막의 두께가 얇을 경우 유전막이 절연파괴되어 게이트 유전막으로써 역할을 하지 못하게 되는 것이다.That is, the capacitor generated by the gate pattern should be able to secure a desired amount of charge. If the thickness of the gate insulating film is thin, the dielectric film is insulated and destroyed so that it cannot serve as the gate dielectric film.
본 발명은 고집적 반도체 장치의 모스트랜지스터의 게이트절연막을 얇게 형성하면서도 유전특성이 좋아 누설전류 특성이 향상된 모스트랜지스터의 제조방법을 제공함을 목적으로 한다.SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a MOS transistor, in which a gate insulating film of a MOS transistor of a highly integrated semiconductor device is thinly formed and the dielectric property is good and the leakage current characteristic is improved.
본 발명은 제1 영역과 제2 영역을 구분되는 기판상의 상기 제1 영역에만 실리콘산화막을 제1 게이트절연막으로 형성하는 단계;상기 제1 영역상의 실리콘산화막과 상기 제2 영역상의 기판상에 실리콘산화막+금속산화막으로 된 복합유전막을 제2 게이트절연막으로 형성하는 단계; 상기 제2 게이트절연막상에 도전막으로 게이트전극막을 형성하는 단계; 및 상기 제1 및 제2 게이트절연막 및 상기 게이트전극막을 패터닝하여 게이트 패턴을 형성하는 단계를 포함하는 반도체 장치의 제조방법을 제공한다.According to another aspect of the present invention, there is provided a method of forming a silicon oxide film as a first gate insulating film on only the first region on a substrate that separates a first region and a second region; Forming a composite dielectric film made of a + metal oxide film as a second gate insulating film; Forming a gate electrode film as a conductive film on the second gate insulating film; And patterning the first and second gate insulating films and the gate electrode film to form a gate pattern.
본 발명은 게이트절연막으로 실리콘산화막만 사용하던 것을 실리콘산화막+알루미늄산화막을 적용하여 유전상수를 높게 하여 유전막의 물리적인 두께를 증가시킴으로서 누설전류 문제 및 두께 재현성 문제를 해결하였다.The present invention solves the leakage current problem and the thickness reproducibility problem by increasing the physical thickness of the dielectric film by increasing the dielectric constant by applying the silicon oxide film + aluminum oxide film to the silicon oxide film as the gate insulating film.
즉, 본 발명은 듀얼 게이트절연막을 형성하는 방법으로 제1 두께를 가지는 제1 게이트절연막은 이전과 동일하게 퍼니스를 이용하여 막질 특성이 우수한 고온의 실리콘산화막을 증착하고, 제2 두께를 가지는 제2 게이트절연막은 원자층 증착법 공정을 이용하여 실리콘산화막+알루미늄산화막을 적용함으로서 게이트절연막의 물리적 두께는 증가시키면서 Tox는 감소시킴으로서 종래기술의 문제를 해결하였다.(실리콘산화막 유전상숭:3.9, 알루미늄산화막 유전상수 :9)That is, the present invention is a method of forming a dual gate insulating film, the first gate insulating film having a first thickness is deposited a high temperature silicon oxide film having excellent film quality characteristics using a furnace as before, and the second having a second thickness The gate insulating film solves the problem of the prior art by increasing the physical thickness of the gate insulating film by reducing the Tox while increasing the physical thickness of the gate insulating film by using an atomic layer deposition process. : 9)
또한, 본 발명은 제2 게이트절연막으로 사용하는 실리콘산화막과 알루미늄산화막은 원자층증착법으로 유전막을 증착함에 있어, 1개의 챔버를 첫번째 유전막인 실리콘산화막과 두번째 유전막인 알루미늄산화막을 연속증착해 이를 한 사이클로 하는 복합유전막으로 제조한다.In the present invention, in the silicon oxide film and the aluminum oxide film used as the second gate insulating film, the dielectric film is deposited by atomic layer deposition. It is prepared as a composite dielectric film.
복합유전막은 [(SiO2)x+(Al2O3)y]z와 같이 증착하는데, 이 때 x와 y를 적적하게 조합하여 (SiO2)x(Al2O3)y 유전막의 조정비를 최적화시키며, z를 조절하여 유전막의 두께를 조절한다. 이 때 증착순서는 (SiO2)x(Al2O3)y 또는 (Al2O3)x(SiO2)y의 순서로 할 수 있다.The composite dielectric film is deposited as [(SiO 2 ) x + (Al 2 O 3 ) y] z, where x and y are properly combined to adjust the adjustment ratio of the (SiO 2 ) x (Al 2 O 3 ) y dielectric film. Optimize, and adjust the thickness of the dielectric film. At this time, the deposition order may be (SiO 2 ) x (Al 2 O 3 ) y or (Al 2 O 3 ) x (SiO 2 ) y.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조하여 설명하기로 한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.
도1 내지 도4는 본 발명의 바람직한 반도체 장치의 제조방법을 나타내는 공정단면도이다. 특히 반도체 메모리 장치에서 셀영역과 주변영역에 형성되는 서로 다른 두께를 가지는 게이트절연막을 형성하는 방법을 중심으로 나타낸 것이다.1 to 4 are process cross-sectional views showing a preferred method of manufacturing a semiconductor device of the present invention. In particular, a method of forming a gate insulating film having a different thickness formed in a cell region and a peripheral region in a semiconductor memory device will be described.
도1에 도시된 바와 같이, 본 발명의 바람직한 반도체 장치의 제조방법은 기판(31)상에 제1 두께의 제1 게이트절연막을 실리콘산화막으로 10 ~ 100Å의 두께를 가지도록 형성한다. 여기서 실리콘산화막은 열적 성장으로 형성시키게 된다.As shown in FIG. 1, in the preferred method of manufacturing a semiconductor device of the present invention, a first gate insulating film having a first thickness is formed on the
이어서, 도2에 도시된 바와 같이, 셀영역(Cell)을 가릴수 있도록 감광막 패턴(33)을 형성한다.Subsequently, as illustrated in FIG. 2, the
이어서 도3에 도시된 바와 같이, 습식각공정을 통해 주변여역(Peri) 지역의 실리콘산화막을 제거한다. 이 때 습식각공정은 BOE나 HF를 사용한다.Subsequently, as shown in FIG. 3, the silicon oxide film in the peripheral region (Peri) region is removed through a wet etching process. At this time, the wet etching process uses BOE or HF.
이어서 셀영역(Cell)에 있던 감광막 패턴(33)을 H2SO4+H2O2를 이용하여 제거 한다. Subsequently, the
이어서 도4에 도시된 바와 같이, 셀영역(Cell)과 주변영역(Peri)에 원차층증착방법을 이용하여 제2 두께를 가지는 제2 게이트절연막으로 (SiO2)x(Al2O3)y을 형성한다.Next, as shown in FIG. 4, (SiO 2 ) x (Al 2 O 3 ) y as a second gate insulating film having a second thickness in the cell region Cell and the peripheral region Peri by using a layer deposition method. To form.
이 때 공정압력은 0.1Torr ~ 10Torr, 공정온도는 25 ~ 500도에서 진행한다.At this time, the process pressure is 0.1 Torr ~ 10 Torr, process temperature is carried out at 25 ~ 500 degrees.
또한, 한개의 챔버에서 동일한 조건으로 [(SiO2)x+(Al2O3)y]z 복합(composite)유전막을 10 ~ 100Å 두께로 증착한다.In addition, a [(SiO 2 ) x + (Al 2 O 3 ) y] z composite dielectric film is deposited to a thickness of 10 to 100 kHz under the same conditions in one chamber.
[(SiO2)x+(Al2O3)y]z에서 z=1 일때를 한 사이클로 정의하여 한 사이클내에서 x와 y의 횟수는 조성비 최적화 및 결정화 방지를 위해 서로 다른 값을 가질 수 있다. 즉, x= 1~5, y=1~5의 범위내에서 조절 할 수 있다.By defining z = 1 in [(SiO 2 ) x + (Al 2 O 3 ) y] z as one cycle, the number of x and y in one cycle may have different values to optimize composition ratio and prevent crystallization. That is, it can adjust within the range of x = 1-5, y = 1-5.
마지막으로 z의 반복횟수로 복합유전막의 전체 두께가 결정되며, 다음과 같은 원자층증착법에 의한 나도 믹스된(nano-mixed) (SiO2)x(Al2O3)y 유전막이 형성된다.Finally, the total thickness of the composite dielectric film is determined by the number of repetitions of z, and a nano-mixed (SiO 2 ) x (Al 2 O 3 ) y dielectric film is formed by the following atomic layer deposition method.
나도 믹스된(nano-mixed) (SiO2)x(Al2O3)y 유전막을 형성하는 방법을 자세히 살펴보면, 먼저 실리콘산화막의 소스인 SiCl4(TCS, TetraChloride Silicon) 또는 Si2Cl6(HCD, HexaChloroDisilane)을 0.1 ~ 10초 동안 반응 챔버내에 흘려주어 반도체 기판의 표면에 Si 원료 물질이 흡착되도록 한다.(a)Looking at how to form a nano-mixed (SiO 2 ) x (Al 2 O 3 ) y dielectric film, I first found SiCl 4 (TCS, TetraChloride Silicon) or Si 2 Cl 6 (HCD), the source of silicon oxide. , HexaChloroDisilane) is flowed into the reaction chamber for 0.1-10 seconds to adsorb the Si raw material on the surface of the semiconductor substrate.
이어서 원자층을 형성한 소스 이외의 미반응 소스를 제거하기 위해 N2 또는 Ar 가스를 0.1 ~ 10초간 플로우시킨다.(b)Subsequently, N 2 or Ar gas is flowed for 0.1 to 10 seconds to remove an unreacted source other than the source on which the atomic layer is formed. (B)
다음으로 반응가스인 H2O 가스를 0.1 ~ 10초간 플로우시켜 Si 원자층위에 산소 원자층이 흡착되어 실리콘산화막이 형성되도록 한다.(c)Next, H 2 O gas, which is a reaction gas, is flowed for 0.1 to 10 seconds so that an oxygen atom layer is adsorbed on the Si atomic layer to form a silicon oxide film. (C)
이어서 미반응 H2O 가스를 제거하기 위해 N2 또는 Ar 가스를 0.1 ~ 10초간 플로우시킨다.(d)Subsequently, N 2 or Ar gas is flowed for 0.1 to 10 seconds to remove unreacted H 2 O gas. (D)
이어서 알루미늄 소스인 Tri Methyl Aluminum(TMA, Al(CH3)3))을 0.1 ~ 5초간 반응 챔버내에 흘려주어 실리콘산화막위에 Al 원료 물질이 흡착되도록 한다.(e)Subsequently, an aluminum source, Tri Methyl Aluminum (TMA, Al (CH 3 ) 3 )), is flowed into the reaction chamber for 0.1 to 5 seconds to adsorb the Al raw material onto the silicon oxide film.
이어서 원자층을 제외한 미반응 소스를 제거하기 위해 N2 또는 Ar 가스를 0.1 ~ 10초간 플로우시킨다.(f)Subsequently, N 2 or Ar gas is flowed for 0.1 to 10 seconds to remove the unreacted source except the atomic layer. (F)
다음으로 반응가스인 H2O 가스를 0.1 ~ 10초간 플로우시켜 알루미늄원자층 위에 산소 원자층이 흡학되어 Al2O3막이 형성되도록 한다.(g)Next, H 2 O gas, which is a reaction gas, is flowed for 0.1 to 10 seconds so that an oxygen atom layer is sucked on the aluminum atom layer to form an Al 2 O 3 film. (G)
이어서 미반응 H2O 가스를 제거하기 위해 N2 또는 Ar 가스를 0.1 ~ 10초간 플로우시킨다.(h)The N 2 or Ar gas is then flowed for 0.1-10 seconds to remove unreacted H 2 O gas. (H)
조성비를 맞추기 위해 전술한 공정에서 (a)~(d)공정을 연속적으로 1 ~ 5회 진행할 수 있으며, (e)~(h)를 연속적으로 1 ~ 5회 진행할 수 있다. 이렇게 하면, (SiO2)x(Al2O3)y 유전막의 x와 y를 결정할 수 있고, 이 과정을 한 사이클로 하여 원하는 만큼 사이클을 진행시키면 원하는 두께의 (SiO2)x(Al2O3)y 유전막을 얻을 수 있는 것이다.In order to match the composition ratio, in the above-described process, the steps (a) to (d) may be continuously performed 1 to 5 times, and (e) to (h) may be continuously performed 1 to 5 times. This, (SiO 2) x (Al 2 O 3) y it is possible to determine the dielectric layer of x and y, the cycloalkyl which the process when conducted a cycle any number of desired thickness (SiO 2) x (Al 2 O 3 You can get a dielectric film.
이상에서 살펴본 바와 같이, (SiO2)x(Al2O3)y 유전막을 제2 게이트절연막으로 형성함으로써, 종래에 실리콘산화막으로만 게이트절연막을 사용할 때보다, 유전상수도 높으면서 실리콘산화막과 유사한 박막특성을 얻을 수 있으며, 구동전류 확보, 채널효과감소, 적절한 문턱전압확보를 위해 Tox를 원하는 값까지 낮춘, 특성좋은 게이트절연막을 얻을 수 있게 되는 것이다.As described above, by forming the (SiO 2 ) x (Al 2 O 3 ) y dielectric film as the second gate insulating film, a thin film characteristic similar to that of the silicon oxide film with a higher dielectric constant than the conventional gate insulating film using only the silicon oxide film is known. In order to secure the drive current, reduce the channel effect, and secure the appropriate threshold voltage, the Tox can be lowered to a desired value, thereby obtaining a gate insulating film having excellent characteristics.
여기서는 실리콘산화막+알루미늄산화막을 사용하였으나, 알루미늄산화막 대신 HfO2, ZrO2, Ta2O5, TiO2, SrTiO3와 같은 보다 높은 유전상수를 가지는 물질을 적용할 수 있다.In this case, a silicon oxide film + aluminum oxide film is used, but a material having a higher dielectric constant such as HfO 2 , ZrO 2 , Ta 2 O 5 , TiO 2 , and SrTiO 3 may be used instead of the aluminum oxide film.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
본 발명에 의해서 구동전류 확보, 채널효과감소, 적절한 문턱전압확보를 위해 Tox를 원하는 값까지 낮춘, 특성좋은 게이트절연막을 얻을 수 있게 되었다.According to the present invention, it is possible to obtain a gate insulating film having a characteristic that lowers Tox to a desired value in order to secure driving current, reduce channel effects, and secure an appropriate threshold voltage.
또한, 게이트절연막의 물리적인 두께를 충분히 높게 유지할 수 있어, 채널링에 의한 누설전류 특성을 확보할 수 있으며, 물리적인 두께 감소로 인해 발생하는 게이트절연막의 신뢰성 문제를 해결할 수 있다.In addition, since the physical thickness of the gate insulating film can be maintained sufficiently high, leakage current characteristics due to channeling can be secured, and reliability problems of the gate insulating film caused by the physical thickness reduction can be solved.
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