KR20070002251A - Non-volatile memory device and method for manufacturing the same - Google Patents

Abstract

A nonvolatile memory apparatus and its manufacturing method are provided to increase the coupling rate by rising volume of an insulation layer connected to a floating gate electrode. A substrate(100) has an active region and a field region that are alternatively arranged in a first direction. A tunnel oxide layer pattern is formed on the active region of the substrate. A floating gate electrode(114b) is formed on the tunnel oxide layer pattern and has a U-shaped isolation pattern shape. An insulation layer(118) is formed on an upper surface, inside and outside, a front side, and a back side of the floating gate electrode and an upper surface of the field region. A control gate electrode(123a) is formed on the insulation layer to be extended to a second direction perpendicular with the first direction.

Description

Non-volatile memory device and method for manufacturing the same

1 is a perspective view of a nonvolatile memory device according to an embodiment of the present invention.

2 to 10 are perspective views of a nonvolatile memory device according to an embodiment of the present invention.

11 to 15 are top plan views of a nonvolatile memory device according to an embodiment of the present invention.

16 is a cross-sectional view of a nonvolatile memory device cut in a first direction according to an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

100 substrate 102 pad oxide film pattern

104: first hard mask pattern 105: trench for device isolation

106: first preliminary isolation pattern 107: second preliminary isolation pattern

107a: device isolation layer pattern 108: active region

110 opening 112 tunnel oxide film pattern

114: first conductive film 114a: floating gate electrode film

114b: Floating gate electrode 115: Sacrificial film

115a: sacrificial film pattern 116 photoresist pattern

118 dielectric film 123 second conductive film

123a: control gate electrode

The present invention relates to a nonvolatile memory device and a method of manufacturing the same, and more particularly, to a nonvolatile memory device and a method of manufacturing the same that can increase the coupling ratio.

Nonvolatile memory devices include EEPROM (Electrically Erasable and Programmable ROM) or flash memory capable of electrically inputting and outputting data. Among them, the flash memory device has a structure for electrically controlling input and output of data by using F-N tunneling or channel hot electron injection.

The flash memory device generally has a stack structure in which a tunnel oxide layer, a floating gate, a dielectric layer, and a control gate are sequentially stacked. Examples of flash memory devices having such a stack structure are disclosed in US Pat. No. 6,153,469 (issued to Yun et al), US Pat. No. 6,455,374 (issued to Lee et al), and the like.

The flash memory device performs programming by applying a voltage to a control gate to inject or extract charges to the floating gate. At this time, the voltage transferred from the control gate to the floating gate can sufficiently reduce the voltage loss by improving the coupling ratio. Here, the coupling coefficient R is expressed as in Equation 1 below.

R = C _ONO / (C _ONO + C _TO )

(Wherein C _ONO represents the capacitance of the dielectric film and C _TO represents the capacitance of the tunnel oxide film pattern)

In addition, the capacitance C of the dielectric film 19 is expressed by Equation 2 below.

C = (ε × A) / T

(Wherein ε represents the dielectric constant of the dielectric film, A represents the area of the dielectric film, and T represents the thickness of the dielectric film)

Accordingly, the coupling ratio may be increased by increasing the area of the dielectric layer 19 or reducing the thickness of the dielectric layer 19. However, although the structure of the floating gate is modified to expand the area of the dielectric layer, there are some limitations in obtaining a desired level of coupling ratio. Therefore, various methods for obtaining the desired coupling ratio are still under study.

On the other hand, the process of forming the flash memory device of the stack structure is a step of forming a tunnel oxide film pattern, a floating gate electrode film, a dielectric film and a control gate electrode film on the substrate, and patterning the control gate electrode film, dielectric film and floating gate electrode It includes. That is, the gate structure may be completed by first patterning the control gate layer and subsequently patterning the dielectric layer and the floating gate pattern using the same mask.

However, in recent flash memory devices, as the level of the dielectric film increases, the etching thickness of the thin film for patterning the control gate electrode film is greatly changed for each region, and the etching thickness of the thin film is also very thick. However, when the control gate electrode film is patterned, etching is excessively performed at a specific part, that is, a part where the thickness of the control gate electrode film is thin. Subsequently, when the floating gate electrode is etched, the excessively etched portion is etched to the surface of the substrate, thereby causing an active fitting phenomenon. The unit device formed in the region where the active fitting is generated may have an operation failure or poor operation characteristics. Therefore, the occurrence of the active fitting adversely affects the yield of the semiconductor device and the reliability of the semiconductor device.

Accordingly, a first object of the present invention is to provide a nonvolatile memory device capable of increasing a coupling ratio.

It is a second object of the present invention to provide a method of manufacturing the nonvolatile memory device.

In order to achieve the above-described first object, a nonvolatile memory device according to an embodiment of the present invention may include a substrate having an active region and a field region extending in a first direction and repeatedly arranged with each other, and on the active region of the substrate. A tunnel oxide layer pattern formed on the tunnel oxide layer, a floating gate electrode formed on the tunnel oxide layer pattern, and having a U-shaped isolation pattern shape, and an upper surface, an inner and outer side surface, a front surface, a rear surface, and an upper portion of the floating gate electrode. And a control gate electrode extending in a second direction perpendicular to the first direction on the dielectric layer formed on a surface thereof.

A method of manufacturing a nonvolatile memory device according to an embodiment of the present invention in order to achieve the above-described second object, first by repeatedly forming a trench element isolation film protruding from the substrate and extending in the first direction to repeatedly The active area and the field area are arranged. A tunnel oxide film pattern is formed on the substrate. A floating gate electrode having a U-shaped isolation pattern shape is formed on the tunnel oxide layer pattern. A dielectric layer is formed on the upper surface, the inner and outer side surfaces, the front surface, the rear surface, and the upper surface of the field region of the floating gate electrode. Next, a control gate electrode is formed on the dielectric layer and extends in a second direction perpendicular to the first direction.

According to the above method, by forming a floating gate electrode having a U-shaped isolated pattern shape first, a dielectric film may be formed on the top surface, the inner and outer side surfaces, the front surface, the rear surface, and the top surface of the field region of the floating gate electrode. . Therefore, a higher coupling ratio can be obtained by expanding the area of the effective dielectric film as compared with the prior art.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a perspective view of a nonvolatile memory device according to an embodiment of the present invention.

Referring to FIG. 1, a substrate 100 having an active region and a field region extending in a first direction and repeatedly arranged to each other is provided. The field region is provided with a trench isolation trench and a device isolation layer pattern filling the inside of the trench for trench isolation.

The tunnel oxide layer pattern 112 is formed on the active region of the substrate 100.

A floating gate electrode 114b is formed on the tunnel oxide layer pattern 112 and has an U-shaped isolation pattern.

A dielectric layer 118 is formed on the upper surface, the inner and outer side surfaces, the front surface, the rear surface, and the upper surface of the field region of the floating gate electrode 114b. That is, the dielectric layer 118 is formed on the entire surface except for the bottom of the floating gate electrode 114b.

The line-shaped control gate electrode 123a extends in the second direction perpendicular to the first direction on the dielectric layer 118. The control gate electrode 123a has a shape in which a doped polysilicon pattern 120a and a metal or metal silicide pattern 122a are stacked.

The line width of the control gate electrode 123a is wider than the width of the floating gate electrode 114b in the second direction. In addition, the control gate electrode 123a has a shape completely surrounding the floating gate electrode 114b.

The second hard mask pattern 124a is provided on the control gate electrode 123a.

As described, in the nonvolatile memory device according to the present invention, the deposition area of the dielectric film in contact with the floating gate electrode is greatly increased. Therefore, it has a high coupling ratio compared to the conventional nonvolatile memory device.

2 to 10 are perspective views of a nonvolatile memory device according to an embodiment of the present invention. 11 through 16 are top plan views of a nonvolatile memory device in accordance with an embodiment of the present invention. 17 is a cross-sectional view of a nonvolatile memory device cut in a first direction according to an embodiment of the present invention.

Referring to FIG. 2, a pad oxide film (not shown) is formed on a substrate 100 made of a semiconductor material such as silicon. The pad oxide layer may be formed by oxidizing a surface of the substrate or by depositing silicon oxide through a chemical vapor deposition process. The pad oxide film is formed to a thickness of 10 to 100 GPa. The pad oxide film is provided to prevent direct contact between the hard mask film formed thereafter and the substrate.

Silicon nitride is deposited on the pad oxide layer to form a hard mask layer (not shown). The hard mask layer not only serves as a mask pattern for forming a device isolation trench through a subsequent process, but also creates an opening for forming a floating gate electrode. Therefore, the hard mask layer should be formed thicker than the target floating gate electrode thickness. Since the hard mask film may be partially consumed during the subsequent cleaning and polishing process, the hard mask film should be formed thicker as the thickness of the film consumed during the process to the thickness of the target floating gate electrode. More specifically, the hard mask layer is formed to be 100 to 3000 microns thicker than the target floating gate electrode.

Next, a photoresist pattern is formed through the photolithography process to selectively expose the device isolation region, and the hard oxide layer and the pad oxide layer are etched using the photoresist pattern as an etch mask, thereby forming the pad oxide layer pattern 102 and the first hard mask pattern 104. ). The first hard mask pattern 104 has a line shape extending in a first direction across the substrate. In addition, a line width of the first hard mask pattern 104 and an interval between the first hard mask patterns 104 are substantially the same.

Using the first hard mask pattern 104 as an etching mask, the substrate 100 is etched to form a trench 105 for device isolation. In this embodiment, the device isolation trench 105 has a fine line width of 90 nm or less.

Thereafter, a trench inner wall oxide layer (not shown) is formed to cure damage to the substrate generated during the etching process for forming the device isolation trench 105 and to prevent leakage current. The process of forming the trench inner wall oxide film may be omitted to simplify the process.

An isolation layer (not shown) is formed to completely fill the inside of the isolation trench 105. The isolation layer for device isolation may be formed by depositing silicon oxide. The insulating layer for device isolation may be formed through a chemical vapor deposition process, a high density chemical vapor deposition process, a spin-on glass process, or the like.

Next, the first preliminary device isolation layer pattern 106 is formed by polishing the device isolation insulating layer so that the first hard mask pattern 104 is exposed. The active region 108 and the field region of the substrate are formed by the first preliminary isolation layer pattern 106.

3 and 11, the exposed first hard mask pattern 104 is removed through a wet etching process. Specifically, first, an oxide or particles formed on the first hard mask pattern 104 are cleaned using a hydrofluoric acid (HF) diluent. Next, the first hard mask pattern 104 is etched using an etching solution containing phosphoric acid (H 3 PO 4).

Thereafter, the pad oxide layer pattern 102 is removed by a wet etching process to form an opening 110 for forming the floating gate. The pad oxide layer pattern 102 may be removed using a mixture of NH 4 OH, H 2 O 2, and H 2 O (typically, SC 1 or SC 2).

When the pad oxide layer pattern 102 is etched, a second preliminary element isolation layer pattern 107 is formed in which a sidewall of the first preliminary element isolation layer pattern 106 is partially etched to reduce the upper line width. Therefore, the opening 110 formed between the second preliminary isolation layer pattern 107 has a width wider than the line width of the active region 108.

The process exposes the substrate surface of the active region 108 to the outside. As shown in FIG. 10, the active region 108 and the field region extend in the first direction and are repeatedly arranged with each other.

Referring to FIG. 4, a tunnel oxide layer pattern 112 is formed on a substrate exposed to a bottom surface of the opening 110. The tunnel oxide layer pattern 112 may be formed of silicon oxide formed by performing a thermal oxidation process on a substrate.

Next, a first conductive layer 114 is continuously formed on the sidewall of the opening 110, the surface of the tunnel oxide layer pattern 112, and the surface of the preliminary isolation layer pattern. The first conductive layer 114 is formed to a thickness such that it does not completely fill the opening 110, that is, a thickness thinner than 1/2 of the inner width of the opening 110. The first conductive layer 114 is provided to the floating gate electrode through a subsequent process. The first conductive layer 114 may be formed by depositing a polysilicon material doped with impurities through a low pressure chemical vapor deposition (LPCVD) process. The impurity doping may be performed by POCl ₃ diffusion, ion implantation, or in-situ doping.

Next, a sacrificial layer 115 is formed to completely fill the inside of the opening 110. The sacrificial layer 115 may be formed by depositing silicon oxide having excellent gap filling properties.

5 and 12, a node is removed by removing a portion of the first conductive layer (FIGS. 9 and 114) and the sacrificial layer (FIGS. 9 and 115) such that an upper surface of the second preliminary isolation pattern 107 is exposed. The separated floating gate electrode layer 114a and the sacrificial layer pattern 115a are formed. The removal can be accomplished by chemical mechanical polishing. The floating gate electrode film 114a has a U shape in cross section and extends in the first direction.

6 and 13, a photoresist layer (not shown) is coated on the sacrificial layer pattern 115a and the floating gate electrode layer 114a. Next, by performing the exposure and development processes, a line-shaped photoresist pattern 116 extending in the second direction perpendicular to the first direction is formed. The photoresist pattern is formed to cover a region where a floating gate electrode is to be formed.

7 and 14, an isolated U-shaped floating gate electrode 114b is formed by etching the floating gate electrode layer 114a using the photoresist pattern 116 as an etching mask. In the process, it is preferable that the sacrificial layer pattern 115a and the second preliminary isolation layer pattern 107 exposed by the photoresist pattern 116 are hardly etched. However, even if portions of the exposed sacrificial layer pattern 115a and the second preliminary isolation layer 107 are slightly etched, process failure does not occur.

As described above, the isolated U-shaped floating gate electrode 114b has a shape in which the front and rear surfaces are exposed to the outside, unlike the floating gate electrode film 114a having a line shape extending in the first direction.

Next, the photoresist pattern 116 is removed by performing an ashing and stripping process.

Referring to FIG. 9, portions of the sacrificial layer pattern 115a remaining in the floating gate electrode 114b and the second preliminary isolation layer pattern 107 contacting sidewalls of the floating gate electrode 114b are removed. By the above process, the device isolation film pattern 107a having a height lower than that of the second preliminary device isolation film pattern 107 is completed.

In this case, the sacrificial layer pattern 115a may be completely removed. In addition, only the upper portion of the second preliminary device isolation layer pattern 107 may be removed so that the device isolation layer pattern does not contact the tunnel oxide layer or the substrate of the active region. By the removal process, the upper surface, the inner and outer side surfaces, the front surface, and the rear surface of the floating gate electrode 114b are exposed to the outside.

Next, the dielectric film 118 is continuously formed on the top surface, the inner and outer side surfaces, the front surface, and the field region upper surface of the floating gate electrode 114b. The dielectric layer 118 may be formed to have a stacked shape of a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer. Alternatively, the dielectric layer 118 may be formed using a metal oxide having a higher dielectric constant than that of the silicon oxide.

However, as described above, the floating gate electrode 114b has an isolated pattern shape, unlike in the prior art, the front, rear, and inside of the floating gate electrode 114b in the previous process before forming the dielectric layer 118. And the deposition area of the dielectric layer 118 is increased because the exposure to the outer side. As a result, the coupling ratio in the unit cell of the nonvolatile memory device can be sufficiently increased.

Referring to FIG. 10, a second conductive layer 123 is formed on the dielectric layer 118. The second conductive layer 123 may be formed by depositing a polysilicon layer 120 doped with impurities and then depositing a metal or metal silicide layer 122. A second hard mask layer 124 is formed on the second conductive layer 123.

11, 15 and 16, by coating a photoresist film on the second hard mask film 124, and exposing and developing the photoresist film, a line-shaped photoresist pattern extending in a second direction perpendicular to the first direction ( Not shown). The second hard mask pattern 124a is formed by etching the second hard mask layer 124 using the photoresist pattern as an etching mask. Next, the photoresist pattern is removed through an ashing and stripping process. At this time, as shown in FIGS. 16 and 17, the line width of the second hard mask pattern 124 is wider than the width of the floating gate electrode 114b in the second direction.

Subsequently, the control gate electrode 123a is formed by etching the second conductive layer 123 exposed by the second hard mask pattern 124. In the present embodiment, the control gate electrode 123a has a shape in which a metal silicide layer pattern or a metal pattern 122a is stacked on the polysilicon layer pattern 120a.

In this case, since the floating gate electrode 114b already has an isolated pattern shape, only the second conductive layer 123 is patterned to form the tunnel oxide layer pattern 112, the floating gate electrode 114b, the dielectric layer 118, and the like. A gate structure including the control gate electrode 123a may be completed. The control gate electrode 123a formed through the process is formed to surround the floating gate electrode 114b while having a line width wider than the width of the floating gate electrode 114b in the second direction.

As described above, unlike the related art, after the control gate electrode is formed, a process of finally patterning the dielectric layer and the floating gate electrode is not performed. Therefore, it is possible to reduce the active fitting phenomenon frequently generated in the process of finally patterning the dielectric film and the floating gate electrode.

As described above, according to the present invention, the area of the dielectric layer in contact with the floating gate electrode is increased, thereby providing a nonvolatile memory device having a high coupling ratio. In addition, when manufacturing a nonvolatile memory device, process defects such as active fittings can be reduced. Therefore, there is an effect that can improve the characteristics and reliability of the nonvolatile memory device.

As described above, although described with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified without departing from the spirit and scope of the invention described in the claims below. And can be changed.

Claims (8)

A substrate having an active region and a field region repeatedly disposed in the first direction with each other; A tunnel oxide pattern formed on an active region of the substrate; A floating gate electrode formed on the tunnel oxide film pattern, the floating gate electrode having a U-shaped isolation pattern shape; A dielectric layer formed on an upper surface, an inner and outer side, front and rear surfaces, and an upper surface of the field region of the floating gate electrode; And And a control gate electrode extending in a second direction perpendicular to the first direction on the dielectric layer. The nonvolatile memory device of claim 1, wherein a line width of the control gate electrode is wider than a width of the floating gate electrode in a second direction. The nonvolatile memory device of claim 1, wherein the control gate electrode has a shape surrounding the floating gate electrode. Forming a trench isolation layer which protrudes from the substrate and extends in a first direction, thereby providing an active region and a field region on the substrate that are repeatedly arranged in a first direction; Forming a tunnel oxide pattern on the substrate; Forming a floating gate electrode having a U-shaped isolated pattern shape on the tunnel oxide layer pattern; Forming a dielectric layer on upper surfaces, inner and outer sides, front and rear surfaces, and upper surface of the field region of the floating gate electrode; And And forming a control gate electrode on the dielectric layer, the control gate electrode extending in a second direction perpendicular to the first direction. The method of claim 4, wherein the forming of the floating gate electrode comprises: Continuously forming a floating gate electrode film on the trench device isolation layer and a substrate surface; Forming a preliminary floating gate electrode in the form of a line by polishing the floating gate electrode layer to expose an upper surface of the trench device isolation layer; And And cutting the preliminary floating gate electrode in the second direction to form a floating gate electrode having a U-shaped isolation pattern shape. 6. The method of claim 5, further comprising forming a sacrificial film on the floating gate electrode film. The method of claim 4, further comprising exposing an upper side surface of the floating gate electrode after forming the floating gate electrode. The method of claim 4, wherein the forming of the control gate electrode comprises: Forming a control gate electrode film on the dielectric film; And And patterning the control gate electrode layer to surround the floating gate electrode while having a line width wider than a width in the second direction of the floating gate electrode.

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