KR20060128377A - Multi chip package - Google Patents

Multi chip package Download PDF

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Publication number
KR20060128377A
KR20060128377A KR1020050049779A KR20050049779A KR20060128377A KR 20060128377 A KR20060128377 A KR 20060128377A KR 1020050049779 A KR1020050049779 A KR 1020050049779A KR 20050049779 A KR20050049779 A KR 20050049779A KR 20060128377 A KR20060128377 A KR 20060128377A
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KR
South Korea
Prior art keywords
semiconductor chip
substrate
circuit pattern
package
attached
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KR1020050049779A
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Korean (ko)
Inventor
정연호
김종현
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주식회사 하이닉스반도체
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Priority to KR1020050049779A priority Critical patent/KR20060128377A/en
Publication of KR20060128377A publication Critical patent/KR20060128377A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/074—Stacked arrangements of non-apertured devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process

Abstract

A multi-chip package is provided to prevent a package defect due to voids by interposing a photoresist between semiconductor chip instead of a space tape. A substrate has a circuit pattern. A first semiconductor chip(3a) is attached on the substrate in a face-up type manner. A photoresist is formed on the first semiconductor chip to expose a bonding pad(9a). A first metal wire(4) electrically connects the boding pad of the first semiconductor chip to the circuit pattern of the substrate. A second semiconductor chip(3b) is attached on the first semiconductor chip in the face-up type manner using the photoresist. A second metal wire(6) electrically connects the bonding pad of the second semiconductor chip to the circuit pattern of the substrate. An encapsulant(7) seals the first and the second semiconductor chip and an upper portion of the substrate including the first and the second metal wire. A solder ball(8) is attached on a lower surface of the substrate.

Description

멀티 칩 패키지{Multi chip package}Multi chip package

도 1은 본 발명에 따른 멀티 칩 패키지의 단면을 도시한다1 shows a cross section of a multi-chip package according to the invention.

도 2 내지 도 4는 본 발명에 따른 감광막 도포 방법을 설명하기 위한 도면.2 to 4 are views for explaining the photosensitive film coating method according to the present invention.

* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

1 : 기판 2a, 2b: 비전도성 접착물질1: Substrate 2a, 2b: non-conductive adhesive material

3 : 웨이퍼 레벨의 반도체 칩 3a : 제 1반도체 칩3: wafer-level semiconductor chip 3a: first semiconductor chip

3b: 제 2반도체 칩 4 : 제 1금속와이어3b: second semiconductor chip 4: first metal wire

5 : 감광막 6 : 제 2금속와이어5: photosensitive film 6: second metal wire

7 : 봉지제 8 : 솔더 볼7: encapsulant 8: solder ball

9a,9b : 본딩패드 10: 웨이퍼9a, 9b: bonding pad 10: wafer

본 발명은 반도체 패키지에 관한 것으로서, 보다 상세하게는 감과막(PR)의 적층을 통해 반도체 칩들을 하나의 패키지로 구현하는 멀티 칩 패키지에 관한 것이 다.The present invention relates to a semiconductor package, and more particularly, to a multi-chip package for implementing semiconductor chips into one package by stacking a photosensitive film PR.

반도체 산업에서 집적회로 칩에 대한 패키징 기술은 지속적으로 발전을 거듭하고 있다. 특히 최근에는 정보통신 분야의 발전과 더불어, 작고 가볍고 다기능의 패키지에 대한 개발 노력들이 계속되고 있다. 이러한 노력의 일환으로 제안된 것이 소위 멀티 칩 패키지(multi chip package)이다.Packaging technology for integrated circuit chips continues to evolve in the semiconductor industry. In particular, with the development of information and communication in recent years, efforts have been made to develop small, lightweight and multifunctional packages. As part of this effort, what has been proposed is a multi chip package.

멀티 칩 패키지는 동일한 크기 및 동일 한 기능의 메모리 칩을 적층하여 메모리 용량을 증대시키거나, 서로 다른 크기와 기능을 가지는 여러 유형의 반도체 칩을 하나의 패키지에 조립하여 제품의 성능과 효율성을 최대화하기 위한 것이다.Multi-chip packages increase memory capacity by stacking memory chips of the same size and function, or assemble different types of semiconductor chips of different sizes and functions into one package to maximize product performance and efficiency It is for.

멀티 칩 패키지는 적용하고자 하는 제품, 제조 회사 등에 따라 그 종류가 매우 다양하다. 종래의 일반적인 멀티 칩 패키지의 경우에는 기판의 한쪽 면에 반도체 칩이 수평으로 적층된다. 적층되는 반도체 칩 간의 전기적 연결은 금속 와이어에 의하여 이루어지며, 회로기판의 반대쪽 면에는 솔더 볼이 형성되어 패키지의 외부접속 단자가 된다. 여기서, 적층되는 반도체 칩 사이에는, 금속 와이어의 데미지 방지를 위한 공간확보를 위해 스페이스 테이프가 개재된다. There are many types of multi-chip packages depending on the product to be applied and the manufacturing company. In a conventional multichip package, a semiconductor chip is horizontally stacked on one side of a substrate. The electrical connection between the stacked semiconductor chips is made by metal wires, and solder balls are formed on the opposite side of the circuit board to become external connection terminals of the package. Here, a space tape is interposed between the stacked semiconductor chips in order to secure space for preventing damage of the metal wire.

그러나, 상술한 종래의 멀티 칩 패키지의 경우, 개별 패키지 단위로 스페이스 테이프 어태치(attach) 공정이 실시되어야 하며, 더욱이, 반도체 칩과 스페이스 테이퍼 사이에 보이드(void)가 발생하여, 패키지의 신뢰성이 저하되는 문제가 있다.However, in the conventional multi-chip package described above, a space tape attach process must be performed in individual package units. Furthermore, voids are generated between the semiconductor chip and the space taper, so that the reliability of the package is increased. There is a problem of deterioration.

따라서, 본 발명은 상기와 같은 문제점을 해결하기 위해 제안된 것으로서, 본 발명의 목적은 감과막(PR)의 적층을 통해 반도체 칩들을 하나의 패키지로 구현하는 멀티 칩 패키지를 제공함에 있다.Accordingly, the present invention has been proposed to solve the above problems, and an object of the present invention is to provide a multi-chip package that implements semiconductor chips into one package by stacking a photosensitive film PR.

상기와 같은 목적을 달성하기 위해 본 발명의 일면에 따라 멀티 칩 패키지가 제공되며: 이 패키지는, 회로패턴을 구비한 기판; 상기 기판 상에 페이스-업 타입으로 부착되고, 상부에 본딩패드가 노출되도록 감광막이 형성된 제 1 반도체 칩; 상기 제 1반도체 칩의 본딩패드와 기판 회로패턴 간을 전기적으로 연결하는 제 1 금속와이어; 상기 감광막을 매개로 상기 제 1 반도체 칩 상에 페이스-업 타입으로 부착된 제 2 반도체 칩; 상기 제 2 반도체 칩의 본딩패드와 기판 회로패턴 간을 전기적으로 연결하는 제 2 금속와이어;상기 제 1 및 제 2 반도체 칩과 제 1 및 제 2금속와이어를 포함한 기판 상부면을 밀봉하는 봉지제; 및 상기 기판 하부면에 부착된 솔더 볼;을 포함하는 것을 특징으로 한다.In accordance with an aspect of the present invention, a multi-chip package is provided. The package includes: a substrate having a circuit pattern; A first semiconductor chip attached to the substrate in a face-up type and having a photosensitive film formed thereon to expose a bonding pad thereon; A first metal wire electrically connecting the bonding pad of the first semiconductor chip and the substrate circuit pattern; A second semiconductor chip attached as a face-up type on the first semiconductor chip via the photosensitive film; A second metal wire electrically connecting between the bonding pad of the second semiconductor chip and the substrate circuit pattern; an encapsulant sealing the upper surface of the substrate including the first and second semiconductor chips and the first and second metal wires; And a solder ball attached to the lower surface of the substrate.

상기 구성에서, 상기 제 1 반도체 칩 상부에 형성된 감광막은 웨이퍼 레벨에서 형성된다.In the above configuration, the photosensitive film formed on the first semiconductor chip is formed at the wafer level.

(실시예)(Example)

이하, 첨부된 도면에 의거하여 본 발명의 바람직한 실시예를 상세하게 설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 1은 본 발명에 따른 멀티 칩 패키지의 단면을 도시한다.1 shows a cross section of a multi-chip package according to the invention.

도시된 바와 같이, 본 발명에 따른 멀티 칩 패키지는 회로패턴을 구비한 기판(1)과 상기 기판(1) 상에 비전도성 접착물질(2a)을 매개로 하여 상부에 감광막 (5)이 도포된 제 1 반도체 칩(3a)이 페이스-업 방식으로 부착된다. 그리고, 상기 제 1반도체 칩(3a)의 본딩패드(9a)와 기판 회로패턴은 제 1금속 와이어(4)로 와이어 본딩된다. 여기서, 제 1 반도체 칩(3a) 상부에 도포된 감광막(5)은 적층되는 반도체 칩 사이에 공간확보를 위한 것으로서, 웨이퍼 레벨에서 형성되며, 마스크 공정을 통해 본딩패드(9a)를 노출시키도록 도포된다.As shown, the multi-chip package according to the present invention is a substrate (1) having a circuit pattern and a photosensitive film (5) is applied to the upper portion via a non-conductive adhesive material (2a) on the substrate (1) The first semiconductor chip 3a is attached in a face-up manner. In addition, the bonding pad 9a of the first semiconductor chip 3a and the substrate circuit pattern are wire bonded to the first metal wire 4. Here, the photosensitive film 5 coated on the first semiconductor chip 3a is used to secure space between the stacked semiconductor chips, and is formed at the wafer level, and is applied to expose the bonding pad 9a through a mask process. do.

또한, 제 1 반도체 칩(3a) 상부에는 감광막(5)을 개재하며, 비전도성 접착물질(2b)을 매개로 제 2 반도체 칩(3b)이 페이스 업 방식으로 부착된다. 그리고 상기 제 2반도체 칩(3b)의 본딩패드(9b)와 기판 회로패턴은 제 2금속와이어(6)로 와이어 본딩되며, 상기 제 1 및 제 2반도체 칩(3a,3b)과 제 1 및 제 2 금속와이어(4,6)를 포함한 기판(1) 상부면은 봉지제(7)로 밀봉되며, 기판(1) 하부면에 솔더볼(8)이 부착된다. In addition, the second semiconductor chip 3b is attached to the upper surface of the first semiconductor chip 3a through the photosensitive film 5, and the second semiconductor chip 3b is attached through the non-conductive adhesive material 2b. The bonding pad 9b and the substrate circuit pattern of the second semiconductor chip 3b are wire bonded to the second metal wire 6, and the first and second semiconductor chips 3a and 3b and the first and the second circuit chips are wire-bonded. The upper surface of the substrate 1 including the two metal wires 4 and 6 is sealed with the encapsulant 7, and the solder ball 8 is attached to the lower surface of the substrate 1.

상기 구성을 통해 알 수 있듯이, 본 발명에 따른 멀티 칩 패키지는, 제 1 및 제 2 반도체 칩 사이에 웨이퍼 레벨에서 형성된 감광막(5)이 개재됨에 따라, 제 1 및 제 2 금속 와이어(4,6)의 데미지 방지를 위한 공간확보가 이루어진다.As can be seen from the above configuration, in the multi-chip package according to the present invention, as the photosensitive film 5 formed at the wafer level is interposed between the first and second semiconductor chips, the first and second metal wires 4 and 6 are provided. Space is secured to prevent damage.

이하, 도 2 내지 도 4를 참조하여, 본 발명에 따른 감광막 도포 방법을 설명하기로 한다. Hereinafter, the photosensitive film coating method according to the present invention will be described with reference to FIGS. 2 to 4.

도 2를 참조하면, 다수의 제 1 반도체 칩(도시안됨)이 실장되어 있는 웨이퍼(10) 상에 투명한 감광막(5)을 열압착 등과 같은 방법을 통해 균일하게 도포한다.Referring to FIG. 2, the transparent photosensitive film 5 is uniformly coated on a wafer 10 on which a plurality of first semiconductor chips (not shown) are mounted by a method such as thermocompression bonding.

그리고, 도 3을 참조하면, 감광막이 웨이퍼 상에 다수의 본딩패드(9a)를 노출시키기 위해, 마스크를 제작하며, 이러한 마스크를 통한 노광공정을 통해 본딩패 드(8a)를 노출시킨다.3, a photosensitive film fabricates a mask to expose a plurality of bonding pads 9a on the wafer, and exposes the bonding pads 8a through an exposure process through the mask.

이후, 도 4를 참조하면, 본딩패드(9a)가 노출되도록 감광막이 도포된 웨이퍼(10)를 소잉(sawing) 공정을 통해 개별 칩으로 분리한다. 이와 같이 제작된 다수의 제 1 반도체 칩(3a)은 상부에 본딩패드(9a)를 노출시키도록 형성된 감광막(5)을 포함하게 된다.Subsequently, referring to FIG. 4, the photosensitive film-coated wafer 10 is separated into individual chips through a sawing process so that the bonding pads 9a are exposed. The plurality of first semiconductor chips 3a manufactured as described above may include the photosensitive film 5 formed to expose the bonding pads 9a thereon.

이상에서 살펴본 바와 같이, 본 발명에 따른 멀티 칩 패키지는, 적층되는 반도체 칩과 반도체 칩사이에 기존의 스페이스 테이프 대신 감광막을 개재함으로써, 필요한 공간을 확보할 수 있다. 더욱이, 감광막은 개별 칩 단위가 아닌 웨이퍼 레벨에서 전체적으로 도포됨으로써, 공정시간을 단축할 수 있으며, 또한, 기존의 스페이스 테이프를 사용하지 않으므로, 보이드(void)에 의한 패키지 불량을 방지할 수 있다.As described above, in the multi-chip package according to the present invention, the necessary space may be secured by interposing a photosensitive film instead of the existing space tape between the stacked semiconductor chip and the semiconductor chip. Furthermore, the photoresist film is applied at the wafer level rather than in individual chip units as a whole, so that process time can be shortened, and package defects due to voids can be prevented since no conventional space tape is used.

본 발명의 상기한 바와 같은 구성에 따라, 웨이퍼 레벨에서의 감광막 도포에 따른 공정시간을 단축할 수 있으며, 또한, 기존의 스페이스 테이프를 사용하지 않으므로, 보이드(void)에 의한 패키지 불량을 방지할 수 있다.According to the above-described configuration of the present invention, the process time due to the application of the photosensitive film at the wafer level can be shortened, and since a conventional space tape is not used, package defects due to voids can be prevented. have.

본 발명을 특정의 바람직한 실시예에 관련하여 도시하고 설명하였지만, 본 발명이 그에 한정되는 것은 아니며, 이하의 특허청구의 범위에 의해 마련되는 본 발명의 정신이나 분야를 이탈하지 않는 한도 내에서 본 발명이 다양하게 개조 및 변형될 수 있다는 것을 당업계에서 통상의 지식을 가진 자는 용이하게 알 수 있다.While the invention has been shown and described with reference to certain preferred embodiments, the invention is not so limited, and the invention is not limited to the spirit and scope of the invention as set forth in the following claims. It will be readily apparent to those skilled in the art that these various modifications and variations can be made.

Claims (2)

회로패턴을 구비한 기판;A substrate having a circuit pattern; 상기 기판 상에 페이스-업 타입으로 부착되고, 상부에 본딩패드가 노출되도록 감광막이 형성된 제 1 반도체 칩;A first semiconductor chip attached to the substrate in a face-up type and having a photosensitive film formed thereon to expose a bonding pad thereon; 상기 제 1반도체 칩의 본딩패드와 기판 회로패턴 간을 전기적으로 연결하는 제 1 금속와이어;A first metal wire electrically connecting the bonding pad of the first semiconductor chip and the substrate circuit pattern; 상기 감광막을 매개로 상기 제 1 반도체 칩 상에 페이스-업 타입으로 부착된 제 2 반도체 칩;A second semiconductor chip attached as a face-up type on the first semiconductor chip via the photosensitive film; 상기 제 2 반도체 칩의 본딩패드와 기판 회로패턴 간을 전기적으로 연결하는 제 2금속와이어;A second metal wire electrically connecting the bonding pad of the second semiconductor chip and the substrate circuit pattern; 상기 제 1 및 제 2반도체 칩과 제 1 및 제 2 금속와이어를 포함한 기판 상부면을 밀봉하는 봉지제; 및An encapsulant sealing the upper surface of the substrate including the first and second semiconductor chips and the first and second metal wires; And 상기 기판 하부면에 부착된 솔더 볼;을 포함하는 것을 특징으로 하는 멀티 칩 패키지.And a solder ball attached to the lower surface of the substrate. 제 1항에 있어서,The method of claim 1, 상기 제 1 반도체 칩 상부에 형성된 감광막은 웨이퍼 레벨에서 형성된 것을 특징으로 하는 멀티 칩 패키지.And the photoresist formed on the first semiconductor chip is formed at a wafer level.
KR1020050049779A 2005-06-10 2005-06-10 Multi chip package KR20060128377A (en)

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