KR20060128280A - Method for manufacturing a semiconductor device - Google Patents

Abstract

A method for manufacturing a semiconductor device is provided to prevent an insulation layer and a conductive layer pattern from being damaged by forming a contact plug in which a contact hole is formed. A first insulation film(111) is formed on a semiconductor substrate(100). A plurality of conductive layer patterns are formed on the first insulation film. A second insulation film(116) is formed on the first insulation film to cover the conductive patterns. The second insulation film between the conductive layer patterns is recessed to form a trench. A third insulation film(125) having a silicon is deposited at an upper portion of the second insulation film. The second insulation film remaining at a lower portion of the trench is etched to form a contact hole. A conductive material is deposited on the third insulation film to bury the contact hole and the trench. The third insulation film and the conductive material are planarized to form a contact plug in which the contact hole and the trench are buried.

Description

Semiconductor device manufacturing method {METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE}

1 is a SEM photograph showing the damage of the HDP oxide film generated when forming a storage node contact of a semiconductor device according to the prior art.

2 to 5 are cross-sectional views illustrating a method for forming a contact plug of a semiconductor device according to a preferred embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

110 semiconductor substrate 110 junction region

111: first insulating film 112: landing plug

113: bit line 114: hard mask

115: bit line spacer 116: second insulating film

117 photoresist pattern 118 etching process

119: trench 120: storage node spacer

122: third insulating film 123: etching process

125: contact hole 127: contact plug

O: Overhang generating area

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a storage node (or lower electrode) contact plug of a capacitor of 80 nm or less.

As the semiconductor devices are highly integrated, storage node contacts of the 80 nm or smaller capacitors are formed using a ArF photosensitive film to form storage node contacts in a hole type. In the case of forming the storage node contact in the hole type as described above, an open area of the upper portion of the storage node contact is narrow, so that an overlay margin with the storage node (the lower electrode of the capacitor) is insufficient. Therefore, to secure the overlay margin, a poly pad must be formed separately between the storage node contact and the storage node.

However, there is a problem that the process is complicated to form the poly pad separately. In addition, since the use of the ArF photosensitive film requires expensive mask equipment, there is a problem in that the manufacturing cost increases.

As a result, in order to solve the complexity of the manufacturing process and the increase in manufacturing cost, the overlay margin between the storage node contact and the storage node is increased by increasing the open area of the storage node contact by applying a widening etch method. It was made. In general, the widening etching method partially etches the interlayer insulating layer, that is, the HDP oxide layer on both sides of the storage node contact, to increase the open area on the storage node contact. In this case, the HDP oxide film is usually formed through two deposition and etching processes in order to improve the buried property. For example, a first HDP oxide layer covering a bit line is deposited through a first deposition process, and a portion in which a void is formed is etched through a first etching process. Then, the second HDP oxide film is deposited on the first HDP oxide film through the second deposition process, and the portion where the voids are formed is etched through the second etching process and then planarized by a chemical mechanical polishing (CMP) process.

However, when the widening etching method is applied, the HDP oxide film may be damaged and, in severe cases, the bit line may be damaged. The reason for this is as follows. In the first and second etching processes, NF ₃ is typically used. After planarization is performed, fluorine (F) of NF ₃ is exposed at the interface between the first and second HDP oxide layers. Then, the etching solution used during the etching process for forming the storage node contacts penetrates into the HDP oxide film along the exposed fluorine to inflict damage to the HDP oxide film (see 'A' region) as shown in FIG. 1. There is a problem. This affects the bit lines and damages the bit lines.

Accordingly, the present invention has been made to solve the above-mentioned problems of the prior art, the insulating film and the conductive that exist on both sides of the storage node contact while ensuring the overlay margin between the storage node contact and the storage node when forming the storage node contact of the semiconductor device It is an object of the present invention to provide a method for manufacturing a semiconductor device that prevents damage to a layer pattern.

According to an aspect of the present invention, there is provided a method including forming a first insulating film having a landing plug interposed on a semiconductor substrate, forming a plurality of conductive layer patterns on the first insulating film, Depositing a second insulating film on the first insulating film so as to cover the conductive layer pattern, recessing the second insulating film between the conductive layer patterns to form a trench, and overhanging the trench Depositing a third insulating film containing silicon on the second insulating film including the trench so as to be generated, and etching the second insulating film remaining on the bottom of the trench through an etching process using the third insulating film as a hard mask. Forming a contact hole exposing the landing plug, and forming a conductive material on the third insulating layer to fill the contact hole and the trench And depositing a contact plug in which the contact hole and the trench are filled by planarizing the third insulating film and the conductive material.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. In addition, in the drawings, the thicknesses of layers and regions are exaggerated for clarity, and in the case where the layers are said to be "on" another layer or substrate, they may be formed directly on another layer or substrate or Or a third layer may be interposed therebetween.

Example

2 to 5 are process cross-sectional views illustrating a method for forming a contact plug of a semiconductor device according to an exemplary embodiment of the present invention. Here, the same reference numerals among the reference numerals shown in FIGS. 2 to 5 are the same elements performing the same function.

First, as shown in FIG. 2, after forming a plurality of word lines (not shown) on the semiconductor substrate 100, a junction region 110 is formed on the substrate 100 exposed to both sides of the word line. .

Subsequently, the first insulating layer 111 is deposited to cover the word line, and the first insulating layer 111 between the word lines is etched to form a contact hole (not shown) exposing the junction region 110. Then, polysilicon is deposited and planarized so that the contact holes are filled to form a landing plug 112 in which the contact holes are embedded. In this case, the first insulating layer 111 is formed of an oxide film-based material as an interlayer insulating layer (ILD). For example, the first insulating layer 111 may be an HDP (High Density Plasma) oxide film, a BPSG (Boron Phosphorus Silicate Glass) film, a PSG (Phosphorus Silicate Glass) film, a PETEOS (Plasma Enhanced Tetra Ethyle Ortho Silicate) film, a PECVD (Plasma Enhanced Chemical) A single layer film or a laminate thereof is formed by using any one of a vapor deposition (USG) film, a USG (Un-doped Silicate Glass) film, a FSG (Fluorinated Silicate Glass) film, a carbon doped oxide (CDO) film, and an organic Silicate Glass (OSG) film. It is formed of a laminated film.

Subsequently, a plurality of bit lines 113 including the hard mask 114 are formed on the first insulating layer 111 including the landing plug 112. Although not illustrated in the drawing, the bit line 113 may have a structure in which polysilicon / barrier metal / tungsten (W) / hard mask 114 is stacked. In addition, both side walls may further include a nitride film bit line spacer 115 for protecting the bit line 113. For example, the bit line 113 is formed as follows.

First, polysilicon is deposited on the first insulating layer 111 including the landing plug 112, and then Ti / TiN is deposited using a barrier metal to a thickness of 100 to 1000 Å. Then, tungsten is deposited to a thickness of 300 to 1000 mW and a hard mask 114 made of a nitride film is deposited to a thickness of 2000 to 4000 mW.

Subsequently, the hard mask 114 is etched by performing a photolithography process, wherein the hard mask 114 has a pressure of 20 to 70 mTorr using a combination gas of CF ₄ / CHF ₃ / O ₂ / Ar. And etching at a power condition of 300 to 1000W.

Subsequently, tungsten is etched through an etching process using the hard mask 114, wherein tungsten is 300 to 1000 W and a pressure of 20 to 70 mTorr using a combination gas of SF ₆ / BCL ₃ / N ₂ / Cl ₂ . Etch under power condition.

Subsequently, the barrier metal and the polysilicon are etched through an etching process using the hard mask 114, and a nitride film is deposited to a thickness of 50 to 150 μm over the entire structure including the hard mask 114. Then, by performing a dry etching process to etch the nitride film, the bit line spacer 115 is formed on both side walls of the bit line 113.

Subsequently, a second insulating layer 116 is deposited on the entire structure including the bit line 113. In this case, the second insulating layer 116 is formed of an oxide-based material. Preferably, the second insulating layer 116 is formed of an HDP (High Density Plasma) oxide film. In addition, the second insulating film 116 is deposited to a thickness of 4000 to 10000 kPa.

Subsequently, a KrF photosensitive film (not shown) is coated on the second insulating film 116, and then a photoresist pattern 117 is formed by performing an exposure and development process using a photomask (not shown). Here, the cost of mask equipment is reduced when using KrF and a photosensitive film.

Next, an etching process 118 using the photoresist pattern 117 as an etching mask is performed to etch the second insulating layer 116 between the bit lines 113. As a result, the trench 119 is formed in the second insulating film 116. At this time, the open area D of the trench 119 is formed to be narrower than the distance between the bit lines 113 so as not to damage the bit lines 113. In addition, the trench 119 is formed to a depth of 1000 to 2000Å.

Here, the etching process 118 for forming the trench 119 is C ₄ F ₈ / C ₅ F ₈ / C ₄ F ₆ / CH ₂ F ₂ / Ar / under a pressure of 15 to 50 mTorr and a power of 300 to 1000 W. It is carried out using a combination gas combining an etching gas of O ₂ / Co / N ₂ .

Subsequently, as shown in FIG. 3, a strip process is performed to remove the photoresist pattern 117 (see FIG. 2), and then a cleaning process is performed.

In addition, although not shown in the drawings, the open area (D, FIG. 2) of the trench 119 (see FIG. 2) through a wet etching process using a BOE (Buffered Oxide Etchant) solution in which HF and NH ₄ F are mixed at 20: 1. 2).

Subsequently, a nitride film (not shown) is deposited to a thickness of 100 to 300 Å along the step above the second insulating film 116 including the trench 119. Thereafter, a dry etching process is performed to etch the nitride film. As a result, storage node spacers 120 are formed on inner walls of the trench 119.

Subsequently, as shown in FIG. 4, a third insulating film 122 containing a predetermined amount of silicon (Si) is deposited on the second insulating film 116 including the trenches 119 (see FIG. 2) to a thickness of 500 to 2000 GPa. do. In this case, the third insulating layer 122 is a silicon rich oxide nitride (SRON) film containing 20 to 50% of silicon, so the step coverage is low. ) Is generated. Accordingly, the critical dimension (CD ₁ , CD ₁ ) between the third insulating film 122 having an overhang (see 'O' region) is generated between the third insulating film 122 above the trench 119. ₂ ) This means that the open area of the trench 119 is larger than the open area of the overhang portion (see 'O' portion).

Subsequently, an etching process 123 using the third insulating layer 122 as a hard mask is performed to etch the third insulating layer 122 and the second insulating layer 116. As a result, a contact hole 125 exposing the landing plug 112 is formed.

Here, since the open area of the contact hole 125 uses the third insulating film 122 as a hard mask, the critical dimension CD ₁ between the third insulating film 122 where an overhang (see 'O' region) occurs and same. Accordingly, damage to the bit line 113 may be prevented by securing a space margin with the bit line 113.

Subsequently, although not shown in the drawings, an etching process for forming the contact hole 125 through a cleaning process using a BOE solution in which H ₂ SO ₄ / H ₂ O ₂ or HF and NH ₄ F are mixed at 300: 1 is performed. Remove polymer remaining in the process.

Subsequently, as illustrated in FIG. 5, a conductive material (not shown) is deposited on the third insulating layer 122 so that the contact holes 125 (see FIG. 4) and the trenches 119 (see FIG. 2) are embedded. At this time, the conductive material is polysilicon and is deposited to a thickness of 1500 to 3000Å.

Subsequently, the third insulating film 122 and the conductive material are planarized by performing a chemical mechanical polishing (CMP) process using the second insulating film 116 as a planarization stop film. As a result, the storage node contact plug 127 in which the contact hole 125 and the trench 119 are embedded is formed. In this case, the open area of the upper portion of the contact plug 127 is equal to the critical dimension CD ₂ between the third insulating layers 122 of the upper portion of the trench 119. Therefore, it is possible to secure an overlay margin with a storage node (not shown) to be formed through a subsequent process.

Subsequently, although not shown in the figure, the storage node of the capacitor is electrically connected to the storage node contact plug 127.

Although the technical spirit of the present invention has been described in detail in the preferred embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. In addition, it will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, after forming a trench having a wide open area in the insulating film between the conductive layer patterns, by forming a contact plug in which the trench is embedded, the critical dimension of the upper portion of the contact plug is increased. Therefore, it is possible to secure an overlay margin between the contact plug and the storage node.

In addition, according to the present invention, a contact plug having a smaller critical dimension than a trench is formed in the bottom of the trench by using a SRON film having a low step coverage and an overhang occurring in the upper portion of the trench as a hard mask. As a result, a space margin between the conductive layer pattern and the insulating film existing on both sides of the contact plug is ensured. Thus, damage to the conductive layer pattern and the insulating film is prevented.

In addition, according to the present invention, it is possible to reduce the cost of the mask equipment by forming a storage node contact using the KrF photosensitive film. Therefore, the manufacturing cost of the semiconductor device can be reduced and the yield can be improved.

Claims (15)

Forming a first insulating film having a landing plug interposed on the semiconductor substrate; Forming a plurality of conductive layer patterns on the first insulating film; Depositing a second insulating film on the first insulating film so as to cover the conductive layer pattern; Recessing the second insulating layer between the conductive layer patterns to form a trench; Depositing a third insulating film containing silicon on the second insulating film including the trench to cause an overhang in the upper portion of the trench; Forming a contact hole exposing the landing plug by etching the second insulating film remaining in the bottom of the trench through an etching process using the third insulating film as a hard mask; Depositing a conductive material on the third insulating layer to fill the contact hole and the trench; And Planarizing the third insulating layer and the conductive material to form a contact plug filling the contact hole and the trench Semiconductor device manufacturing method comprising a. The method of claim 1, The third insulating film is a semiconductor device manufacturing method of forming a SRON film containing 20 to 50% of silicon. The method according to claim 1 or 2, And an open area of the trench is larger than an open area between the third insulating layers at which the overhang has occurred. The method according to claim 1 or 2, And forming a spacer on an inner wall of the trench after forming the trench. The method of claim 4, wherein The spacer is a semiconductor device manufacturing method of forming a nitride film. The method of claim 1, The conductive layer pattern is a semiconductor device manufacturing method is a bit line formed of a laminated structure of a polysilicon layer / barrier metal / tungsten / hard mask. The method of claim 6, The barrier metal is a semiconductor device manufacturing method formed of Ti / TiN. The method of claim 6, The hard mask is a semiconductor device manufacturing method of forming a nitride film. The method according to claim 1 or 6, The conductive layer pattern is a semiconductor device manufacturing method comprising a spacer consisting of a nitride film on both side walls. The method according to claim 1 or 2, After forming the trench, a method of manufacturing a semiconductor device further comprising increasing the open area of the trench through a wet etching process using a BOE (Buffered Oxide Etchant) solution in which HF and NH ₄ F are mixed at 20: 1. . The method of claim 1, The trench combines an etching gas of C ₄ F ₈ / C ₅ F ₈ / C ₄ F ₆ / CH ₂ F ₂ / Ar / O ₂ / Co / N ₂ at a pressure of 15 to 50 mTorr and a power of 300 to 1000 W. A method of manufacturing a semiconductor device formed by an etching process using a combination gas. The method according to claim 1 or 2, After forming the contact hole further comprises the step of removing the remaining polymer through a cleaning process using a BOE solution H ₂ SO ₄ / H ₂ O ₂ or HF and NH ₄ F is mixed 300: 1 Manufacturing method. The method according to claim 1 or 2, The contact hole is an etching gas of C ₄ F ₈ / C ₅ F ₈ / C ₄ F ₆ / CH ₂ F ₂ / Ar / O ₂ / Co / N ₂ at a pressure of 15 to 50 mTorr and a power of 300 to 1000 W. A semiconductor device manufacturing method formed by performing an etching process using a combination gas combined. The method according to claim 1 or 11, wherein The trench is a semiconductor device manufacturing method to form a depth of 1000 to 2000Å. The method according to claim 1 or 2, The second insulating film is a semiconductor device manufacturing method to form a thickness of 4000 to 10000Å.

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