KR20060125111A - Liquid crystal display device - Google Patents

Abstract

An LCD is provided to reduce the gravity defect of an LCD panel due to volume expansion of a liquid crystal layer, by respectively forming spacers at different regions, in which step heights of patterns are different from each other. A gate line(101) vertically crosses a data line to define a pixel region above a first substrate. A thin film transistor is formed at a crossing region of the gate line and the data line. The thin film transistor includes a gate electrode, a source electrode(105a), and a drain electrode(105b). A pixel electrode(107) is formed in the pixel region, and electrically connected to the drain electrode. A first spacer(115a) is formed at a contact region of the drain electrode and the pixel electrode. A second spacer(115b) is formed on the gate line. The first substrate is distanced from a second substrate by the first and second spacers. A liquid crystal layer is formed between the first substrate and the second substrate.

Description

Liquid crystal display device {LIQUID CRYSTAL DISPLAY DEVICE}

1 is a cross-sectional view schematically showing a liquid crystal display device.

2 is a plan view showing a liquid crystal display device according to the present invention.

3 is a cross-sectional view taken along the line II ′ and II-II ′ of FIG. 2.

*** Explanation of symbols for main parts of drawing ***

110: first substrate 101: gate line;

103: data line 105a: source electrode

105b; Drain Electrode 105b ': Drain Electrode Connection Pattern

108: semiconductor layer 107: pixel electrode

111: gate insulating film 113: protective film

115a: first spacer 115b: second spacer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device capable of preventing gravity failure due to volume expansion of liquid crystals.

Recently, with the development of various portable electronic devices such as mobile phones, PDAs, and notebook computers, there is an increasing demand for flat panel display devices for light and thin applications. Such flat panel displays are being actively researched, such as LCD (Liquid Crystal Display), PDP (Plasma Display Panel), FED (Field Emission Display), VFD (Vacuum Fluorescent Display), but mass production technology, ease of driving means, Liquid crystal display devices (LCDs) are in the spotlight for reasons of implementation.

1 schematically illustrates a cross section of a general liquid crystal display device. As shown in the figure, the liquid crystal display device 1 is composed of a lower substrate 5 and an upper substrate 3 and a liquid crystal layer 7 formed between the lower substrate 5 and the upper substrate 3. . Although the lower substrate 5 is a driving element array substrate, although not shown in the drawing, a plurality of pixels are formed on the lower substrate 5, and each pixel is driven such as a thin film transistor. An element is formed, and the upper substrate 3 is a color filter substrate, and a color filter layer for realizing color is formed. In addition, a pixel electrode and a common electrode are formed on the lower substrate 5 and the upper substrate 3, respectively, and an alignment film for aligning liquid crystal molecules of the liquid crystal layer 7 is coated.

The lower substrate 5 and the upper substrate 3 are bonded by a sealant 9 formed on the outer periphery of the substrate and have a constant cell gap by a spacer 8 formed between them (the upper substrate and the lower substrate). Keep it. In addition, the liquid crystal layer 7 formed between the substrates 3 and 5 drives the liquid crystal molecules by a driving element formed on the lower substrate 5 to display information by controlling the amount of light passing through the liquid crystal layer. .

The liquid crystal display device configured as described above is formed by a drive element array substrate process of forming a drive element on the lower substrate 5, and the upper substrate 3 is formed by a color filter substrate process of forming a color filter. Thereafter, the liquid crystal display device is completed through a spacer and a sealant forming process.

In the driving device array substrate process, a plurality of gate lines and data lines are formed on the lower substrate 5 to define pixel regions, and the gate lines and the data lines are respectively formed in the pixel regions. After forming the thin film transistor which is the driving element to be connected, the pixel electrode is connected to the thin film transistor to form a pixel electrode for driving the liquid crystal layer as a signal is applied through the thin film transistor.

In addition, the color filter substrate process is performed by forming a black matrix on the upper substrate 3, forming a color filter on the upper substrate, and then forming a common electrode.

The spacer may be formed as a ball or a column, and the ball spacer is formed by a scattering method, and the column spacer is formed by depositing or coating an organic polymer material on a substrate, and then selectively It is formed by a photolithography process to remove. However, the scattering method interferes with the alignment of the liquid crystal and lowers the aperture ratio because spacers exist in the pixel region through which light passes. Therefore, in order to improve this, a column spacer is proposed which forms a spacer patterned at a desired position.

In addition, in the case of a large liquid crystal display device having a low cell gap, a column spacer is mainly used. This is because it is difficult to produce a ball spacer with a size of 4 to 5 μm or less and it is difficult to secure uniformity of the cell gap when applied to a large area.

The column spacer is coated on the lower substrate or the upper substrate with a predetermined thickness, cured, and formed at an arbitrary position on the substrate by a photoresist process. In this case, the column spacer is positioned in the region where the black matrix is formed and is uniformly formed with the same height.

However, the spacer 8 is pressed by the pressure applied when the upper substrate 3 and the lower substrate 5 are bonded and the pressure applied when vacuum injecting the liquid crystal to reduce the cell gap in the center portion of the liquid crystal panel. In particular, this phenomenon occurs remarkably when a large area liquid crystal display device is manufactured. On the other hand, since the sealant 9 formed at the edge of the liquid crystal panel includes glass fibers to maintain the initial cell gap, the cell gap of the edge region of the liquid crystal panel is relatively larger than that of the center portion.

In this state, if the liquid crystal layer formed inside the liquid crystal panel increases in volume due to temperature rise and the cell gap of the liquid crystal panel becomes larger than the spacers, the liquid crystal is driven to the edge of the liquid crystal panel having a higher cell gap, resulting in poor gravity. . In other words, when the liquid crystal is driven to the edge of the liquid crystal panel, the transmittance of the liquid crystal is changed in this portion, and the screen display characteristics are deteriorated.

Accordingly, the present invention has been made to solve the above problems, and an object of the present invention is to provide a liquid crystal display device that can improve the gravity failure of the liquid crystal panel in response to the volume expansion of the liquid crystal layer.

The present invention for achieving the above object is a first substrate and a second substrate; A plurality of gate lines arranged in a first direction on the first substrate; A plurality of data lines crossing the gate lines and defining a plurality of pixel regions; A thin film transistor disposed at an intersection of the gate line and the data line, the thin film transistor comprising a gate electrode, a semiconductor layer, a source electrode, and a drain electrode; A pixel electrode formed in the pixel region and electrically connected to the drain electrode; A first spacer formed on the gate line; A second spacer formed in the connection region between the drain electrode and the pixel electrode; And a liquid crystal layer formed between the first and second substrates spaced by the first and second spacers. In this case, the second spacer maintains the set cell gap, and the first spacer maintains the cell gap of the expanded liquid crystal layer.

The first substrate corresponding to the first spacer includes a gate pattern formed on the first substrate, a gate insulating film formed on the gate pattern, a drain electrode formed on the gate insulating film, a protective film formed on the drain electrode, and And a pixel electrode formed on the passivation layer, wherein the first substrate corresponding to the first spacer includes a gate line formed on the first substrate, a gate insulation layer formed on the gate line, and a passivation layer formed on the gate insulation layer. And a pixel electrode formed on the passivation layer.

The second substrate may further include: a black matrix arranged vertically and horizontally to define a plurality of pixels; A color filter formed in each pixel region; And a common electrode formed on the color filter. In this case, the first and second spacers are formed on the second substrate, and may be formed on the first substrate.

As described above, the present invention solves the gravity failure of the liquid crystal display by forming spacers at positions different from each other. Since the liquid crystal expands in volume over a predetermined temperature (about 50 ° C.), even if an appropriate amount of liquid crystal is injected into the liquid crystal panel at room temperature, the liquid crystal expands and becomes thicker than the original cell gap when the temperature rises. Accordingly, the cell gap of the liquid crystal panel becomes higher than the height of the spacer, and the liquid crystal is oriented in the direction of gravity, causing gravity failure. When the spacer is made in consideration of the expansion of the liquid crystal, the liquid crystal is oriented in the direction of gravity I can prevent it. In other words, the spacer formed in a region where the pattern height at a high temperature is relatively high serves to prevent the liquid crystal from being oriented in the direction of gravity.

In the present invention, the second spacer formed in the gate line region having a relatively low level of step maintains the set cell gap, and the second spacer formed in the connection region between the drain electrode and the pixel electrode maintains the cell gap at a high temperature (50 ° C. or higher). Prevents gravity from tipping.

In this case, the first spacer may be formed on the thin film transistor. However, in the present invention, since the first spacer may damage the semiconductor layer of the thin film transistor due to external pressure, the characteristics of the thin film transistor may be degraded. In particular, the first spacer may be located in the connection region between the drain electrode and the pixel electrode. It prevents damage of thin film transistor by external force.

Hereinafter, the liquid crystal display device according to the present invention will be described in more detail with reference to the accompanying drawings.

2 shows a part of a thin film transistor array substrate of a liquid crystal display device according to the present invention.

As shown in the figure, the liquid crystal display device 100 according to the present invention has a plurality of gate lines 101 arranged in a first direction on the transparent substrate 110 and vertically aligned with the gate lines 101. And a plurality of data lines 103 defining a plurality of pixels, and a thin film transistor TFT formed at an intersection area of the gate line 101 and the data line 103. The thin film transistor TFT may include a gate electrode drawn from the gate line 101, a semiconductor layer 108 formed on the gate electrode, and a source electrode and a drain electrode formed at predetermined intervals on the semiconductor layer 108. It consists of 105a and 105b.

Although not shown in detail, a gate insulating film is described between the gate electrode and the semiconductor layer 108, and a protective film is formed on the substrate including the data line 103 and the source / drain electrodes 105a and 105b. Not shown) is formed.

In the pixel region, a pixel electrode 107 formed of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) is formed, and the pixel electrode 107 forms a drain contact hole 106. It electrically connects with the drain electrode extension pattern 105b 'extending from the drain electrode 105b.

In addition, the pixel electrode 107 is formed on the passivation layer and extends to the upper portion of the gate line 101 to form a storage capacitor Cst together with the gate line 101.

The thin film transistor array substrate configured as described above is bonded at regular intervals together with the color filter, the black matrix, and the color filter substrate on which the common electrode is formed. At this time, a constant cell gap between the thin film transistor array substrate and the color filter substrate is maintained. Spacers are formed. The spacer is formed on the color filter substrate.

In the present invention, the spacer formed on the color filter substrate is bonded to the thin film transistor array substrate, and then the region corresponding to the first spacer 115a and the gate line 101 disposed in the region corresponding to the drain electrode connection pattern 105b '. It consists of a second spacer 115b disposed in the.

Since the step height of the pattern is higher than that of the gate line 101, the region of the drain electrode connection pattern 105b ′ may be formed in the region of the drain electrode connection pattern 105b ′ where the first spacer 115a is disposed. The thin film transistor array substrate is in contact with the first spacer 115a, but the thin film transistor array substrate in the region of the gate line 101 where the second spacer 115b is disposed forms a predetermined distance from the second spacer 115b. .

That is, the thin film transistor array substrate in the region where the first spacer 115a is disposed has a pattern such as a gate pattern, a gate insulating film, and a drain electrode connection pattern, whereas the thin film transistor array substrate in the region where the second spacer is disposed is a gate. Since the pattern, the gate insulating film, and the like are formed, the height of the pattern is formed higher in the region corresponding to the first spacer 115a. Accordingly, the first spacer 115a is in contact with the thin film transistor array substrate, but the second spacer 115b has a space corresponding to the thickness of the pattern added to the first spacer 115a.

3 is a cross-sectional view of the drain electrode connection pattern and the gate line formation region of FIG. 2, that is, the cross-sections of I-I 'and II-II', respectively.

As shown in the figure, first and second spacers which maintain their cell gap between the thin film transistor array substrate 110 (hereinafter referred to as a first substrate) and the color filter substrate (hereinafter referred to as a second substrate). 115a and 115b are formed, and the first and second spacers 115a and 115b are formed on the color filter substrate 120.

The second substrate 120 includes a color filter, a black matrix and a common electrode, the black matrix blocks light leakage, and the common electrode is filled between the first and second substrates together with the pixel electrode 107. An electric field is applied to the obtained liquid crystal layer 130.

First, as shown in the cross section of I-I ', the gate pattern 101a, the gate insulating film 111 and the drain electrode connection pattern are formed on the first substrate 110 corresponding to the region where the first spacer 115a is disposed. The pixel electrodes 105 'are sequentially stacked on the drain electrode connection pattern 105b' and electrically connected to the drain electrode connection pattern 105b 'through the passivation layer 113 and the drain contact hole 106. 107 is formed. In this case, the gate insulating layer 111 and the passivation layer 113 are formed over the entire surface of the substrate, and the gate pattern 101a is formed separately to match the step with the region where the thin film transistor is formed, and the gate line and the gate electrode are formed. Can be formed together.

Although not shown, a semiconductor pattern may be interposed between the gate insulating layer 111 and the drain electrode connection pattern 105b '.

The first spacer 115a formed on the second substrate 120 is in contact with the uppermost layer pattern formed on the first substrate. Although the pixel electrode is shown as the uppermost layer, substantially, since the alignment film is applied to the first spacer and the pixel electrode, the alignment film formed on the surface of the first spacer and the pixel electrode abuts.

In addition, as shown in the cross section of II-II ', the gate line 101, the gate insulating film 111, and the protective film 113 are formed on the first substrate 110 corresponding to the region where the second spacer 115b is disposed. The stacked electrodes are sequentially stacked, and the pixel electrode 107 is formed on the passivation layer 113. The pixel electrode 107 formed on the gate line 101 is intentionally overlapped with the gate line 101 to form a storage capacitor, as described in the previous drawings.

As such, the patterns formed on the first substrate 110 corresponding to the first spacer 115a have more drain electrode connection patterns 105b 'than the regions corresponding to the second spacer 115b. In the second spacer 115b, a space d having a thickness equal to the thickness of the pixel electrode 107 and the drain electrode connection pattern 105b ′ formed on the uppermost layer of the first substrate 110 is formed.

In other words, the height of the pattern formed on the first substrate 110 corresponding to the first spacer 115a is formed higher, which prevents the liquid crystal from being directed in the direction of gravity in a high temperature environment of 50 ° C. or higher.

Accordingly, the second spacer 115b mainly maintains the cell gap set in an environment of 50 ° C. or less, whereas the first spacer 115a mainly extends by two layers of the liquid crystal layer in a 50 ° C. or more environment. The cell gap between the first and second substrates is maintained.

In particular, in order to prevent gravity failure, the first spacer 115a may be formed in any region (eg, a thin film transistor) as long as the height of the pattern is formed relatively higher than the region where the second spacer 115b is formed. Can be.

However, when the first spacer 115a is formed in a region corresponding to the thin film transistor, the first spacer 115a may damage the thin film transistor, especially the semiconductor layer, due to an external force. Accordingly, in the present invention, the first spacer is formed in a region corresponding to the drain electrode connection pattern electrically connected to the pixel electrode so as to solve such a problem, thereby preventing the spacer from damaging the thin film transistor by an external force.

As described above, the present invention provides a liquid crystal display device capable of preventing a gravity failure by forming a different height of the spacer. In particular, the present invention provides a second spacer for maintaining the cell gap of the set liquid crystal panel, and when the cell gap of the panel becomes larger than the set cell gap due to the volume expansion of the liquid crystal layer formed inside the liquid crystal panel, after the volume expansion of the liquid crystal layer, By forming a first spacer capable of maintaining the cell gap of the liquid crystal panel, the liquid crystal is prevented from moving and the gravity defect is solved.

Further, the present invention effectively prevents the spacer from damaging the thin film transistor by an external force by forming the first spacer in a region corresponding to the drain electrode connection pattern.

As described above, according to the present invention, it is possible to cope with the volume expansion of the liquid crystal layer by forming the spacers in regions where the steps of the pattern are different from each other. In particular, the present invention forms a spacer in a region corresponding to the drain electrode connection pattern which extends from the drain electrode and electrically connects to the pixel electrode, thereby protecting the thin film transistor from the pressure of the spacer due to external force, thereby improving reliability of the liquid crystal display device. Let's do it.

Claims (8)

A first substrate and a second substrate; A plurality of gate lines arranged in a first direction on the first substrate; A plurality of data lines crossing the gate lines and defining a plurality of pixel regions; A thin film transistor disposed at an intersection of the gate line and the data line, the thin film transistor comprising a gate electrode, a semiconductor layer, a source electrode, and a drain electrode; A pixel electrode formed in the pixel region and electrically connected to the drain electrode; A first spacer formed in a connection region between the drain electrode and the pixel electrode; A second spacer formed on the gate line; And And a liquid crystal layer formed between the first and second substrates spaced apart by the first and second spacers. The method of claim 1, And the first spacer maintains a cell gap of the expanded liquid crystal layer. The method of claim 1, And the second spacer maintains a set cell gap. The method of claim 1, The first substrate corresponding to the first spacer, A gate pattern formed on the first substrate; A gate insulating film formed on the gate pattern; A drain electrode connection pattern extending from the drain electrode formed on the gate insulating film; A passivation layer formed on the drain electrode connection pattern; And And a pixel electrode formed on the passivation layer. The method of claim 4, wherein And a semiconductor pattern interposed between the gate insulating film and the drain electrode connection pattern. The method of claim 1, On the first substrate corresponding to the second spacer, A gate line formed on the first substrate; A gate insulating film formed on the gate line; A protective film formed on the gate insulating film; And And a pixel electrode formed on the passivation layer. The method of claim 1, The second substrate, A black matrix arranged vertically and horizontally to define a plurality of pixels; A color filter formed in each pixel region; And And a common electrode formed on the color filter. The method of claim 7, wherein And the first and second spacers are formed on a second substrate.

Images