KR20060123969A - Delay locked loop for high speed - Google Patents

Abstract

A delay locked loop for performing a high-speed operation is provided to reduce errors by simplifying resolution and control of a DLL circuit in a DDR DRAM. A clock buffer(110) buffers external clocks and outputs the buffered clocks. A variable delay circuit(120) includes N unit delay parts for delaying the buffered clocks and has an initial value of a variable delay which is set as a half of the amount of variable delay. A replica unit(130) generates feedback clocks by delaying internal clocks of the variable delay circuit. A phase comparator(140) generates a delay-up signal and a delay-down signal by comparing the external clocks with the feedback clocks. A shifter(150) controls the amount of variable delay based on the initial value of the variable delay in response to the delay-up signal and the delay-down signal.

Description

Delay locked loop for high speed

1 and 2 are block diagrams showing a conventional DLL circuit.

3 is an operation timing diagram of the DLL circuit of FIGS. 1 and 2.

4 is a block diagram illustrating a DLL circuit according to a preferred embodiment of the present invention.

FIG. 5 is a circuit diagram illustrating the variable delay circuit of FIG. 4.

6 is a circuit diagram illustrating a phase comparator of FIG. 4.

7A to 7C illustrate waveforms of signals input to the phase comparator of FIG. 6.

8A and 8B are operation timing diagrams of the DLL circuit of FIG. 4.

<Description of Symbols for Main Parts of Drawings>

11, 21, 110: clock buffer 13, 23, 120: variable delay circuit

15, 25, 130: replicas 16, 26, 140: phase comparators

17, 27, 150: Shifters 14, 24, 160: DLL Driver

The present invention relates to a DLL circuit for high speed operation, and more particularly, to a DLL circuit used for SDRAM of DDR2 / DDR3 / DDR4 that implements high speed (333MHz or more).

In a double data rate (DDR) SDRAM, data is input / output in synchronization with a rising edge and a falling edge of an external clock. At this time, the data output to the outside by the read operation of the DDR SDRAM should be exactly aligned to the edge of the external clock. The DDR SDRAM receives an external clock, delays a predetermined time, generates an internal clock, and controls input and output of data in synchronization with the generated internal clock. By controlling the input and output of the data in this way, the data can be exactly aligned at the edge of the external clock. In this case, a circuit that generates an internal clock by receiving an external clock and delaying a predetermined time is called a delay locked loop (DLL) circuit.

1 and 2 are block diagrams showing a general DLL circuit.

1 and 2, the phase comparator 16 or 26 (phase detector) is output from the clock free control unit 12 or the divider 22 and the replica (compensation delay; 15 or 25; replica). The phases of the feedback clocks FBCLK are compared and output to the shifters 17 and 27, and the variable delay circuit 13 or 23 adjusts the amount of the variable delay in response to a control signal output from the shifters 17 or 27 and is locked. Generate internal clock DLLCLK '. The driver 14 or 24 then uses the internal clock DLLCLK 'to generate a DL clock DLLCLK for controlling the output of the data.

This DLL circuit is set to a long tCK (over 3 ns) to set the initial value of the variable delay of the variable delay circuit 13 or 23 to the minimum delay of the variable delay circuit.

3A and 3B are timing diagrams showing the operation of the DLL circuit shown in Figs. 1 and 2.

As shown in FIG. 3A, when the rising edge of the first feedback clock FBCLK is behind the falling edge of the external clock EXCLK, the rising edge of the feedback clock FBCLK is frozen at the next rising edge of the external clock EXCLK. To lock in, the amount of variable delay of the variable delay circuit 13 or 23 is increased by tDY1 (the amount of delay required for locking).

As shown in Fig. 3B, in the case where the rising edge of the initial feedback clock FBCLK is ahead of the falling edge of the external clock EXCLK, a variable delay circuit (1) is used to align the rising edge of the feedback clock FBCLK to the previous rising edge of the external clock EXCLK. 13, or 23) the amount of variable delay should be reduced. However, since the initial value of the variable delay of the variable delay circuit is set to the minimum delay and thus the amount of the variable delay cannot be reduced, the amount of the variable delay of the variable delay circuits 13 and 23 must be increased by tDY2. In other words, in order to fit the feedback clock FBCLK by approximately one cycle (tCK) to the rising edge of the external clock EXCLK, the conventional DLL circuit adopts a method of increasing the amount of delay.

The DLL circuit shown in Fig. 1 has a circuit which distinguishes Figs. 3A and 3B from a phase comparator 16 which compares the phase of the feedback clock FBCLK and the phase of the external clock EXCLK, and the DLL circuit shown in Fig. In order not to cause the situation as shown in FIG. 3B, that is, to reduce the amount of variable delay, a method of comparing phases by separating the external clock EXCLK is used.

However, the addition of the stuck-free control unit 12 or divider 22 not only increases the current consumption of the DLL circuit but also increases the area, and also increases the probability of occurrence of an operation error, as well as the response time of the DLL circuit. There is a problem of decreasing the response time.

An object of the present invention is to provide a DLL circuit that accurately locks the minimum feedback clock to an external clock by increasing / decreasing the variable delay amount.

According to a preferred embodiment of the present invention, a DLL circuit includes: a clock buffer configured to buffer and output an external clock input from the outside; A variable delay including N unit delay units for delaying the buffered external clock output from the clock buffer and having an initial value of a variable delay set to half of the variable delay amount of the N unit delay units. Circuit; A replica unit for generating a feedback clock by delaying an internal clock output from the variable delay circuit; A phase comparator for comparing a feedback external clock with the feedback clock to generate a delay up signal for increasing the variable delay amount and a delay down signal for reducing the variable delay amount based on an initial value of the variable delay; And a shifter for generating control signals for adjusting the variable delay amount based on the initial value of the variable delay in response to the delay up signal and the delay down signal.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in various different forms, only the embodiments to complete the disclosure of the present invention and complete the scope of the invention to those skilled in the art. It is provided to inform you.

In order to guarantee the operation of a high speed (> 333Mhz) DLL circuit, the present invention excludes a stuck pre-controller or a divider and uses an external clock inputted from the outside without changing the period, and also has a variable delay circuit. By setting half of to the initial value of the variable delay, we propose a DLL circuit that correctly locks the feedback clock to an external clock.

4 shows a DLL circuit according to a preferred embodiment of the present invention.

Referring to FIG. 4, the DLL circuit includes a clock buffer 110, a variable delay circuit 120, a replica 130, a phase comparator 140, a shifter 150, and a DLL driver 160. The clock buffer 110 receives the external clock EXCLK and buffers the output, and the variable delay circuit 120 buffers the external buffered in response to one of the control signals CON <0: n> output from the shifter 150. The clock BEXCLK is delayed and output. The replica 130 delays the internal clock DLLCLK 'output from the variable delay circuit 120 to generate the feedback clock FBCLK. The phase comparator 140 phase compares the external clock EXCLK (or BEXCLK) with the feedback clock FBCLK to reduce the delay amount of the delay up signal DLUP and the variable delay circuit 120 to increase the amount of delay of the variable delay circuit 120. To generate a delay down signal DLDOWN. The shifter 150 generates a control signal CON <0: n> for increasing or decreasing the delay amount of the variable delay circuit 120 in response to the delay up signal DLUP or the delay down signal DLDOWN. Then, the variable delay circuit 120 delays the buffered external clock BEXCLK in response to one of the control signals CON <0: n> output from the shifter 150 and outputs the internal clock DLLCLK 'locked to the external clock. The DLL driver 160 receives the locked internal clock DLLCLK 'and generates a DL clock DLLCLK that controls the output of the data.

FIG. 5 shows a detailed circuit of the variable delay circuit 120 shown in FIG.

Referring to FIG. 5, the variable delay circuit 120 includes N unit delay units 120-1 to 120-n. One unit delay unit (eg, 120-1) includes three NAND gates, and is output from the clock buffer 110 in response to one of the control signals CON <0: n> output from the shifter 150. The buffered external clock BEXCLK is delayed for a predetermined time to generate the locked internal clock DLLCKL '. Here, one unit delay unit is implemented using only three NAND gates. The unit delay unit may be variously implemented using an inverter, a resistor, a capacitor, or the like.

In the present invention, the amount of variable delay is set to have a value 10% greater than one period (1 * tCK) of the smallest frequency (the largest period) among the frequencies of the operating range. In other words, if the operating speed of 333Mhz is the smallest operating frequency of the chip, one cycle (1 * tCK) is 3.0ns and the variable delay has 3.3ns. Further, the initial value of the variable delay is set to n / 2-α (where n is the number of unit delay parts and α is 5%) of the delay amount of the variable delay circuit. That is, the initial value of the variable delay is set to a position having a delay greater than period / 2.

FIG. 6 shows a detailed circuit of the phase comparator 140 shown in FIG.

Referring to FIG. 6, the phase comparator 140 includes a one-step delay unit 151, a first comparator 152, and a second comparator 153. The one-step delay unit 151 delays and outputs the feedback signal FBCLK output from the replica 130 by only the delay amount of one unit delay unit described with reference to FIG. 5. The first comparator 152 compares and outputs the control clock CTRCLK, the external clock EXCLK, and the feedback clock FBCLK, and the second comparator 153 is output from the control clock CTRCLK, the external clock EXCLK, and the one-step delay unit 151. Compare and output the feedback clock FBCLK1. The delay up / down signal generator 154 combines the output signals of the first and second comparators 152 and 153 to increase the amount of delay of the variable delay circuit 120 and the delay up signal DLUP and the variable delay circuit ( A delay down signal DLDOWN is generated to reduce the delay amount of 120).

The one-step delay unit 151 has the same configuration as one unit delay unit (for example, 120-1) of the variable delay circuit 120.

The first comparator 152 includes NAND gate latches ND1 and ND2, NAND gates ND3 and ND4, and NAND gate latches ND5 and ND6. The NAND gate latches ND1 and N2 latch and output the external clock EXCLK and the feedback clock FBCLK. The NAND gate ND3 inverts the logic signal of the control clock CTRCLK and the NAND gate ND1, and the NAND gate ND4 inverts the output signal of the control clock CTRCLK and the NAND gate ND2. The NAND gate latches ND5 and ND6 latch and output the output signals of the NAND gates ND3 and ND4.

The second comparator 153 includes NAND gate latches ND8 and ND9, NAND gates ND10 and ND11, and NAND gate latches ND12 and ND13. The NAND gate latches ND8 and ND9 latch and output the feedback clock FBCLK 'outputted from the external clock EXCLK and the one-step delay unit 151. The NAND gate ND10 inverts and logically multiplies the output signal of the control clock CTRCLK and the NAND gate ND8, and the NAND gate ND11 inverts and logically multiplies the output signal of the control clock CTRCLK and the NAND gate ND9. The NAND gate latches ND12 and ND13 latch and output the output signals of the NAND gates ND10 and ND11.

The delay up / down signal generator 154 includes NAND gates ND7 and ND14, and inverters IV1 and IV2. The NAND gate ND7 inversely logically multiplies the output signal of the NAND gate ND5 of the first comparator 152 with the output signals of the NAND gate ND12 of the second comparator 153. The inverter IV1 inverts the output signal of the NAND gate ND7 to output the delay up signal DLUP. The NAND gate ND14 inverts the output signal of the NAND gate ND6 of the first comparator 152 and the output signals of the NAND gate ND13 of the second comparator 153. The inverter IV2 inverts the output signal of the NAND gate ND14 and outputs a delay down signal DLDOWN.

The phase comparator 140 operates according to the frequencies of the external clock EXCLK and the feedback clock FBCLK, but adjusts the generation of the output signals DLUP and DLDOWN in response to the control clock CTRCLK. That is, by not generating the output signals DLUP and DLDOWN when the control clock CTRCLK is logic low, the overall operation of the DLL circuit is controlled. This control clock CTRCLK has the same frequency as the external clock EXCLK or has a pulse width less than 1 * tCK / 2 of the external clock EXCLK. The control clock CTRCLK can also be used by dividing the external clock EXCLK.

Hereinafter, an operation for locking the feedback clock FBCLK to the external clock EXCLK will be described in detail with reference to FIGS. 4 to 6, 7A to 7B, and 8A and 8B.

7A shows waveforms of the clocks EXCLK, FBCLK, and FBCLK1 for increasing the delay amount of the variable delay circuit 120.

Referring to the left logic state in FIG. 7A, the external clock EXCLK is logic low, the feedback clock FBCLK is logic high, and the feedback clock FBCLK1 is logic high. Therefore, in order to lock the feedback clock FBCLK to the external clock EXCLK, the reference clock FBCLK must be moved to the right. The phase comparator 150 then outputs a logic high delay up signal DLUP to the shifter 150 to move the feedback clock FBCLK to the right, i.e., to increase the amount of delay. Then, the shifter 150 moves the control signal to the variable delay circuit 120 to the left based on the control signal for increasing the delay amount, that is, the initial value of the variable delay (a small position of 5% at half the variable delay amount). Output At this time, the variable delay circuit 120 increases the amount of delay in response to the control signal moved to the left based on the initial value n / 2 ± 10% of the variable delay.

8A illustrates an operation of increasing the amount of delay by T1 based on the initial value of the variable delay of the variable delay circuit 120.

As shown in Fig. 8A, when the rising edge of the feedback clock FBCLK is located after the first falling edge of the external clock EXCLK, that is, when the clocks EXCLK and FBCLK are inputted in the waveform as shown in Fig. 7A, the variable delay is applied. The delay amount is increased by T1 based on the initial value of, aligning the rising edge of the initial feedback clock FBCLK to the next rising edge Tr of the external clock EXCLK. Then, the variable delay circuit 120 generates the internal clock DLLCK 'locked to the rising edge Tr of the external clock EXCLK.

Meanwhile, FIG. 7B illustrates waveforms of the clocks EXCLK, FBCLK, and FBCLK1 for reducing the delay amount of the variable delay circuit 120.

Referring to the right logic state based on the dotted line in FIG. 7B, the external clock EXCLK is logic high, the feedback clock FBCLK is logic low, and the feedback clock FBCLK1 is logic low. Therefore, in order to lock the feedback clock FBCLK to the external clock EXCLK, the reference clock FBCLK must be moved to the left. Then, the phase comparator 150 outputs a logic high delay down signal DLDOWN to the shifter 150 to move the feedback clock FBCLK to the left, that is, to reduce the amount of delay. Then, the shifter 150 outputs a control signal for reducing the delay amount, that is, a control signal moved to the right based on the initial value of the variable delay, to the variable delay circuit 120. In this case, the variable delay circuit 120 reduces the amount of delay in response to the control signal moved to the right based on the initial value of the variable delay.

8B illustrates an operation of reducing the delay amount by T2 based on the initial value of the variable delay of the variable delay circuit 120. As shown in Fig. 8B, in the case where the rising edge of the feedback clock FBCLK is located before the falling edge of the external clock EXCLK, that is, when the external and feedback clocks EXCLK and FBCLK are input in the waveform as shown in Fig. 7B, the variable delay circuit is shown. 120 reduces the amount of delay by T2 based on the initial value of the variable delay to align the rising edge of the feedback clock FBCLK with the previous rising edge of the external clock EXCLK. Then, the variable delay circuit 120 generates the internal clock DLLCK 'locked to the rising edge Tr of the external clock EXCLK. This reduction in the amount of variable delay is possible because the initial value of the variable delay is located at half of the total variable delay amount.

The above-mentioned variable delay amount, that is, the increase or decrease of the delay amount may have a range of 2 ns to 15 ns according to the range of the operating frequency, and is configured to be 10% larger than one period of the smallest operating frequency among the operating frequency ranges of the chip. . If the frequency of the external clock EXCLK is 333 Mhz or more, tCK has 3 x 10 ^ -9 = 3 ns or less. In this case, in the case of FIG. 8A, the delay of T1 may not be greater than 1.5 ns, and T2 of FIG. That is, in the case of reducing or increasing the amount of delay in FIGS. 8A and 8B, if the half cycle (tCK / 2) FBCLK is held, the feedback clock FBCLK may be locked to the external clock EXCLK. However, in order to cope with changes in the chip and various environmental changes, it is necessary to secure a margin of the variable delay, so it is recommended to secure the actual variable delay amount of 3ns + α (α is 10%). As described above, when the frequency of the external clock EXCLK is 333 Mhz or more, the amount of variable delay has 3.3 ns.

7C shows waveforms of the clocks EXCLK, FBCLK, and FBCLK1 so that the delay amount of the variable delay circuit 120 does not increase or decrease.

As shown in FIG. 7C, when the clocks EXCLK, FBCLK, and FBCLK1 have a logic level, the phase comparator 150 generates a delay up signal DLUP and a delay down signal DLDOWN at a logic low level. The delay circuit 1200 does not increase or decrease the amount of delay.

As described above, according to the present invention, the resolution and control of the DLL circuit in the DDR DRAM having a high speed can reduce the possibility of error and improve the response time of the DLL circuit. .

In addition, the elimination of the stuck-free control unit or divider may reduce not only the current consumption of the DLL circuit but also the area.

Claims (11)

A clock buffer for buffering and outputting an external clock input from the outside; A variable delay including N unit delay units for delaying the buffered external clock output from the clock buffer and having an initial value of a variable delay set to half of the variable delay amount of the N unit delay units. Circuit; A replica unit for generating a feedback clock by delaying an internal clock output from the variable delay circuit; A phase comparator comparing the external clock with the feedback clock to generate a delay up signal for increasing the variable delay amount and a delay down signal for reducing the variable delay amount based on an initial value of the variable delay; And And a shifter for generating control signals for adjusting the variable delay amount based on an initial value of the variable delay in response to the delay up signal and the delay down signal. The method of claim 1, And the variable delay amount of the N unit delay units is set to have a value 10% greater than one period (1 * tCK) of the smallest frequency or the largest frequency among the frequencies of the operating range. The method of claim 1, The initial value of the variable delay is set to a value reduced to 5% from the center of the variable delay amount of the N unit delay units, that is, N / 2-5% (N is the number of unit delay units). Circuit. The method of claim 1, And the variable delay circuit delays the buffered external clock by increasing the variable delay amount based on the initial value of the variable delay when the phase comparator generates the delay up signal. The method of claim 1, And wherein the variable delay circuit delays the buffered external clock by reducing the variable delay amount based on the initial value of the variable delay when the phase comparator generates the delay down signal. The method of claim 1, The phase comparator phase compares the feedback clock with the buffered external clock output from the clock buffer to reduce the delay up signal and its variable delay amount to increase the variable delay amount based on the initial value of the variable delay. And generating a delay down signal to cause the signal to be delayed. The method according to claim 1 or 6, Wherein the phase comparator determines whether to operate in response to a control clock. The method of claim 1, The phase comparator may include a one-step delay unit configured to delay the feedback clock only by a delay amount of one unit delay unit of the plurality of unit delay units; A first comparator for comparing the external clock, the feedback clock, and a control clock; And A second comparator for comparing the external clock, the control clock, and a feedback clock output from the one-step delay unit; And And a digital signal generator for combining the output signals of the first and second comparators to generate the delay up signal and the delay down signal. The method of claim 8 The first comparator includes a first latch circuit for latching the external clock and the feedback clock; A logic circuit for logically combining the output signals of the first latch circuit and the control clock; And And a second latch circuit for latching output signals of the logic circuit. The method of claim 8 The second comparator includes a first latch circuit for latching a feedback clock output from the external clock and the one-step delay unit; A logic circuit for logically combining the output signals of the first latch circuit and the control clock; And And a second latch circuit for latching output signals of the logic circuit. The method of claim 8 The digital signal generator comprises: a first logic element for logically combining the output signals of the first and second comparators; A first inverting element inverting an output signal of the first logic element to generate the delay up signal; A second logic element for logically combining the output signals of the first and second comparators; And And a second inversion element inverting the output signal of the second logic element to generate the delay down signal.

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