KR20060123952A - Lcd driving circuit for preventing abnormal diplay and method there-of - Google Patents

Abstract

An LDI(Liquid Crystal Display Driver Integrated Circuit) and a driving method thereof for preventing abnormal display are provided to restrict an image from being abnormally displayed in turning on or off an LCD by applying driving voltage to a liquid crystal panel after the power stabilization time if a display-on command is input before reaching the power stabilization time, and turning off a power circuit with stopping applying the driving voltage to the liquid crystal panel. An LDI for driving and controlling an LCD includes a power circuit unit(220) generating driving voltages(V1~V5) for driving a liquid crystal panel; a driver unit(240) applying the driving voltage to the liquid crystal panel in response to an internal display-on signal(DISP_On) and stopping applying the driving voltage to the liquid crystal panel in response to an internal display-off signal(DISP_Off); and a control logic unit(210) controlling the power circuit unit and the driver unit in response to a command sent from an MPU(Main Processing Unit). The control logic unit generates the internal display-on signal in response to a display-on command. If the display-on command is applied before the time counted by the control logic unit reaches the power stabilization time, the control logic unit generates the display-on signal after the counted time reaches the power stabilization time. The control logic unit generates the internal display-off signal in response to a display-off command if a power-off command is applied before receiving the display-off command.

Description

LCD driving circuit for preventing abnormal diplay and method there-of}

BRIEF DESCRIPTION OF THE DRAWINGS In order to better understand the drawings cited in the detailed description of the invention, a brief description of each drawing is provided.

1 is a flow diagram illustrating a typical LDI operation sequence.

FIG. 2 is a diagram schematically illustrating an internal configuration of a liquid crystal display driving circuit LDI according to an exemplary embodiment of the present invention and a relationship with another module.

FIG. 3 is a block diagram illustrating a more detailed configuration of the control logic unit and the power circuit unit shown in FIG. 2.

4 is a flowchart illustrating a method of driving a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 5 is a detailed circuit diagram of the display on / off control circuit shown in FIG. 3.

6 is a timing diagram illustrating an example of an operation timing of the circuit illustrated in FIG. 5.

FIG. 7 is a timing diagram illustrating another example of the operation timing of the circuit illustrated in FIG. 5.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving circuit of a liquid crystal display (LCD), and more particularly, to prevent abnormal display phenomenon (abnormal screen display) that may occur during a process of turning on or off a liquid crystal display. An LCD driving circuit having an on-chip power circuit.

Currently, the liquid crystal display (TFT-LCD), the flagship product of flat panel displays, has rapidly progressed in size and resolution due to the achievement of mass production technology and research and development. It is widely used in application products, portable electronic devices, and the like.

When the LCD is mounted on an application device, an LCD driving integrated circuit (hereinafter referred to as LDI) mainly operates under the command of the main processing unit (MPU) of the application device and drives the liquid crystal display panel. Let's do it.

1 is a flow diagram illustrating a typical LDI operation sequence.

First, power (VDD, VSS, ground voltage, etc.) required for the operation of the LDI is supplied from the outside (S110), and the LDI is initialized through a hardware reset (H / W Reset) (S112). Next, a command for setting a register necessary for the operation of the power circuit is applied from the MPU (S114), and a power-on command for operating the power circuit is applied (S116). A command for setting a mode is applied (registers of blocks other than the power circuit are set according to this command) (S118), and a display on command is applied (S120). In response to the display command, the LDI applies a driving voltage to the liquid crystal display panel so that the screen display is performed on the liquid crystal display panel. In the display on state (S122), the display off command is applied before the power off command is applied (S124, S126).

As described above, the LDI operates under the command of the external MPU, and a minimum execution time is required for each instruction. Most instructions are handled within one cycle time specified in the LDI AC specification, but in the case of a power-on instruction (Power_On), a significant amount of time is required to achieve a stable power output. The on-chip power circuit in the LDI generates and outputs a driving voltage necessary for driving the liquid crystal display panel in response to the power-on command. Therefore, a considerable time is required for the on-chip analog power circuit to start the voltage generation operation in response to the power-on command to output stable power.

As such, some time is required to output stable power. When a display on command (Display_On) is applied before power is stabilized, an abnormal display phenomenon such as streaks or dots occurs when the LCD panel is turned on. . That is, when the display-on command is applied without a time margin for power stabilization after the power-on command is applied, a bad screen may be displayed on the screen of the liquid crystal panel due to the influence of unstable power.

An abnormal display phenomenon may also occur when a power-off command is applied in a display on state, that is, a voltage is continuously applied from the power circuit to the liquid crystal panel.

The reason why the abnormal display phenomenon as described above occurs when the LDI is mounted and operated in an application device (eg, a mobile phone, etc.) is that the subject (MPU) of command application and the subject (LDI) requiring stabilization time are different. This is because the LDI drive program is different depending on the application device on which it is mounted. In more detail, according to the LDI driving program, the next command may be applied without changing the sequence of commands or considering the time required for power stabilization.

Accordingly, the present invention provides a driving circuit and a driving method thereof for preventing an abnormal display phenomenon (abnormal screen display) that may occur in a process of turning on or off a liquid crystal display.

According to a preferred aspect of the present invention to achieve the above object, in the driving circuit of the liquid crystal display device for driving and controlling the liquid crystal display device mounted on the application device, generating a driving voltage for driving the liquid crystal display panel A power circuit unit; A driver unit applying the generated driving voltage to the liquid crystal display panel in response to an internal display on signal and stopping the application of the generated driving voltage to the liquid crystal display panel in response to an internal display off signal; And a control logic unit controlling the power circuit unit and the driver unit in response to a command from the main processor unit (MPU) of the application device, wherein the control logic unit generates the internal display on signal in response to a display on command, If the display on command is applied before the counted time reaches the predetermined power stabilization time by counting the time, the internal display on signal is output after the counted time reaches the predetermined power stabilization time. And generate the internal display off signal in response to a display off command, and generate the internal display off signal when the power off command is received prior to the reception of the display off command. Provided .

According to another preferred aspect of the present invention to achieve the above object, in the method of driving a liquid crystal display device mounted on an application device, generating an internal display on signal in response to a display on command, but counting the time internally Generating the internal display on signal after the counted time reaches the predetermined power stabilization time if the display on command is applied before the counted time reaches the predetermined power stabilization time; Generating a driving voltage for driving the liquid crystal display panel in response to the power on command; And driving the liquid crystal display panel using the generated driving voltage in response to the internal display on signal.

According to still another aspect of the present invention, there is provided a method of driving a liquid crystal display device mounted in an application device, the method comprising: driving a liquid crystal display panel by generating a driving voltage; Generating an internal display off signal in response to a display off command but generating the internal display off signal if the power off command is received prior to receipt of the display off command; And stopping driving of the liquid crystal display panel in response to the internal display off signal.

According to another preferred aspect of the present invention to achieve the above object, in the method of driving a liquid crystal display device mounted in an application device, receiving a power-on signal-driven in response to the power-on signal Voltages are generated in the power circuit; Counting time in response to the power on signal; If a display on signal is received, checking whether the counted time is greater than a predetermined power stabilization time; And when the counted time is equal to or greater than the predetermined power stabilization time, the driving voltages generated by the power circuit are applied to the liquid crystal display panel, and when the counted time is less than the power stabilization time, Waiting until a counted time is greater than or equal to the power stabilization time and applying the driving voltages to the liquid crystal display panel, wherein the power on signal is generated in response to a power on command of a main processor unit (MPU). The display on signal is generated in response to a display on command of the MPU.

DETAILED DESCRIPTION In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

FIG. 2 is a diagram schematically illustrating an internal configuration of a liquid crystal display driving circuit LDI according to an exemplary embodiment of the present invention and a relationship with another module. Referring to FIG. 2, the LDI 200 includes a control logic unit 210, an on-chip power circuit unit 220, a memory unit 230, and a driver unit 240. The control logic unit 210 receives and decodes a command applied from the MPU 150, and controls each block in the LDI 200 to implement an operation according to the command. The power circuit unit 220 is an on-chip analog circuit and generates a driving voltage in response to the control of the control logic unit 210. The driver 240 drives the liquid crystal display panel 160 using the driving voltage generated by the power circuit unit 200 in response to the control of the control logic unit 210. The memory unit 230 is an LDI other block and includes a memory.

3 is a diagram for describing in more detail the operations of the control logic unit 210, the power circuit unit 220, and the driver unit 240 shown in FIG. 2.

The control logic unit 210 includes a command decoder 213 and a display on / off control circuit 215. The command decoder 213 receives commands (power on / off command, display on / off command) applied from the MPU 150 and decodes the same to generate internal signals PWR_OnOff and DISP_OnOff corresponding to the received command. Internal signals corresponding to the command (PWR_OnOff, DISP_OnOff) are sent to the block or circuit. For example, when a power on command is applied from the MPU 150, the command decoder 213 decodes it and sends a power on signal PWR_OnOff to the power circuit unit 220.

The display on / off control circuit 215 is a circuit added to the control logic unit 210 to prevent abnormal display of the screen displayed on the liquid crystal display panel 160, and the driving voltage generator 221 of the power circuit unit 220. The timing at which the driving voltages V1 to V5 generated in the control panel 1 is applied is controlled. Specifically, the time point at which the driving voltages V1 to V5 are applied to the liquid crystal display panel 160 is controlled by the internal display on / off control signal IN_DISP_OnOff generated by the display on / off control circuit 215.

Specifically, the power circuit unit 220 includes a driving voltage generator 221 and a clock signal generator 223. The clock signal generator 223 generates the reference clock OSC_CLK necessary for the operation of the display on / off control circuit 215. The driving voltage generator 221 generates driving voltages V1 to V5 having a plurality of voltage levels.

The driver unit 240 includes a switching unit 241 positioned on a path between the driving voltage generator 221 and the liquid crystal display panel 160. The switching unit 241 includes a plurality of switches that are opened and closed in response to the internal display on-off control signal IN_DISP_OnOff. The switching unit 241 is turned on (the switch is closed) in response to an internal display on control signal (in this embodiment, the first logic level or rising edge of the internal display on / off control signal), thereby driving voltages V1 to V5. The liquid crystal display panel 160 is applied to the liquid crystal display panel 160. On the other hand, the switching unit 241 is turned off in response to the internal display off control signal (second logic level or falling edge of the internal display on / off control signal in this embodiment), and the driving voltages V1 to V5) is not applied to the liquid crystal display panel 160.

4 is a flowchart illustrating a method of driving a liquid crystal display according to an exemplary embodiment of the present invention. The driving method of the liquid crystal display according to the exemplary embodiment of the present invention is performed by the logic controller 210 of FIG. 3, in particular, by the display on / off control circuit 215.

3 and 4, a driving method of a liquid crystal display according to an exemplary embodiment of the present invention will be described.

When the power-on command is received (S412), counting time starts in response to the power-on command (S414). In addition, in response to the power on command, the power circuit unit 220 starts to generate driving voltages for driving the liquid crystal display panel 160. When receiving the display on command, it is checked whether the counted time is equal to or greater than the predetermined power stabilization time (S418). If the counted time is equal to or greater than the power stabilization time, the driving voltage generated in the power circuit unit is controlled to be applied to the liquid crystal panel (S422). If the counted time is less than the power stabilization time, time counting is continued but the driving voltage is continued. Is not applied to the liquid crystal display panel (S420). That is, if the counted time is less than the power stabilization time, the counter waits until the count time reaches the power stabilization time and then applies driving voltages to the liquid crystal display panel.

When the driving voltages are applied to the liquid crystal panel, the display on state is maintained (S424). When the display off command is received in the display on state (S426), the application of the driving voltage to the liquid crystal display panel is immediately stopped (S430). If the power-off command is first received before the display-off command in the display on state, the application of the driving voltage to the liquid crystal display panel is immediately stopped and the power circuit is turned off (S432).

As described above, according to the LCD driving method according to the present invention, when the display on command is input even before the stable power is generated after the operation of the power circuit, that is, before the power stabilization time is reached, the power stabilization time waits for the power ( The driving voltage) is applied to the liquid crystal display panel to prevent a screen abnormality that may occur during the process of turning on the liquid crystal display. In addition, when the power off command is applied before the display off command, a screen abnormality may occur due to the power circuit being turned off while power (driving voltage) is applied to the liquid crystal display panel. If the power-off command is applied before the command, stop the application of the driving voltage to the liquid crystal display panel in response to the power-off command and turn off the power circuit to prevent screen abnormality that may occur in the process of turning off the liquid crystal display device do.

FIG. 5 is a detailed circuit diagram of the display on / off control circuit 215 shown in FIG.

Referring to this, the display on / off control circuit 215 includes a clock divider 511, a counter 513, a comparator 515, a multiplexer 517, and a plurality of logic gates 521, 523, and 525. do.

The clock divider 511 divides the reference clock OSC_CLK to generate a divided clock. Here, the reference clock OSC_CLK is a clock signal that is applied from the MPU or generated by an internal clock signal generator (see 223 of FIG. 3) mounted inside the LDI chip. The reference clock OSC_CLK has a relatively high frequency, so that the size of the counter 513 may be large to use the reference clock OSC_CLK for counting. Therefore, by dividing the reference clock (OSC_CLK), to generate a relatively low frequency divided clock, which is used for counting, the size of the counter is reduced.

The OR gate 521 performs an OR on the divided clock signal and the display control flag signal (output signal of the comparator) and outputs the logical OR. The output signal of the OR gate 521 is input to the input signal of the counter 513. The AND gate 523 logically outputs the reset signal RESET and the power on / off signal PWR_OnOff.

The output signal of the AND gate 523 is input as a reset signal of the counter 513. The power on off signal PWR_OnOff becomes the first logic level when the power on command is applied and becomes the second logic level when the power off command is applied. In the present embodiment, it is assumed that the first logic level is a high level (1), and the second logic level is a low level (0). Therefore, the power on off signal PWR_OnOff is a high enable signal.

The counter 513 is an N (an integer greater than or equal to 1) bit counter. The counter 513 counts a signal output from the OR gate 521 and outputs a counted time TIME_CNT, which is reset in response to an output signal of the AND gate 523. do. The comparator 515 outputs the display control flag signal DISP_CTRL_FLAG by comparing the counted time TIME_CNT with the power stabilization time TIME_VAL. Here, the power stabilization time TIME_VAL is a time from when the power circuit unit starts to operate and the stabilized driving voltage is output, and is preferably set in advance. The power stabilization time can be determined by testing. The power stabilization time TIME_VAL may also be set or changed anew.

Specifically, the comparator 515 outputs a display control flag signal DISP_CTRL_FLAG of 0 when the counted time TIME_CNT is less than the power stabilization time TIME_VAL, and otherwise, a display control flag signal of 1 ( DISP_CTRL_FLAG). When the display control flag signal DISP_CTRL_FLAG is '0', the counting operation of the counter 513 is continuously performed. When the display control flag signal DISP_CTRL_FLAG is '1', the input signal of the counter 513 is '1'. ', The counting operation of the counter 513 is stopped.

The display control flag signal DISP_CTRL_FLAG is input to the selection signal s of the multiplexer 517.

The multiplexer 517 selects one of the reset signal RESET and the display on-off signal DISP_OnOff inverted by the inverter 525 according to the display control flag signal DISP_CTRL_FLAG and outputs it as the internal display on-off signal IN_DISP_OnOff. do. When the display control flag signal DISP_CTRL_FLAG is '0', the inverted signal of the reset signal is selected and output as the internal display on-off signal IN_DISP_OnOff. Therefore, the internal display on off signal IN_DISP_OnOff becomes 0 (off state). On the other hand, when the display control flag signal DISP_CTRL_FLAG is '1', the received display on-off signal DISP_OnOff is selected and output as the internal display on-off signal IN_DISP_OnOff. The display on-off signal DISP_OnOff is a signal that is 1 when the display on command is applied and becomes 0 when the display off command is applied.

FIG. 6 is a timing diagram illustrating an example of operation timing of the circuit of FIG. 5. 6 is an operation timing diagram when the display on command is received before the power stabilization time is reached and when the power off command is applied in the display on state.

The reset signal RESET is a signal for hardware reset of the LDI chip, and is typically a signal applied to the LDI chip through an external pin. As shown in FIG. 6, the reset signal RESET becomes '0' for a predetermined time and then recovers to '1'. When the power on off signal PWR_OnOff changes from 0 to 1 in response to the application of the power on command, a reference clock is generated from the internal oscillator in response to the rising edge of the power on off signal PWR_OnOff. 513 starts the operation, and the counted time TIME_CNT is output.

When the counted time TIME_CNT reaches the power stabilization time TIME_VAL, the display control flag signal DISP_CTRL_FLAG becomes '1'. The display control flag signal DISP_CTRL_FLAG becomes '1' after the power stabilization time TIME_VAL and then becomes '0' in response to the falling edge of the power-on command, that is, the power-on-off signal PWR_OnOff.

As shown in FIG. 6, even if the display on command is applied before the power stabilization time TIME_VAL is reached, the internal display on-off signal IN_DISP_OnOff becomes 1 in response to the rising edge of the display control flag signal DISP_CTRL_FLAG. After the power stabilization time (TIME_VAL), it becomes '1'. The internal display on-off signal IN_DISP_OnOff, which has kept '1' after the power stabilization time TIME_VAL, becomes '0' in response to the falling edge of the power-off command, that is, the power-on-off signal.

FIG. 7 is a timing diagram illustrating another example of the operation timing of the circuit illustrated in FIG. 5. 7 is an operation timing diagram when the display on command is received after the power stabilization time TIME_VAL and when the display off command is applied before the power off command is applied.

As shown in FIG. 7, when the display on command is received after the power stabilization time TIME_VAL, the internal display on-off signal IN_DISP_OnOff becomes '1'. In addition, when the display off command is applied before the power off command is applied, the internal display on-off signal IN_DISP_OnOff becomes '0' in response to the display off command immediately. Therefore, the case of FIG. 7 is the same as that of the normal display on / off control.

Although the present invention has been described with reference to the embodiments shown in the drawings, this is merely exemplary, and it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. Therefore, the true scope of protection of the present invention should be defined only by the appended claims.

As described above, according to the present invention, when the display on command is input even before the stable power is generated after the operation of the power circuit, that is, before the power stabilization time is reached, the liquid crystal display is waited for the power stabilization time. By applying to the panel, a screen abnormality that may occur during the process of turning on the liquid crystal display may be prevented. In addition, according to the present invention, by stopping the application of the driving voltage to the liquid crystal display panel in response to the power off command and by turning off the power circuit, screen abnormality that may occur in the process of turning off the liquid crystal display device can also be prevented. Therefore, according to the present invention, abnormal screen display of the liquid crystal display device is prevented, so that the reliability of the operation of the LCD-equipped application product is improved.

Claims (14)

In the driving circuit of the liquid crystal display device for driving and controlling the liquid crystal display device mounted on the application device, A power circuit unit generating a driving voltage for driving the liquid crystal display panel; A driver unit applying the generated driving voltage to the liquid crystal display panel in response to an internal display on signal and stopping the application of the generated driving voltage to the liquid crystal display panel in response to an internal display off signal; And Control logic section for controlling the power circuit section and the driver section in response to a command from the main processor unit (MPU) of the application device Including but not limited to: The control logic unit The counted time is generated when the display on command is generated before the counted time reaches a predetermined power stabilization time by generating the internal display on signal in response to a display on command. The internal display on signal is generated after the power stabilization time is reached, and the internal display off signal is generated in response to a display off command, but the internal display off when the power off command is received before the display off command is received. A drive circuit for a liquid crystal display device, which generates a signal. The method of claim 1, The power circuit unit starts operation in response to a power-on command, And the predetermined power stabilization time is a time from an operation time point of the power circuit unit to a time point at which a stabilized driving voltage is generated. The method of claim 2, wherein the power stabilization time is It is possible to change and set the drive circuit of a liquid crystal display device. The method of claim 1, The power circuit unit includes a driving voltage generator for generating the driving voltage, And the driver unit comprises a switching circuit which is opened and closed in response to the internal display on signal and the internal display off signal. The method of claim 4, wherein And the internal display on signal and the internal display off signal are represented by internal display on / off signals having two or more logic levels. The method of claim 5, wherein the control logic unit An instruction decoder for decoding an instruction signal from the main processing unit of the application device; And The display on-off control circuit for generating the internal display on-off signal The driving circuit of the liquid crystal display device comprising a. The method of claim 6, wherein the display on off control circuit A counter for outputting a counted time by counting a clock signal in response to a power on / off signal; A comparator for generating a display control flag signal by comparing the counted time with the power stabilization time; And A signal generator for generating the internal display on-off signal in response to the display control flag signal and a display on-off signal Including; The power on off signal is a signal that the logic level is shifted in response to the power on command and the power off command, And wherein the display on / off signal is a signal of which a logic level is shifted in response to the display on command and the display off command. The method of claim 7, wherein the counter Receiving an AND signal of the display control flag signal and the clock signal as an input signal, And a reset signal and a logical product signal of the power on / off signal. 9. The apparatus of claim 8, wherein the signal generator And a multiplexer which selects any one of an inverted signal of the reset signal and the display on / off signal in response to the display control flag signal to generate the internal display on / off signal. In the driving method of the liquid crystal display device mounted to the application device, The counted time is generated when the display on command is generated before the counted time reaches a predetermined power stabilization time by generating an internal display on signal in response to a display on command but counting time internally. Generating the internal display on signal after a stabilization time has been reached; Generating a driving voltage for driving the liquid crystal display panel in response to the power on command; And Driving the liquid crystal panel using the generated driving voltage in response to the internal display on signal Method of driving a liquid crystal display comprising a. The method of claim 10, wherein generating the internal display on signal comprises: Receiving a power on signal, the drive voltages being generated in a power circuit in response to the power on signal; Counting time in response to the power on signal; If a display on signal is received, checking whether the counted time is greater than a predetermined power stabilization time; And Generating the internal display on signal when the counted time becomes equal to or greater than the predetermined power stabilization time as a result of the check; Method of driving a liquid crystal display device comprising a. In the driving method of the liquid crystal display device mounted to the application device, Generating a driving voltage to drive the liquid crystal display panel; Generating an internal display off signal in response to a display off command but generating the internal display off signal if the power off command is received prior to receiving the display off command; And And stopping driving of the liquid crystal display panel in response to the internal display off signal. In the driving method of the liquid crystal display device mounted to the application device, Receiving a power on signal, the drive voltages being generated in a power circuit in response to the power on signal; Counting time in response to the power on signal; If a display on signal is received, checking whether the counted time is greater than a predetermined power stabilization time; And As a result of the check, when the counted time is equal to or greater than the predetermined power stabilization time, the driving voltages generated by the power circuit are applied to the liquid crystal display panel, and when the counted time is less than the power stabilization time, the counting time is applied. Waiting until the set time exceeds the power stabilization time and applying the driving voltages to the liquid crystal display panel Including but not limited to: The power on signal is generated in response to a power on command of the main processor unit (MPU), And the display on signal is generated in response to a display on command of the MPU. The method of claim 13, wherein the driving method of the liquid crystal display device is Stopping the application of the driving voltages to the liquid crystal display panel in response to at least one of a display off signal and a power off signal Include more, The power off signal is generated in response to a power off command of the MPU, And the display off signal is generated in response to a display off command of the MPU.

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