KR20060123816A - Method for forming device isolation of semiconductor device - Google Patents

Abstract

A method for forming an isolation layer in a semiconductor device is provided to prevent a moat from being generated by removing a pad nitride layer by a dry etch process using CH3F in a process for forming an isolation layer. A pad oxide layer(202) and a pad nitride layer(204) are sequentially deposited on a silicon substrate(200). After a trench is formed in a predetermined region of the silicon substrate, an insulation material(210) is gap-filled. A planarization process is performed on the insulation material to expose the pad nitride layer. An oxide layer formed on the pad nitride layer is removed by a first dry etch process. The pad oxide layer and the pad nitride layer are removed by a second dry etch process. The first dry etch process is performed in a mixture gas atmosphere including CH3F, CF4, O2 and Ar in which a ratio of CH3F to CF4 is not higher than 1.5. The second dry etch process is performed in a mixture gas atmosphere including CH3F, CF4, O2 and Ar in which a ratio of CH3 to CF4 is not higher than 2.

Description

METHODS FOR FORMING DEVICE ISOLATION OF SEMICONDUCTOR DEVICE}

1A to 1E are process flowcharts illustrating a process of forming an isolation layer on a semiconductor substrate according to a conventional method;

2A to 2G are process flowcharts illustrating a process of forming an isolation layer on a semiconductor substrate in accordance with an embodiment of the present invention.

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method of forming a device isolation film of a semiconductor device suitable for forming a device isolation film used for electrically separating a plurality of devices formed on a semiconductor substrate. .

As is well known, semiconductor devices have a large number of unit devices, such as transistors and capacitors, limited by the capacity of the semiconductor device (eg, thousands to billions), which are integrated for independent operation. It is necessary to isolate (or isolate) electrically.

Accordingly, as a method for electrical separation between such semiconductor devices, a silicon substrate (LOCOS: LOCal Oxidation of Silicon) that recesses the silicon substrate and grows a field oxide layer and the silicon substrate is etched in a vertical direction. Shallow Trench Isolation (STI), which is embedded with an insulating material, is well known.

Among them, the shallow trench isolation method is a method of forming narrow and deep shallow trenches by using dry etching methods such as reactive ion etching and plasma etching, and gap fill the insulating film therein. It is an advantageous method for miniaturization by reducing the area occupied by the separation region.

1A to 1E are process flowcharts illustrating a process of forming a device isolation film on a semiconductor substrate according to a conventional method, and a method of forming a device isolation film according to a conventional method will be described with reference to these drawings.

Referring to FIG. 1A, a pad oxide film 102 is formed on a silicon substrate 100 doped with a conductive impurity (ie, P-type), and a pad nitride film (as a shallow trench pattern film) is formed on the pad oxide film 102. 104) is deposited in order. For example, the pad oxide film 102 is formed to be approximately 40 kPa thick, and the pad nitride film 104 is formed to be approximately 1000 kPa thick.

In order to define a device isolation region by performing a photolithography and a dry etching process, for example, 3500 Å to 4500 Å from the pad nitride film 104 to a predetermined depth of the silicon substrate 100 is defined according to the photoresist pattern 106. Etching forms the shallow trench 108 as shown in FIG. 1B. Here, an oxide film may be formed on the surface of the shallow trench 108 through a wet or dry etching process, and the oxide film may be uniformly formed on the side and bottom of the shallow wrench 108 in a thickness of approximately 40 kW.

Next, by removing the photoresist pattern 106 and performing a deposition process using CVD as shown in Figure 1c, as an insulating material 110 that can completely gap-fill the inside of the trench 108 An oxide film is deposited on the silicon substrate 100. Here, the deposition process is performed using, for example, a method such as PE-CVD (Plasma Enhanced Chemical Vapor Deposition), HDP-CVD (High Density Plasma Chemical Vapor Deposition), or the like. do.

As shown in FIG. 1D, the insulating material 110 is exposed to a top surface of the pad nitride layer 104 of the silicon substrate 100 on which the shallow trench 108 is not formed by performing a chemical mechanical polishing (CMP) process. Remove evenly.

Finally, as the device isolation layer embedded with the internal insulating material of the silicon substrate 100 as shown in FIG. 2E, the pad nitride layer 104 and the pad oxide layer 102 are sequentially removed through a wet etching process. The shallow trench isolation layer 110a is formed.

However, in the case of forming the device isolation layer according to the conventional method described above, when the pad nitride layer is removed, a trench upper edge is eroded as shown in FIG. 1E while performing a wet etching process, thereby causing a moat. Deterioration of the electrical characteristics of semiconductor devices and trenches by inducing a hump phenomenon in which the transistor at the edge of the current-voltage graph of the transistor turns on first and an inverse narrow width effect (INWE) phenomenon in which the threshold voltage of the transistor is lowered There was this.

Accordingly, the present invention is to solve the problems of the prior art, a device isolation film of a semiconductor device that can prevent the generation of the mott by removing the pad nitride film by a dry etching process using CH3F in the device isolation film forming process of the semiconductor device. The purpose is to provide a formation method.

Another object of the present invention is to provide a method of forming a device isolation layer of a semiconductor device capable of preventing the Hump phenomenon and the INWE phenomenon caused by the generation of the mott during the device isolation layer formation process of the semiconductor device.

In order to achieve the above object, the present invention is a method of forming a device isolation film of a semiconductor device, the process of sequentially depositing a pad oxide film, a pad nitride film on a silicon substrate, and after forming a trench in a predetermined region of the silicon substrate, Gap-filling the insulating material, planarizing the insulating material to expose the pad nitride film, removing the oxide film formed on the pad nitride film through a first dry etching process, and performing a second dry etching process. The method provides a device isolation film forming method of a semiconductor device, the method including removing the pad oxide film and the pad nitride film through the same.

The above and other objects and various advantages of the present invention will become more apparent from the preferred embodiments of the present invention described below with reference to the accompanying drawings by those skilled in the art.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The core technology of the present invention is different from the conventional method of removing the pad oxide film and the pad nitride film, which are used to form a new trench separator in the process of forming a device isolation layer of a semiconductor device, by a wet etching process. After sequentially depositing a nitride film, forming a trench in a predetermined region of the silicon substrate, gap insulating the material, and planarizing the insulating material to expose the pad nitride film, and then forming an oxide film on the pad nitride film through the first dry etching process. By removing and removing the pad nitride film and the pad nitride film through the second dry etching process, it is possible to easily achieve the object of the present invention through this technical means.

2A to 2G are process flowcharts illustrating a process of forming an isolation layer on a semiconductor substrate according to an embodiment of the present disclosure. A method of forming the isolation layer according to an embodiment of the present disclosure will be described with reference to these drawings. .

Referring to FIG. 2A, a pad oxide film 202 is formed on a silicon substrate 200 doped with a conductive impurity (ie, P-type), and a pad nitride film (as a shallow trench pattern film) is formed on the pad oxide film 202. 204 is deposited in order.

Then, the wafer is etched from the pad nitride film 204 to a predetermined depth of the silicon substrate 200 according to the photoresist pattern 206 to define a device isolation region by performing a photo and dry etching process, as shown in FIG. 2B. Trench 208 is formed. Here, an oxide film may be formed on the surface of the shallow trench 208 through a wet or dry etching process.

Next, by removing the photoresist pattern 206 and performing a deposition process using CVD as shown in Figure 2c, as an insulating material 210 that can completely gap-fill the inside of the trench 208 An oxide film is deposited on the silicon substrate 200. Here, the deposition process is performed using, for example, a method such as PE-CVD (Plasma Enhanced Chemical Vapor Deposition), HDP-CVD (High Density Plasma Chemical Vapor Deposition), or the like. do.

As shown in FIG. 2D, the insulating material 210 is formed to expose the upper portion of the pad nitride layer 204 of the silicon substrate 200 in which the shallow trench 208 is not formed by performing a chemical mechanical polishing (CMP) process. Remove evenly. In this case, although not shown in FIG. 2D, a native oxide film may be formed on the upper surface of the pad nitride film 204.

Next, as illustrated in FIG. 2E, an oxide film (not shown) that may be formed on the surface of the pad nitride film 204 is removed through the first dry etching process. Here, the first dry etching process is performed using a mixed gas containing CH ₃ F, CF ₄ , O ₂ , Ar, pressure of 140 mT-160 mT, source power of 200 W-400 W, 100 W-200 W bias power, 10 sccm-30 sccm CH ₃ F, 10 sccm-20 sccm CF ₄ , 30 sccm-70 sccm O ₂ , 100 sccm-400 sccm Ar, is performed on CF ₄ The ratio of CH ₃ F to 1.5 or less and the etching selectivity to less than 5.

Finally, as shown in FIG. 2F, the pad nitride film 204 and the pad oxide film 202 are removed through a second dry etching process, thereby filling the silicon substrate 200 with an internal insulating material as shown in FIG. 2G. The shallow trench isolation layer 210a is formed as an element isolation layer. Here, the second dry etching process is performed using a mixed gas containing CH ₃ F, CF ₄ , O ₂ , Ar, pressure of 140 mT-160 mT, source power of 200 W-400 W, 0 W-200 W bias power, 20 sccm-30 sccm CH ₃ F, 10 sccm-20 sccm CF ₄ , 150 sccm-250 sccm O ₂ , 100 sccm-400 sccm Ar, is performed on CF ₄ It is carried out with the ratio of CH ₃ F to 2 or more.

Accordingly, by removing the pad nitride layer and the pad oxide layer by using the first dry etching process and the second dry etching process, the device isolation layer may be formed to prevent mott generation.

As described above, the present invention, unlike the conventional method of removing the pad oxide film and the pad nitride film formed on the silicon substrate by using a wet etching process in the process of forming a device isolation layer of the semiconductor device, the pad oxide film, the pad nitride film on the silicon substrate After sequentially depositing the trenches, forming trenches in a predetermined region of the silicon substrate, gap-filling the insulating material, and planarizing the insulating material to expose the pad nitride film, and then forming an oxide film formed on the pad nitride film through the first dry etching process. By removing the pad nitride layer and the pad nitride layer through the second dry etching process, the pad oxide layer and the pad nitride layer are removed by performing the dry etching process in the process of forming the device isolation layer of the semiconductor device, thereby preventing the generation of motes.

In addition, a dry etching process may be performed in the process of forming a device isolation layer of the semiconductor device to remove an oxide film that may be formed on the pad nitride layer, and to form a device isolation layer of the semiconductor device to prevent hump generation and INWE.

Claims (6)

As a method of forming a device isolation film of a semiconductor device, Sequentially depositing a pad oxide film and a pad nitride film on a silicon substrate, Forming a trench in a predetermined region of the silicon substrate, and then gap filling an insulating material; Planarizing the insulating material to expose the pad nitride layer; Removing an oxide film formed on the pad nitride film through a first dry etching process; Removing the pad oxide layer and the pad nitride layer through a second dry etching process Device isolation film formation method of a semiconductor device comprising a. The method of claim 1, The first dry etching process is performed in a mixed gas atmosphere containing CH ₃ F, CF ₄ , O ₂ , Ar having a ratio of CH ₃ F to CF ₄ of 1.5 or less, and the second dry etching process is CF _A method of forming a device isolation film for a semiconductor device, characterized by performing in a mixed gas atmosphere containing CH ₃ F, CF ₄ , O ₂ , Ar having a ratio of CH ₃ F to ₄ of 2 or more. The method of claim 2, Wherein the first dry etching process is performed under a pressure range of 140 mT to 160 mT, a source power source of 200 W to 400 W, and a bias power source of 100 W to 200 W. The method of claim 2, The first dry etching process is performed using 10 sccm-30 sccm CH ₃ F, 10 sccm-20 sccm CF ₄ , 30 sccm-70 sccm O ₂ , 100 sccm-400 sccm Ar A device isolation film forming method of a semiconductor device. The method of claim 2, Wherein the second dry etching process is performed under a pressure in a range of 140 mT to 160 mT, a source power source of 200 W to 400 W, and a bias power source of 0 W to 200 W. The method of claim 2, The second dry etching process is performed using 20 sccm-30 sccm CH ₃ F, 10 sccm-20 sccm CF ₄ , 150 sccm-250 sccm O ₂ , 100 sccm-400 sccm Ar A device isolation film forming method of a semiconductor device.

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