KR20060123806A - Method of manufacturing the stacked semiconductor device - Google Patents

Abstract

A method for manufacturing a stacked semiconductor device is provided to reduce erosion of a single crystalline silicon layer pattern by forming differently a lower metal silicide layer and a lateral metal silicide layer in the thickness. A plurality of interlayer dielectrics are formed on a single crystalline silicon substrate(100). A single crystalline silicon layer pattern(108a) is formed between the interlayer dielectrics. A contact hole for exposing a sidewall of the single crystalline silicon layer pattern and a part of the single crystalline silicon substrate is formed by etching sequentially the interlayer dielectrics. A first metal silicide layer(142) having a first thickness is formed on the exposed single crystalline silicon substrate. A second metal silicide layer(144) thinner than the first metal silicide layer is formed on a sidewall of the single crystalline silicon layer.

Description

Method of manufacturing the stacked semiconductor device

1 is a cross-sectional view showing a defect occurring when forming a contact plug in a conventional stacked semiconductor device.

2 to 10 are cross-sectional views illustrating a method of manufacturing a stacked semiconductor device including a metal silicide film according to Embodiment 1 of the present invention.

11 to 14 are cross-sectional views illustrating a method of manufacturing a stacked semiconductor device including a metal silicide film according to Embodiment 2 of the present invention.

The present invention relates to a method of manufacturing a semiconductor device. More specifically, a method of manufacturing a stacked semiconductor device provided with a single crystal silicon film and a contact plug for connecting with the single crystal silicon film is disclosed.

In order to continuously integrate a semiconductor device, the size of a pattern formed on a chip and the distance between the formed patterns are gradually reduced. However, when the size of the pattern is reduced as described above, problems such as the resistance of the conductive pattern is greatly increased. Therefore, there is a limit to increasing the degree of integration by reducing the size of the pattern. Therefore, recently, in order to highly integrate the semiconductor device, stack type semiconductor devices in which semiconductor unit elements such as MOS transistors are stacked on a substrate have been developed.

In particular, in the SRAM device of the semiconductor memory device, since the unit cell is implemented with six transistors, the cell area is very large. Therefore, the cell area is reduced by stacking transistors constituting the unit cell in the vertical direction.

For example, in a double stack type SRAM device, two pull-down devices and two access devices, an NMOS transistor, are implemented in a semiconductor substrate, and the NMOS transistor is disposed in a single crystal silicon film located on the substrate. Two pull-up devices, PMOS transistors, connected to are implemented. In addition, a triple stack type SRAM device has two pull-down devices, NMOS transistors are implemented in a semiconductor substrate, and two pull-ups connected to the NMOS transistors in a first single crystal silicon film located on the substrate. A PMOS transistor, which is an up-up device, is implemented, and two NMOS transistors, which are two access devices, are implemented on a second single crystal silicon film positioned on the first single crystal silicon film.

In order to implement the stacked SRAM device, gate or contact regions of each transistor stacked on the substrate or single crystal silicon must be electrically connected to each other. For this purpose, a contact plug having a structure in which the single crystal silicon film and the gate electrode of the transistor are in direct contact between the substrate and the single crystal silicon film should be provided. In addition, since the contact resistance of the contact plug must be very small, the contact plug is usually made of a metallic material.

In order to implement the stack-type SRAM device without defects, it is very important to form the contact plug at the correct position to satisfy the complex connection structure of the unit cells of the SRAM device. However, it is difficult to form a contact hole at an accurate position because there are various kinds of films to be etched in the etching process involved in forming the contact plug. In addition, when the contact plug is formed in the contact hole, the contact plug may unexpectedly react with the films in contact with the contact plug. Therefore, process defects frequently occur when the contact plug is formed.

1 is a cross-sectional view showing a defect occurring when forming a contact plug in a conventional stacked semiconductor device.

The contact plug 30 may be formed by performing contact hole formation, barrier metal film 18 and metal film 22 processes. When the contact hole is formed, the sidewall of the single crystal silicon film 14 is partially exposed in the contact hole, so that the contact plug 30 is connected to the upper active region provided as the single crystal silicon film 14.

In the case of forming the barrier metal film 18 having a thickness of about 75 GPa on the sidewalls and the bottom of the contact hole, the barrier metal film 18 and silicon react with the exposed sidewalls of the single crystal silicon film 14 in an annealing process. As a result, the metal silicide layer 20 having an excessive thickness is formed. The metal silicide layer 20 having such an excessive thickness is partially voided by the silicon atoms in the single crystal silicon layer 14 by partially moving toward the metal silicide layer 20 to participate in the silicide reaction. (24) is generated. The voids 24 generated as described above are then filled with a metal material when the metal film 22 is deposited to form the contact plug 30.

For the above reason, when the contact plug is formed, process defects such as the formation of the metal silicide and the metal material to the portion where the single crystal silicon film is to be formed frequently occur. In particular, a contact region (not shown) of a transistor is mainly formed in a single crystal silicon film at a portion that is connected to the contact plug, and in the case where such a process defect occurs, most of the impurity ions constituting the contact region are eroded. The area will not be formed normally. As a result, an operation failure of the semiconductor device occurs and the reliability is lowered.

Although not shown in the drawing, when the barrier metal film is formed to a thickness of about 30 GPa, a metal silicide film having a thin thickness may be formed on the exposed sidewall of the single crystal silicon film, but the metal silicide formed on the surface of the single crystal silicon substrate. The film causes an increase in the resistance of the contact plug due to the lack of forming thickness.

An object of the present invention is to provide a method of manufacturing a stacked semiconductor device including a metal silicide film having a different thickness.

In a method of manufacturing a stacked semiconductor device according to an embodiment of the present invention for achieving the above object, first, a single crystal silicon film stacked between the interlayer insulating films and used as an upper active region is formed on a single crystal silicon substrate. The interlayer insulating layers are sequentially etched to expose the surface of the single crystal silicon substrate to form contact holes exposing sidewalls of the single crystal silicon layer and the surface of the substrate. A lower metal silicide film, which is a first metal silicide film having a first thickness, on the single crystal silicon substrate exposed to the contact hole, and a side metal silicide film, which is a second metal silicide film having a thickness lower than a first thickness, on the sidewall of the single crystal silicon film; Form.

As described above, metal silicide films having different thicknesses are formed on the single crystal silicon sidewall and the single crystal silicon substrate surface exposed by the contact hole, respectively. That is, since the side metal silicide film having a relatively lower thickness than the lower metal silicide film on the sidewall of the contact hole is formed, the single crystal silicon film pattern exposed by the contact hole inner wall is hardly eroded. Therefore, the defective operation of the stacked semiconductor device caused by the erosion of the single crystal silicon film pattern can be reduced, and ultimately, the yield and reliability of the stacked semiconductor device can be improved.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Example 1

2 to 10 are cross-sectional views illustrating a method of manufacturing a stacked semiconductor device including a metal silicide film according to Embodiment 1 of the present invention.

Referring to FIG. 2, a first interlayer insulating film 102 is formed on the single crystal silicon substrate 100. The first interlayer insulating layer 102 may be formed by depositing silicon oxide. For example, the first interlayer insulating layer 102 may be formed by depositing a high density plasma (HDP) oxide or BoroPhosphor Silicate Glass (BPSG). Here, it is preferable that a semiconductor unit element such as a transistor is formed on the substrate 100.

Subsequently, the first interlayer insulating layer 102 is partially etched to form an opening 104 that selectively exposes the surface of the substrate 100. After the opening 104 is formed, a cleaning process may be further performed to remove a natural oxide film formed on the surface of the substrate 100 and a residue present in the opening. For example, the cleaning process may be performed using an etching solution containing hydrofluoric acid (HF).

A preliminary epitaxial layer (not shown) is grown to completely fill the inside of the opening 104 from the substrate exposed on the bottom surface of the opening 104. When the preliminary epitaxial film is grown, growth is not easy if the process temperature is less than about 750 ° C., and if the process temperature exceeds about 1,250 ° C., process control according to the growth of the epitaxial film is easy. It is not desirable because it does not.

Therefore, the growth of the preliminary epitaxial film is preferably performed at a temperature of about 750 to 1,250 ° C, and more preferably at a temperature of about 800 to 900 ° C.

It is preferable that the reaction gas for forming the preliminary epitaxial film includes a silicon source gas. Examples of the silicon source gas include silicon tetrachloride (SiCl ₄ ), silane (SiH ₄ ), dichlorosilane (SiH ₂ Cl ₂ ), trichlorochloride silane (SiHCl ₃ ), and the like. It is preferable to use these individually, and you may mix and use two or more as needed. In this embodiment, mainly silicon tetrachloride is used as the reaction gas.

The preliminary epitaxial film is polished to form an epitaxial film 106 having an upper surface coplanar with an upper surface of the first interlayer insulating film 102.

Referring to FIG. 3, an amorphous silicon film (not shown) is formed on the first interlayer insulating film 102 and the epitaxial film 106. For example, the amorphous silicon film may be formed by performing a chemical vapor deposition process.

Subsequently, the amorphous silicon film is heat-treated to change the amorphous silicon film. The amorphous silicon film is switched to the single crystal silicon film 108 by the phase change.

Specifically, the amorphous silicon film is phase-changed by the heat treatment process, and the silicon material of the epitaxial film 106 acts as a seed, thereby changing the crystal structure of the amorphous silicon film into a single crystal.

Referring to FIG. 4, the single crystal silicon film 108 is selectively etched to form a single crystal silicon film pattern 108a to be provided to the upper active region. Various unit devices including a transistor may be formed on the single crystal silicon layer pattern 108a.

Subsequently, a second interlayer insulating film 110 is formed on the single crystal silicon film pattern 108a and the first interlayer insulating film 102.

Referring to FIG. 5, the second contact hole 112 is formed by partially etching the second interlayer insulating layer 110. Subsequently, the first interlayer insulating layer 102 is partially etched to form a first contact hole 114 communicating with the second contact hole 112. Hereinafter, the second contact hole 112 and the first contact hole 114 will be collectively described as a contact hole 116. By forming the contact hole 116, the second interlayer insulating film 110 and the first interlayer insulating film 102 are converted into a second interlayer insulating film pattern 110a and a first interlayer insulating film pattern 102a. In this case, the contact hole 116 is formed to expose a portion of the single crystal silicon film pattern 108a on an inner surface thereof.

When the contact hole 116 is formed in the epitaxial layer 106 shown in FIG. 4, the process of etching the epitaxial layer 106 as well as the first interlayer insulating layer 102 should be performed. .

Referring to FIG. 6, a first barrier metal layer 120 is formed on sidewalls, bottom surfaces of the contact hole 116, an exposed portion of the single crystal silicon layer pattern, and an upper surface of the second interlayer insulating layer pattern 110a. .

The first barrier metal film 120 may include, for example, titanium, tantalum, cobalt, titanium nitride, tantalum nitride, and cobalt nitride. It is preferable to use these independently, and it can mix and use two or more as needed.

That is, the first barrier metal film 120 may have a single metal film structure or may have a structure in which a metal film / metal nitride film is stacked. It is preferable that the first barrier metal film 120 of this embodiment has a structure in which a titanium film / titanium nitride film is stacked. For example, the metal film is formed to have a thickness of 75 kPa or less, and preferably formed to have a thickness of 50 to 25 kPa.

The first barrier metal layer 120 is preferably formed by a physical vapor deposition process. Since the physical vapor deposition process has a characteristic that it is difficult to form a first barrier metal film having substantially the same thickness in the contact hole, the first barrier metal film is hardly formed on the sidewall of the contact hole. For this reason, the first barrier metal film is formed to have a predetermined thickness only on the exposed portion of the single crystal silicon film pattern and the upper surface of the second interlayer insulating film pattern 110a.

For example, since the process of forming the first barrier metal film is performed at a high temperature, the silicon of the first barrier metal film, the substrate, and the silicon film may inevitably undergo a silicide reaction.

Referring to FIG. 7, an etch back process is performed on the first barrier metal layer 120 to form a first barrier metal layer pattern 120a exposed on the bottom surface of the contact hole 116 and disposed on a single crystal silicon substrate. do.

The etch back process is performed to improve the profile of the contact hole 116 inlet, which is poor due to the first barrier metal film formed by the physical vapor deposition process. Thereafter, a cleaning process may be further performed to remove the etching residue remaining in the contact hole in which the first barrier metal layer pattern 120a is formed. For example, the cleaning process may be performed using an etching solution containing hydrofluoric acid (HF).

Referring to FIG. 8, a second barrier is formed on a sidewall of the contact hole 116 on which the first barrier metal layer pattern 120a is formed, an upper surface of the first barrier metal layer pattern, and an upper surface of the second interlayer insulation layer pattern 110a. The metal film 130 is formed continuously.

The second barrier metal layer 130 may be, for example, titanium, tantalum, cobalt, titanium nitride, tantalum nitride, cobalt nitride, or the like. It is preferable to use these individually, and you may mix and use two or more as needed.

The second barrier metal film 130 may have a single metal film structure or may have a structure in which a metal film / metal nitride film is stacked. It is preferable that the second barrier metal film 130 of this embodiment has a structure in which a titanium film / titanium nitride film is stacked. For example, the metal film is formed to have a thickness of 75 kPa or less, and preferably formed to have a thickness of 50 to 25 kPa.

For example, the titanium film, which is the second barrier metal film 130, may be formed after flowing TiCl ₄ gas into the contact hole. In particular, the second barrier metal film is preferably formed by a chemical vapor deposition process. The chemical vapor deposition process may form a second barrier metal layer 130 having substantially the same thickness in the contact hole to be different from the physical vapor deposition process.

Referring to FIG. 9, a rapid thermal annealing process may be performed to form a single crystal silicon substrate exposed to the contact hole, that is, a lower metal silicide layer, which is a first metal silicide layer 142 having a first thickness, on the bottom surface of the contact hole, and the single crystal A side metal silicide film, which is a second metal silicide film 144 having a second thickness lower than the first thickness, is formed on the sidewall of the silicon film pattern 108a.

The first metal silicide layer 142 may have a first barrier metal layer pattern 120a that is in contact with the substrate and the silicon of the single crystal silicon substrate exposed to the contact hole when the substrate is rapidly heat treated at a temperature of about 850 ° C. or less. It is formed by the silicide reaction. As the first metal silicide layer 142 having the first thickness is formed on the bottom surface of the contact hole 116, the contact resistance decreases. When the first barrier metal film includes a titanium film, the heat treatment temperature is preferably about 650 ° C.

The second metal silicide layer 144 may be interviewed with the silicon of the sidewall of the single crystal silicon layer pattern exposed to the contact hole and the sidewall of the silicon layer pattern when the substrate is rapidly heat treated at a temperature of about 850 ° C. or less. The barrier metal film 130 is formed by silicide reaction. As the second silicide layer 144 having the second thickness lower than the first thickness is formed on the side of the contact hole 116, the contact resistance decreases.

As described above, the thicknesses of the first metal silicide layer 142 and the second metal silicide layer 144 are formed differently so that the second metal silicide layer 142 penetrates to the single crystal silicon layer pattern 108a. The defect that occurs can be reduced. In addition, since the first silicide layer 142 having a thickness greater than that of the second silicide layer 144 is formed, contact resistance between the single crystal silicon substrate 100 and the contact plug electrically connected to the first silicide layer 144 may be reduced.

Referring to FIG. 10, a metal film (not shown) is deposited to fill the inside of the contact hole 116 of the resultant formed first and second metal silicide films, and the second interlayer insulating film pattern 110a is exposed. By planarizing, a contact plug, which is a metal film pattern 122 filling the inside of the contact hole 116, is formed. The contact plug 150 may be formed using tungsten, aluminum, or copper.

Example 2

11 to 14 are cross-sectional views illustrating a method of manufacturing a stacked semiconductor device including a metal silicide film according to Embodiment 2 of the present invention.

The method described below is the same as the semiconductor device manufacturing method described with reference to FIGS. 2 to 10 except for the method of forming the first barrier metal film, the second barrier metal film, and the first and second metal silicide films.

Referring to FIG. 11, the first barrier metal layer 220 formed on the single crystal silicon substrate exposed to the upper surface of the second interlayer dielectric layer and the contact hole 216 may be subjected to a rapid heat treatment process in the physical vapor deposition process. The metal silicide film 225 is formed. The auxiliary metal silicide layer 225 is a third metal silicide layer.

The auxiliary metal silicide layer 225 may be formed of silicon of the single crystal silicon substrate exposed to the contact hole and the first barrier metal layer pattern 220a that is in contact with the substrate when the substrate is rapidly heat treated at a temperature of about 850 ° C. or less. Some are formed by silicide reactions. In the heat treatment process, a process gas including an inert gas and nitrogen is provided. When the first barrier metal film includes a titanium film, the heat treatment temperature is preferably about 650 ° C.

Thereafter, an etching process is performed on the first barrier metal layer, which is not applied to the formation of the auxiliary metal silicide layer 225, using an etching solution. The etching solution may include, for example, sulfuric acid, phosphoric acid, acetic acid, nitric acid, and the like. In the etching process using the etching solution, only the auxiliary metal silicide layer is present on the bottom surface of the contact hole, that is, the single crystal silicon substrate. After performing the etching process, a rinse process for removing the material remaining on the substrate using deionized water is further performed.

Referring to FIG. 12, a second barrier metal layer 230 is continuously formed on an upper surface of the auxiliary metal silicide layer 225, a sidewall of the contact hole 216, and an upper surface of the second interlayer insulating layer pattern 210a. .

The second barrier metal film 230 may include, for example, titanium, tantalum, cobalt, titanium nitride, tantalum nitride, and cobalt nitride. It is preferable to use these individually, and you may mix and use two or more as needed.

The second barrier metal film 230 may have a single metal film structure or may have a structure in which a metal film / metal nitride film is stacked. It is preferable that the second barrier metal film 230 of this embodiment has a structure in which a titanium film / titanium nitride film is stacked. For example, the titanium film, which is the second barrier metal film 230, may be formed after the TiCl ₄ gas flows into the contact hole. In particular, the second barrier metal film is preferably formed by a chemical vapor deposition process. The chemical vapor deposition process may form a second barrier metal layer 230 having a thickness substantially the same as that of the physical vapor deposition process.

Referring to FIG. 13, a lower metal silicide layer 242 is formed by performing a rapid heat treatment process to form a fourth metal silicide layer on the auxiliary metal silicide layer 225, and then on the sidewall of the single crystal silicon layer pattern 208a. A side metal silicide film 244 that is a second metal silicide film having a second thickness is formed.

The fourth metal silicide layer 241 is formed by silicide reaction of the second barrier metal layer 230 that is in contact with the auxiliary metal silicide layer 225 when the substrate is rapidly heat treated at a temperature of about 850 or less. When the second barrier metal film includes a titanium film, the heat treatment temperature is preferably about 650 ° C.

Accordingly, since the fourth metal silicide layer 241 is formed on the auxiliary metal silicide layer 225, a lower metal silicide layer having a thickness greater than that of the second metal silicide 244 layer is formed on the bottom surface of the contact hole 216. 242 is formed. This reduces the contact resistance of the contact plug that is electrically connected to the substrate.

The side metal silicide layer 244 is a second barrier metal that is in contact with the sidewall of the silicon film pattern and the silicon of the sidewall of the single crystal silicon film pattern exposed to the contact hole when the substrate is rapidly heat-treated at a temperature of about 850 or less. The film 230 is formed by silicide reaction. Accordingly, the side metal silicide layer 244 which is a second metal silicide layer having a second thickness lower than the first thickness is formed on the side surface of the contact hole 216. As the side metal silicide layer is formed, the contact resistance is reduced.

As described above, since the thicknesses of the lower metal silicide layer 242 and the side metal silicide layer 244 are formed differently, defects caused by metal penetration into the single crystal silicon layer pattern 208a are reduced. In addition, since the lower metal silicide film 242 having a thickness thicker than the side metal silicide film 244 can be formed, the contact resistance between the single crystal silicon substrate and the contact plug can be reduced.

Referring to FIG. 14, a metal layer (not shown) is deposited to fill an inside of the contact hole 216 in which the lower metal silicide layer 242 and the side metal silicide layer 244 are formed, and the second interlayer insulating layer pattern ( The planarization of the contact hole 216 is performed to form a contact plug that is a metal layer pattern 250 filling the contact hole 216. The metal layer pattern 250 may be formed using tungsten, aluminum, or copper.

As described above, according to the present invention, by forming the lower metal silicide film and the instant metal silicide film to have different thicknesses, it is possible to reduce the erosion of the single crystal silicon film pattern frequently generated when forming the contact plug of the stacked semiconductor device.

In addition, the contact resistance between the single crystal silicon substrate and the contact plug can be reduced. Therefore, the yield and the reliability of the semiconductor device are improved.

As described above, although described with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified without departing from the spirit and scope of the invention described in the claims below. And can be changed.

Claims (15)

Forming a single crystal silicon film pattern used as an upper active region between the interlayer insulating films formed on the single crystal silicon substrate and the interlayer insulating films; Sequentially etching the interlayer insulating layers to expose a surface of the single crystal silicon substrate to form contact holes exposing sidewalls of the single crystal silicon layer pattern and a portion of the single crystal silicon substrate; And Forming a first metal silicide film having a first thickness on the single crystal silicon substrate exposed to the contact hole, and forming a second metal silicide film having a thickness lower than the first thickness on the sidewall of the single crystal silicon film pattern. The manufacturing method of a stacked semiconductor device. The method of claim 1, wherein the forming of the first and second metal silicide layers is performed. Continuously forming a first barrier metal film having a third thickness on the sidewall of the contact hole and having a fourth thickness higher than the third thickness on the bottom of the contact hole; Performing an etch back process and a cleaning process on the first barrier metal film to form a first barrier metal film pattern present only on the bottom surface of the contact hole; Continuously forming a second barrier metal film on the resultant material; And Performing a heat treatment to form a first metal silicide film having a first thickness on the single crystal silicon substrate and a second metal silicide film having a thickness lower than the first thickness on sidewalls of the single crystal silicon film pattern. A method of manufacturing a stacked semiconductor device. The method of claim 2, wherein the first barrier metal film is formed by performing a physical vapor deposition process, and the second barrier metal film is formed by performing a chemical vapor deposition process. The method of claim 2, wherein the first and second barrier metal films are formed by sequentially stacking a titanium film and a titanium nitride film. The method of claim 2, wherein the second metal silicide layer is formed by reacting silicon on the sidewall of the single crystal silicon film with a second barrier metal film interviewed on the sidewall of the single crystal silicon film. The stack type semiconductor device of claim 2, wherein the first metal silicide layer is formed by reacting silicon on the surface of the single crystal silicon substrate with a first barrier metal film pattern interviewed on the surface of the single crystal silicon substrate. Manufacturing method. The method of claim 1, wherein the forming of the first and second metal silicide layers is performed. Continuously forming a first barrier metal film having a third thickness on the sidewall of the contact hole and having a fourth thickness higher than the third thickness on the bottom of the contact hole; Reacting silicon on the surface of the single crystal silicon substrate exposed to the contact hole with the first barrier metal film to form a third metal silicide film; Removing the first barrier metal layer not applied to the third metal silicide layer using a first etching solution; Continuously forming a second barrier metal film on the resultant material; And Performing a heat treatment to form a fourth metal silicide film on the third metal silicide film, thereby forming the first metal silicide film having a first thickness on the sidewall of the single crystal silicon film pattern; A method of manufacturing a stacked semiconductor device, comprising the step of forming a metal silicide film. The method of claim 7, wherein the first barrier metal film is formed by performing a physical vapor deposition process, and the second barrier metal film is formed by performing a chemical vapor deposition process. The method of manufacturing a stacked semiconductor device according to claim 7, wherein the first and second barrier metal films are formed by sequentially stacking a titanium film and a titanium nitride film. The method of claim 7, wherein the first metal silicide layer is formed by stacking the third metal silicide layer and the fourth metal silicide layer. The method of claim 7, wherein the second metal silicide film is formed by reacting silicon of the single crystal silicon film pattern with a second barrier metal film that is interviewed on a surface of the single crystal silicon film pattern. . The method of claim 7, wherein the first cleaning solution comprises sulfuric acid, phosphoric acid, acetic acid, and nitric acid. 8. The method of claim 7, wherein the first and second barrier metal films comprise at least one selected from the group consisting of titanium, tantalum, cobalt, titanium nitride, tantalum nitride, and cobalt nitride. . The method of claim 1, further comprising: cleaning the contact hole with a second cleaning solution containing hydrofluoric acid. The method of claim 1, wherein the forming of the interlayer insulating layers and the single crystal silicon layer pattern having the contact hole is performed. Forming a first interlayer insulating film on the single crystal silicon substrate, the first interlayer insulating film having an opening that partially exposes the surface of the substrate; Forming an epitaxial layer filling the opening by performing selective epitaxial growth with a seed exposed on the bottom surface of the opening; Forming an amorphous silicon film on the epitaxial film and the first interlayer insulating film; Heat treating the amorphous silicon film to convert the amorphous silicon film into a single crystal silicon film; Patterning the single crystal silicon film to form a single crystal silicon film pattern; Forming a second interlayer insulating film on the single crystal silicon film pattern and the first interlayer insulating film; And And sequentially etching the first and second interlayer insulating films to expose a portion of the single crystal silicon film pattern to form contact holes.

Images