KR20060118078A - Method of manufacturing the stacked semiconductor device - Google Patents

Abstract

A method for manufacturing a stack type semiconductor device is provided to restrain the erosion of a single crystal silicon pattern by forming uniformly a metal silicide layer using a nitrogen doped region. A first interlayer dielectric(102a), a single crystal silicon pattern(108a) and a second interlayer dielectric(110a) are sequentially formed on a single crystal silicon substrate(100). The single crystal silicon layer is used as an upper active region. A contact hole for exposing an upper portion of the single crystal silicon substrate and sidewalls of the single crystal silicon pattern to the outside is formed on the resultant structure by etching. A nitrogen doped region(118) is formed at the exposed sidewalls of the single crystal silicon pattern by using a nitrogen ion implantation. A barrier metal is formed along an upper surface of the resultant structure. A heat treatment is performed on the resultant structure to form a lower metal silicide layer on the exposed single crystal silicon substrate and a side silicide layer on the sidewalls of the single crystal silicon pattern.

Description

Method of manufacturing the stacked semiconductor device

1 is a cross-sectional view showing a defect occurring when forming a contact plug in a conventional stacked semiconductor device.

2 to 9 are cross-sectional views illustrating a method of manufacturing a stacked semiconductor device including a metal silicide film according to an embodiment of the present invention.

The present invention relates to a method of manufacturing a semiconductor device. More specifically, a method of manufacturing a stacked semiconductor device provided with a single crystal silicon film and a contact plug for connecting with the single crystal silicon film is disclosed.

In order to continuously integrate a semiconductor device, the size of a pattern formed on a chip and the distance between the formed patterns are gradually reduced. However, when the size of the pattern is reduced as described above, a problem such as the resistance of the conductive pattern is greatly increased. Therefore, there is a limit to increasing the degree of integration by reducing the size of the pattern. Therefore, recently, in order to highly integrate the semiconductor device, stack type semiconductor devices in which semiconductor unit elements such as MOS transistors are stacked on a substrate have been developed.

In particular, in the SRAM device of the semiconductor memory device, since the unit cell is implemented with six transistors, the cell area is very large. Therefore, the cell area is reduced by stacking transistors constituting the unit cell in the vertical direction.

For example, in a double stack type SRAM device, two pull-down devices and two access devices, an NMOS transistor, are implemented in a semiconductor substrate, and the NMOS transistor is disposed in a single crystal silicon film located on the substrate. Two pull-up devices, PMOS transistors, connected to are implemented. In addition, a triple stack type SRAM device has two pull-down devices, NMOS transistors are implemented in a semiconductor substrate, and two pull-ups connected to the NMOS transistors in a first single crystal silicon film located on the substrate. A PMOS transistor, which is an up-up device, is implemented, and two NMOS transistors, which are two access devices, are implemented on a second single crystal silicon film positioned on the first single crystal silicon film.

In order to implement the stacked SRAM device, gate or contact regions of each transistor stacked on the substrate or single crystal silicon must be electrically connected to each other. For this purpose, a contact plug having a structure in which the single crystal silicon film and the gate electrode of the transistor are in direct contact between the substrate and the single crystal silicon film should be provided. In addition, since the contact resistance of the contact plug must be very small, typically the contact plug is made of a metallic material.

In order to implement the stack-type SRAM device without defects, it is very important to form the contact plug at the correct position to satisfy the complex connection structure of the unit cells of the SRAM device. However, it is difficult to form a contact hole at an accurate position because there are various kinds of films to be etched in the etching process involved in forming the contact plug. In addition, when the contact plug is formed in the contact hole, the contact plug may unexpectedly react with the films in contact with the contact plug. Therefore, process defects frequently occur when the contact plug is formed.

1 is a cross-sectional view showing a defect occurring when forming a contact plug in a conventional stacked semiconductor device.

The contact plug 30 may be formed by performing contact hole formation, barrier metal film 18 and metal film 22 processes. When the contact hole is formed, the sidewall of the single crystal silicon film 14 is partially exposed in the contact hole, so that the contact plug 30 is connected to the upper active region provided as the single crystal silicon film 14.

In the case of forming the barrier metal film 18 having a thickness of about 75 GPa on the sidewalls and the bottom of the contact hole, the barrier metal film 18 and silicon react with the exposed sidewalls of the single crystal silicon film 14 in an annealing process. As a result, a metal silicide film 20 having an excessive thickness is formed.

The metal silicide layer 20 having such an excessive thickness is partially voided in the single crystal silicon layer 14 by partially moving silicon atoms in the single crystal silicon layer 14 toward the metal silicide layer 20 to participate in a silicide reaction. (24) is generated. The voids 24 generated as described above are then filled with a metal material when the metal film 22 is deposited to form the contact plug 30.

For the above reason, when the contact plug is formed, process defects such as the formation of the metal silicide and the metal material to the portion where the single crystal silicon film is to be formed frequently occur.

Particularly, a contact region (not shown) of a transistor is mainly formed in a single crystal silicon film of a portion to be connected to the contact plug, and in the case where such a process defect occurs, most of the impurity ions forming the contact region are eroded. The area will not be formed normally. As a result, an operation failure of the semiconductor device occurs and the reliability is lowered.

An object of the present invention is to provide a method of manufacturing a stacked semiconductor device including a metal silicide film having a different thickness.

In the stack-type semiconductor device according to an embodiment of the present invention for achieving the above object, the interlayer insulating films formed on a single crystal silicon substrate and the single crystal silicon film pattern used as the upper active region are interposed between the interlayer insulating films. To form. Subsequently, the interlayer insulating layers are sequentially etched to expose the surface of the single crystal silicon substrate to form contact holes exposing sidewalls of the single crystal silicon pattern and portions of the single crystal silicon substrate. Subsequently, nitrogen is ion implanted into the surface of the sidewall of the single crystal silicon film pattern exposed to the contact hole to form a nitrogen doped region. Subsequently, a barrier metal film is continuously formed on the upper surface of the interlayer insulating structure, the sidewalls and the bottom of the contact hole. The barrier metal film is heat-treated to form a lower metal silicide film on the single crystal silicon substrate exposed to the contact hole, and a side metal silicide film is formed on the sidewall of the single crystal silicon film having the nitrogen doped region. As a result, a stacked semiconductor device including a metal silicide film can be completed.

As described above, by forming a nitrogen doped region on the sidewall of the single crystal silicon film exposed by the contact hole, a metal silicide film having a uniform thickness can be formed in the single crystal silicon substrate and the single crystal silicon film. That is, since the nitrogen doped region formed on the sidewall of the contact hole can prevent the diffusion of silicon applied to form the side metal silicide film, the single crystal silicon film pattern can be prevented from being substantially eroded. Therefore, the malfunction of the stacked semiconductor device caused by the erosion of the single crystal silicon film pattern may be reduced, and ultimately, the yield and reliability of the stacked semiconductor device may be improved.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 to 9 are cross-sectional views illustrating a method of manufacturing a stacked semiconductor device including a metal silicide film according to an embodiment of the present invention.

Referring to FIG. 2, a first interlayer insulating film 102 is formed on the single crystal silicon substrate 100. The first interlayer insulating layer 102 may be formed by depositing silicon oxide. For example, the first interlayer insulating layer 102 may be formed using high density plasma (HDP) oxide or BoroPhosphor Silicate Glass (BPSG). Here, it is preferable that a semiconductor unit element such as a transistor is formed on the substrate 100.

Subsequently, the first interlayer insulating layer 102 is partially etched to form an opening 104 that selectively exposes the surface of the substrate 100. After the opening 104 is formed, a cleaning process for removing a natural oxide film formed on the surface of the substrate 100 and a residue present in the opening may be further performed. For example, the cleaning process may be performed using an etching solution containing hydrofluoric acid (HF).

A preliminary epitaxial layer (not shown) is grown to completely fill the inside of the opening 104 from the substrate exposed on the bottom surface of the opening 104. When the preliminary epitaxial film is grown, growth is not easy if the process temperature is less than about 750 ° C., and if the process temperature exceeds about 1,250 ° C., process control according to the growth of the epitaxial film is easy. It is not desirable because it does not.

Therefore, the growth of the preliminary epitaxial film is preferably performed at a temperature of about 750 to 1,250 ° C, and more preferably at a temperature of about 800 to 900 ° C.

Preferably, the reaction gas for forming the preliminary epitaxial film includes a silicon source gas. Examples of the silicon source gas include silicon tetrachloride (SiCl ₄ ), silane (SiH ₄ ), dichlorosilane (SiH ₂ Cl ₂ ), trichlorochloride silane (SiHCl ₃ ), and the like. It is preferable to use these individually, and you may mix and use two or more as needed. In this embodiment, mainly silicon tetrachloride is used as the reaction gas.

The preliminary epitaxial film is polished to form an epitaxial film 106 having an upper surface coplanar with an upper surface of the first interlayer insulating film 102.

Referring to FIG. 3, an amorphous silicon film (not shown) is formed on the first interlayer insulating film 102 and the epitaxial film 106. For example, the amorphous silicon film may be formed by performing a chemical vapor deposition process.

Subsequently, the amorphous silicon film is heat-treated to change the amorphous silicon film. The amorphous silicon film is switched to the single crystal silicon film 108 by the phase change.

Specifically, the amorphous silicon film is phase-changed by the heat treatment process, and the silicon material of the epitaxial film 106 acts as a seed, thereby changing the crystal structure of the amorphous silicon film into a single crystal.

Referring to FIG. 4, the single crystal silicon film 108 is selectively etched to form a single crystal silicon film pattern 108a to be provided to the upper active region. Various unit devices including a transistor may be formed on the single crystal silicon layer pattern 108a.

Next, a second interlayer insulating film 110 is formed on the single crystal silicon film pattern 108a and the first interlayer insulating film 102.

Referring to FIG. 5, the second contact hole 112 is formed by partially etching the second interlayer insulating layer 110. Subsequently, the first interlayer insulating layer 102 is partially etched to form a first contact hole 114 in communication with the second contact hole 112. Hereinafter, the second contact hole 112 and the first contact hole 114 will be collectively described as a contact hole 116. By forming the contact hole 116, the second interlayer insulating film 110 and the first interlayer insulating film 102 are converted into a second interlayer insulating film pattern 110a and a first interlayer insulating film pattern 102a. In this case, the contact hole 116 is formed to expose a portion of the single crystal silicon film pattern 108a on an inner surface thereof.

When the contact hole 116 is formed in the epitaxial layer 106 shown in FIG. 4, the process of etching the epitaxial layer 106 as well as the first interlayer insulating layer 102 should be performed. .

Referring to FIG. 6, nitrogen is ion implanted into the sidewall of the single crystal silicon film pattern 108a exposed by the contact hole 116 to form a nitrogen doped region 118 on the sidewall surface of the single crystal silicon film pattern.

It is preferable to form nitrogen ions for forming the nitrogen doped region by gradient ion implantation. In the inclined ion implantation, the ion implantation angle may be selectively changed according to the diameter of the contact hole inlet and the thickness of the second interlayer insulating layer.

The nitrogen doped region 118 may be formed by ion implanting nitrogen ions at 1 to 20 eV energy, and particularly by ion implanting nitrogen ions at about 10 eV energy. In addition, the nitrogen doped region 118 may be formed by gradient ion implantation of 0.1E ¹⁵ to 9 E ¹⁵ nitrogen ions, and in particular, by gradient ion implantation of 0.5E ¹⁵ to 5 E ¹⁵ nitrogen ions.

In the method described above, the nitrogen doped region 118 formed on the sidewall surface of the single crystal silicon film pattern 108a has a barrier of silicon (Si) included in the single crystal silicon film pattern when a sidewall metal silicide film (not shown) is subsequently formed. It is used as a blocking film which can prevent the diffusion into the metal film. Therefore, the formation thickness of the sidewall metal silicide film formed on the sidewall surface of the single crystal silicon film pattern may be adjusted.

Referring to FIG. 7, the sidewalls and bottom surfaces of the contact hole 116 are continuously formed on the sidewalls of the single crystal silicon film pattern 180a including the nitrogen doped region 118 and the top surface of the second interlayer insulating film pattern 110a. The barrier metal film 120 is formed.

The barrier metal film 120 may include, for example, titanium, tantalum, cobalt, titanium nitride, tantalum nitride, and cobalt nitride. It is preferable to use these independently, and it can mix and use two or more as needed. That is, the first barrier metal film 120 may have a single metal film structure or may have a structure in which a metal film / metal nitride film is stacked. The barrier metal film 120 of the present embodiment preferably has a structure in which a titanium film / titanium nitride film is stacked. The barrier metal film 120 preferably includes a metal film having a sufficient thickness to form a first metal silicide film having a first thickness.

In addition, the barrier metal film 120 is preferably formed by a chemical vapor deposition process. The chemical vapor deposition process may form a barrier metal film having substantially the same thickness in the contact hole. For example, the titanium film, which is the barrier metal film 130, may be formed after the TiCl ₄ gas flows into the contact hole.

On the other hand, since the process of depositing the barrier metal film proceeds at a high temperature, the silicon of the barrier metal film, the substrate and the silicon film may inevitably undergo a silicide reaction.

Although not illustrated, an etch back process may be further performed on the barrier metal film 120. The etch back process is performed to improve the profile of the inlet of the contact hole 116 which is poor due to the barrier metal film formed by the chemical vapor deposition process. Thereafter, a cleaning process for removing the etching residue remaining in the contact hole in which the barrier metal layer 120 is formed may be further performed. For example, the cleaning process may be performed using an etching solution containing hydrofluoric acid (HF).

Referring to FIG. 8, a single crystal silicon layer 100 is formed on a single crystal silicon substrate 100 exposed to the contact hole, that is, a bottom surface of the contact hole by performing a rapid heat treatment process, and the nitrogen doped region is formed. The side metal silicide film 144 is formed on the sidewall of the pattern 108a.

The lower metal silicide layer 142 is formed by silicide reaction between the silicon of the single crystal silicon substrate exposed to the contact hole and the barrier metal layer 120 in contact with the substrate when the substrate is rapidly heat treated at a temperature of about 850 or less. do. As the lower metal silicide layer 142 is formed on the bottom of the contact hole 116, the contact resistance decreases. When the barrier metal film includes a titanium film, the heat treatment temperature is preferably about 650 ° C.

The second metal silicide layer 144 may include silicon included in sidewalls of the single crystal silicon layer pattern in which the nitrogen doped region 118 is formed when the substrate is rapidly heat treated at a temperature of about 850 or less, and sidewalls of the silicon layer pattern. The barrier metal film 120 to be interviewed is formed by silicide reaction. At this time, since the nitrogen doped region blocks diffusion of silicon, a side metal silicide layer having a substantially uniform thickness or a smaller thickness is formed on the sidewall of the single crystal silicon layer pattern.

As described above, the nitrogen doped region in which the nitrogen ions are formed by the gradient ion implantation contributes to forming the first metal silicide layer 142 and the second metal silicide layer 144 to have different thicknesses. Up to 108a), defects caused by penetration of the metal silicide film can be reduced.

Referring to FIG. 9, a metal layer (not shown) is deposited to bury the contact hole 116 of the resultant metal silicide layer, and the planarization layer exposes the second interlayer insulating layer pattern 110a to expose the contact hole 116. ) A contact plug, which is a metal layer pattern 150 embedded therein, is formed. The contact plug 150 may be formed using tungsten, aluminum or copper.

As described above, according to the present invention, it is possible to uniformly form the lower metal silicide film and the instant metal silicide film by using the nitrogen doped region, thereby preventing the erosion of the single crystal silicon film pattern frequently generated when forming the contact plug of the stacked semiconductor device. Can be reduced.

In addition, since the metal silicide film pattern or the metal film pattern is eroded by the single crystal silicon film pattern, malfunction of the transistors formed in the single crystal silicon film pattern may be minimized.

As described above, although described with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified without departing from the spirit and scope of the invention described in the claims below. And can be changed.

Claims (7)

 Forming a single crystal silicon film pattern used as an upper active region between the interlayer insulating films formed on the single crystal silicon substrate and the interlayer insulating films; Sequentially etching the interlayer insulating layers to expose a surface of the single crystal silicon substrate to form contact holes exposing sidewalls of the single crystal silicon layer pattern and a portion of the single crystal silicon substrate; Forming a nitrogen doped region by ion implanting nitrogen into the sidewall surface of the single crystal silicon film pattern exposed to the contact hole; Continuously forming a barrier metal film on an upper surface of the interlayer insulating structure, sidewalls and bottom of a contact hole; And And performing a heat treatment process on the barrier metal film to form a lower silicide film on a single crystal silicon substrate exposed to a contact hole, and forming a side silicide film on sidewalls of the single crystal silicon film having the nitrogen doped region. Method of manufacturing the device. The method of claim 1, wherein the nitrogen doped region is formed by inclining ion implantation of nitrogen ions at 1 to 20 eV. The method of claim 1, wherein the nitrogen doped region is formed by gradient ion implantation of 0.1E ¹⁵ to 9 E ¹⁵ nitrogen ions. The method of claim 1, wherein the barrier metal film comprises at least one selected from the group consisting of titanium, tantalum, cobalt, titanium nitride, tantalum nitride, and cobalt nitride. The method of claim 1, wherein the barrier metal film is formed by sequentially stacking a titanium film and a titanium nitride film. The method of claim 1, further comprising: cleaning the contact hole with an etching solution containing hydrofluoric acid. The method of claim 1, wherein the forming of the interlayer insulating layers and the single crystal silicon layer pattern having the contact hole is performed. Forming a first interlayer insulating film on the single crystal silicon substrate, the first interlayer insulating film having an opening that partially exposes the surface of the substrate; Forming an epitaxial layer filling the opening by selectively performing epitaxial growth with a seed exposed on the bottom surface of the opening; Forming an amorphous silicon film on the epitaxial film and the first interlayer insulating film; Heat treating the amorphous silicon film to convert the amorphous silicon film into a single crystal silicon film; Patterning the single crystal silicon film to form a single crystal silicon film pattern; Forming a second interlayer insulating film on the single crystal silicon film pattern and the first interlayer insulating film; And And sequentially etching the first and second interlayer insulating films to expose a portion of the single crystal silicon film pattern to form contact holes.

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