KR20060122222A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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KR20060122222A
KR20060122222A KR1020050044502A KR20050044502A KR20060122222A KR 20060122222 A KR20060122222 A KR 20060122222A KR 1020050044502 A KR1020050044502 A KR 1020050044502A KR 20050044502 A KR20050044502 A KR 20050044502A KR 20060122222 A KR20060122222 A KR 20060122222A
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film
titanium
storage node
titanium nitride
nitride film
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KR1020050044502A
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KR100693786B1 (en
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곽노정
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02186—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing titanium, e.g. TiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02247—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by nitridation, e.g. nitridation of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Semiconductor Memories (AREA)

Abstract

A method for manufacturing a semiconductor device is provided to prevent the damage of titanium silicide formed at a lower portion of a lower electrode without using an additional process. A storage node contact plug(23) is formed on a substrate(21). An insulating layer(22) having a hole for opening the storage node contact plug is formed on the resultant structure. A titanium silicide layer(25) is formed on the exposed storage node contact plug. A first titanium nitride layer(27) and a titanium film are sequentially formed on the resultant structure. The titanium film is changed to a second titanium nitride layer by treating under nitrogen atmosphere. A third titanium nitride layer(29) is formed on the second titanium nitride layer. The insulating layer is selectively eliminated by using wet-chemical.

Description

반도체 소자 제조 제조 방법{METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE} Manufacture method of semiconductor device manufacturing {METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}

도 1a 및 도 1b는 종래 기술에 따른 반도체 소자 제조 방법을 도시한 단면도와 전자현미경 사진,1A and 1B are cross-sectional views and electron micrographs showing a method of manufacturing a semiconductor device according to the prior art;

도 2a 내지 도 2d는 본 발명의 일실시예에 따른 반도체 소자 제조 방법을 도시한 단면도. 2A to 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

21 : 반도체 기판 22 : 층간절연막21 semiconductor substrate 22 interlayer insulating film

23 : 스토리지노드콘택플러그 24 : 식각정지막23: storage node contact plug 24: etch stop

25 : 하부전극용 금속실리사이드 26 : SN 산화막25 metal silicide for lower electrode 26 SN oxide film

27 : 제 1 TiN 28 : Ti 27: first TiN 28: Ti

29 : 제 2 TiN29: second TiN

본 발명은 반도체 제조 기술에 관한 것으로, 특히 반도체 소자의 캐패시터 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing techniques, and more particularly, to a method of manufacturing capacitors in semiconductor devices.

최근 DRAM의 집적도가 증가함에 따라서 캐패시터의 면적이 작아지게 되어 요구되는 유전용량의 확보가 점점 어려워지고 있다. 요구되는 유전용량을 확보하기 위해서는 유전박막의 두께를 낮추거나 유전상수가 큰 물질을 적용해야 한다.Recently, as the integration of DRAM increases, the area of the capacitor becomes smaller, which makes it difficult to secure the required dielectric capacity. To secure the required dielectric capacity, it is necessary to reduce the thickness of the dielectric thin film or apply a material having a high dielectric constant.

특히, 80㎚급 이하의 DRAM에서는 누설 전류 특성을 확보하면서 유전 용량을 확보하기 위한 기술이 개발되고 있다.In particular, in the DRAM of 80 nm or less, techniques for securing the dielectric capacity while securing leakage current characteristics have been developed.

이러한 유전박막 구조에서 유전 용량을 확보하는데 있어 콘케이브(Concave) 구조로는 한계에 다다르고 있으며, 실린더(Cylinder) 구조를 적용하여 캐패시터의 면적을 확보해야 한다.In the dielectric thin film structure, the dielectric capacity is approaching the limit of the concave structure (Concave), the cylinder (Cylinder) structure should be applied to secure the area of the capacitor.

도 1a 및 도 1b는 종래 기술에 따른 반도체 소자 제조 방법을 나타낸 단면도와 전자현미경 사진이다.1A and 1B are cross-sectional views and electron micrographs showing a method of manufacturing a semiconductor device according to the prior art.

도 1a에 도시된 바와 같이, 반도체 기판(11) 상부에 층간절연막(12)을 형성한 후, 층간절연막(12)을 관통하여 반도체 기판(11)의 일부와 콘택되는 스토리지노드콘택플러그(13)을 형성한다. 이 때, 스토리지노드콘택플러그(13)는 폴리실리콘플러그이며, 스토리지노드콘택플러그(13) 형성 전에 소자분리, 워드라인 및 비트라인 등의 DRAM 구성에 필요한 공정이 진행된다.As shown in FIG. 1A, after forming the interlayer insulating film 12 on the semiconductor substrate 11, the storage node contact plug 13 penetrating the interlayer insulating film 12 and contacting a portion of the semiconductor substrate 11. To form. At this time, the storage node contact plug 13 is a polysilicon plug, and processes necessary for DRAM isolation such as device isolation, word lines, and bit lines are performed before the storage node contact plug 13 is formed.

이어서, 스토리지노드콘택플러그(13) 상부에 식각정지막(14)과 SN 산화막(15)을 적층 형성한다. 여기서 SN 산화막(15)은 실린더 구조의 스토리지노드가 형 성될 홀을 제공하기 위한 산화막이고, 식각정지막(14)은 SN 산화막(15) 식각시 하부구조물이 식각되는 것을 방지하기 위한 식각베리어 역할을 한다.Subsequently, an etch stop layer 14 and an SN oxide layer 15 are stacked on the storage node contact plug 13. Here, the SN oxide layer 15 is an oxide layer for providing a hole in which a storage node having a cylindrical structure is to be formed, and the etch stop layer 14 serves as an etch barrier to prevent the underlying structure from being etched when the SN oxide layer 15 is etched. do.

다음으로, SN 산화막(15)과 식각정지막(14)을 순차적으로 식각하여 스토리지노드콘택플러그(13) 상부를 개방시키는 스토리지노드홀(도시하지 않음)을 형성한다.Next, the SN oxide layer 15 and the etch stop layer 14 are sequentially etched to form a storage node hole (not shown) that opens the upper portion of the storage node contact plug 13.

이어서, 스토리지노드홀 아래에 노출된 스토리지노드콘택플러그(13) 표면에 오믹 콘택을 형성하기 위한 티타늄실리사이드(16)를 형성한 후, 스토리지노드홀의 내부에 실린더 구조를 갖는 SN TiN(17)을 형성한다. 이 때, SN TiN(17)은 캐패시터의 스토리지노드(Storage Node; SN)로 사용되는 TiN을 일컫는다.Subsequently, after forming titanium silicide 16 for forming ohmic contact on the surface of the storage node contact plug 13 exposed under the storage node hole, SN TiN 17 having a cylinder structure is formed in the storage node hole. do. In this case, SN TiN 17 refers to TiN used as a storage node (SN) of a capacitor.

일반적으로 캐패시터 하부 전극으로 사용되는 TiN의 케미컬 침투 내성을 강화하기 위해 여러 차례에 걸쳐 TiN을 증착하며, 각각의 증착이 끝날 때마다 NH3 또는 N2 처리를 실시하여 계면 특성을 강화한다.Generally, TiN is deposited several times in order to enhance chemical penetration resistance of TiN, which is used as a capacitor lower electrode, and NH 3 or N 2 treatment is performed at each end to enhance interfacial properties.

그러나, 이러한 처리만으로는 부족하여 TiN을 통하여 케미컬이 침투('A')하고 이에 의해 티타늄실리사이드(TiSi2)가 손실되어 콘택 저항이 증가하는 현상이 발생한다. 이러한 현상이 발생하는 원인은 TiN이 주상 구조(collumnar)를 갖고 있기 때문이며 후속 처리를 실시하더라도 주상 구조의 그레인 바운더리(Grain Boundary)가 불연속하지(discontinous) 않고 계속 연장되어 있기 때문이다. However, such treatment alone is not sufficient, and the chemical penetrates through TiN ('A'), thereby causing the loss of titanium silicide (TiSi 2 ) to increase the contact resistance. This phenomenon occurs because TiN has a columnar structure, and the grain boundary of the columnar structure is not discontinous and continues to extend even after subsequent processing.

'A' 영역을 확대한 도면에서, 티타늄실리사이드(16) 상에 SN TiN(17)이 형성되는데 TiN의 주상 구조 특성으로 인하여 케미컬이 침투하여 티타늄실리사이드(16) 에 보이드가 발생하게 된다.In the enlarged view of the 'A' region, SN TiN 17 is formed on the titanium silicide 16, and due to the columnar structural characteristics of TiN, chemical penetrates to cause voids in the titanium silicide 16.

도 1b는, 케미컬 침투로 인해 티타늄실리사이드에 보이드가 발생한 전자현미경 사진으로, 주상 구조의 TiN이 형성되고 후속 세정 공정시 케미컬이 TiN 그레인 사이로 침투하여 TiSi2의 로스를 발생시킴을 알 수 있다.FIG. 1B is an electron micrograph in which voids occur in titanium silicide due to chemical penetration, and it can be seen that TiN of columnar structure is formed and chemicals penetrate between TiN grains to cause loss of TiSi 2 during the subsequent cleaning process.

상술한 바와 같이, 케미컬 침투를 방지하기 위해 여러 차례에 걸쳐 TiN을 증착하지만, TiN은 주상 구조를 갖기 때문에 그 사이로 케미컬이 침투하여 하부 구조에 보이드를 발생시킴을 알 수 있다.As described above, TiN is deposited several times to prevent chemical penetration, but since TiN has a columnar structure, it can be seen that chemical penetrates therebetween to cause voids in the underlying structure.

본 발명은 상기한 종래 기술의 문제점을 해결하기 위해 제안된 것으로, 케미컬 침투 경로를 근본적으로 차단하여 캐패시터의 동작 특성을 개선하는데 적합한 반도체 소자의 캐패시터 제조 방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a method of manufacturing a capacitor of a semiconductor device suitable for fundamentally blocking a chemical penetration path to improve the operation characteristics of a capacitor.

상기 목적을 달성하기 위한 일 특징적인 본 발명의 반도체 소자 제조 방법은 반도체 기판 상부에 스토리지노드콘택플러그를 형성하는 단계, 상기 스토리지노드콘택플러그가 형성된 결과물의 상부에 상기 스토리지노드콘택플러그 표면을 오픈하는 홀을 갖는 절연막을 형성하는 단계, 상기 홀의 내부의 상기 스토리지노드콘택플러그 상에 티타늄 실리사이드막을 형성하는 단계, 상기 티타늄실리사이드막이 형성 된 결과물 상에 제 1 티타늄나이트라이드막을 형성하는 단계, 상기 제 1 티타늄나이트라이드막 상에 티타늄막을 형성하는 단계, 상기 티타늄막을 질소분위기에서 처리하여 제 2 티타늄나이트라이드막으로 형성하는 단계, 상기 제 2 티타늄나이트라이드막 상에 제 2 티타늄나이트라이드막을 형성하는 단계, 습식 케미컬을 이용하여 상기 절연막을 선택적으로 제거하는 단계, 상기 실린더형 스토리지노드 상에 유전막을 형성하는 단계, 및 상기 유전막 상에 플레이트 전극을 형성하는 단계를 포함한다.According to another aspect of the present invention, a method of manufacturing a semiconductor device includes: forming a storage node contact plug on an upper surface of a semiconductor substrate; Forming an insulating film having a hole, forming a titanium silicide film on the storage node contact plug in the hole, and forming a first titanium nitride film on a resultant product of the titanium silicide film, the first titanium Forming a titanium film on the nitride film, treating the titanium film in a nitrogen atmosphere to form a second titanium nitride film, forming a second titanium nitride film on the second titanium nitride film, and a wet process. The insulating film using the chemical Selectively removing, forming a dielectric film on said cylindrical storage node, and a step of forming a plate electrode on the dielectric film.

상기와 같은 발명을 적용함으로써, 주상 구조를 갖는 TiN 사이에 구조가 다른 TiN을 형성하여 습식 케미컬로부터 하부 막들을 보호할 수 있는 효과가 있다.By applying the invention as described above, there is an effect that can protect the lower films from the wet chemical by forming TiN having a different structure between the TiN having a columnar structure.

이하, 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the most preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. .

도 2a 내지 도 2d는 본 발명의 일실시예에 따른 반도체 소자 제조 방법을 도시한 단면도이다.2A through 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

도 2a에 도시된 바와 같이, 반도체 기판(21) 상부에 층간절연막(22)을 형성한 후, 층간절연막(22)을 관통하여 반도체 기판(21)의 일부와 콘택되는 스토리지노드콘택플러그(23)을 형성한다. 이 때, 스토리지노드콘택플러그(23)는 폴리실리콘플러그이며, 스토리지노드콘택플러그(23) 형성 전에 소자분리, 워드라인 및 비트라인 등의 DRAM 구성에 필요한 공정이 진행된다.As shown in FIG. 2A, after forming the interlayer dielectric layer 22 on the semiconductor substrate 21, the storage node contact plug 23 penetrates the interlayer dielectric layer 22 and contacts a portion of the semiconductor substrate 21. To form. At this time, the storage node contact plug 23 is a polysilicon plug, and processes necessary for DRAM isolation such as device isolation, word lines, and bit lines are performed before the storage node contact plug 23 is formed.

한편, 층간절연막(22)은 BSG(Boro-Silicate-Glass)막, BPSG(Boro-Phospho-Silicate-Glass)막, PSG(Phospho-Silicate-Glass)막, TEOS(Tetra-Ethyl-Ortho-Silicate)막, HDP(High Density Plasma) 산화막, 또는 APL(Advanced Planarization Layer)막 등을 이용하거나, 산화막 계열 이외에 무기 또는 유기 계열의 저유전율막을 이용한다. Meanwhile, the interlayer insulating film 22 may include a BSG (Boro-Silicate-Glass) film, a BPSG (Boro-Phospho-Silicate-Glass) film, a PSG (Phospho-Silicate-Glass) film, and a TEOS (Tetra-Ethyl-Ortho-Silicate) film. A film, an HDP (High Density Plasma) oxide film, an APL (Advanced Planarization Layer) film, or the like, or an inorganic or organic low dielectric constant film other than the oxide film is used.

이어서, 스토리지노드콘택플러그(23) 상부에 식각정지막(24)과 SN 산화막(25)을 적층 형성한다. 여기서 SN 산화막(25)은 실린더 구조의 스토리지노드가 형성될 홀을 제공하기 위한 산화막이고, 식각정지막(24)은 SN 산화막(25) 식각시 하부구조물이 식각되는 것을 방지하기 위한 식각베리어 역할을 한다.Subsequently, an etch stop layer 24 and an SN oxide layer 25 are stacked on the storage node contact plug 23. Here, the SN oxide layer 25 is an oxide layer for providing a hole in which a storage node having a cylindrical structure is to be formed, and the etch stop layer 24 serves as an etch barrier to prevent the underlying structure from being etched during the SN oxide layer 25 etching. do.

바람직하게, 식각정지막(24)은 저압화학기상증착방식(LPCVD)의 실리콘질화막(Si3N4)으로 형성하며 그 두께는 500Å∼1500Å이고, SN 산화막(25)은 BPSG, USG, PETEOS 또는 HDP 산화막으로 형성한다.Preferably, the etch stop film 24 is formed of a low pressure chemical vapor deposition (LPCVD) silicon nitride film (Si 3 N 4 ), the thickness is 500 ~ 1500Å, SN oxide film 25 is BPSG, USG, PETEOS or It is formed of an HDP oxide film.

다음으로, SN 산화막(25)과 식각정지막(24)을 순차적으로 식각하여 스토리지노드콘택플러그(23) 상부를 개방시키는 스토리지노드홀(도시하지 않음)을 형성한다.Next, the SN oxide layer 25 and the etch stop layer 24 are sequentially etched to form a storage node hole (not shown) that opens the upper portion of the storage node contact plug 23.

이어서, 스토리지노드홀 아래에 노출된 스토리지노드콘택플러그(23) 표면에 오믹콘택을 형성하기 위한 하부전극용 금속실리사이드막(26)을 형성한다. 이 때, 금속실리사이드막(26)은 티타늄실리사이드(Ti-Silicide), 탄탈륨실리사이드(Ta- Silicide), 몰리브데늄실리사이드(Mo-Silicide) 또는 니켈실리사이드(Ni-Silicide) 중에서 선택된 물질로 형성하며 예컨대, 본 발명의 일실시예에서는 티타늄실리사이드막을 사용한다.Subsequently, a metal silicide layer 26 for lower electrodes is formed on the surface of the storage node contact plug 23 exposed under the storage node hole to form an ohmic contact. In this case, the metal silicide layer 26 is formed of a material selected from titanium silicide (Ti-Silicide), tantalum silicide (Ta- Silicide), molybdenum silicide (Mo-Silicide), or nickel silicide (Ni-Silicide). In one embodiment of the present invention, a titanium silicide film is used.

한편, 하부전극용 금속실리사이드막(26)은 살리사이드(Salicide) 공정, 또는 인시튜(in-situ) 실리사이드 공정, 또는 스퍼터링 방법을 사용한다. On the other hand, the lower electrode metal silicide film 26 uses a salicide process, an in-situ silicide process, or a sputtering method.

이 때, 살리사이드 공정은 급속 열 처리(Rapid Thermal Process; 'RTP')를 사용하는데 650℃∼900℃의 범위에서 N2, Ar 또는 He 분위기에서 실시한다.At this time, the salicide process uses a rapid thermal process ('RTP'), which is carried out in an N 2 , Ar or He atmosphere in the range of 650 ° C. to 900 ° C.

이어서, 하부전극용 금속실리사이드막(26)을 포함하는 SN 산화막(25) 표면 상에 하부전극용 제 1 TiN(27)을 증착한다. 제 1 TiN(27)은 TiCl4 또는 MO 소스를 사용하여 증착한다.Subsequently, the first TiN 27 for the lower electrode is deposited on the surface of the SN oxide film 25 including the metal silicide layer 26 for the lower electrode. The first TiN 27 is deposited using a TiCl 4 or MO source.

TiCl4 소스를 사용하여 제 1 TiN(27)을 증착할 때, 50Å∼300Å 두께로 증착한다.When depositing the first TiN 27 using a TiCl 4 source, it is deposited to a thickness of 50 kPa to 300 kPa.

도 2b에 도시된 바와 같이, 제 1 TiN(27)을 증착한 후 같은 챔버 내에서 Ti(28)를 증착하며, 이는 10Å∼100Å 두께로 증착한다.As shown in FIG. 2B, after depositing the first TiN 27, Ti 28 is deposited in the same chamber, which is deposited to a thickness of 10 μs to 100 μs.

이 때, Ti(28)는 제 1 TiN(27) 및 제 2 TiN(도 2d의 29)과 다른 구조를 갖으며, 이는 후속 습식딥아웃 공정시 케미컬의 하부 구조물로의 침투를 방지하기 위한 일종의 블로킹막 (Blocking layer)역할을 한다. At this time, the Ti 28 has a different structure from the first TiN 27 and the second TiN (29 in FIG. 2D), which is a kind of material for preventing the chemical from penetrating into the lower structure during the subsequent wet dipout process. It acts as a blocking layer.

도 2c에 도시된 바와 같이, Ti(28)를 증착한 후 Ti(28)를 TiN(28a)화 하기 위해 NH3 또는 N2 처리를 실시한다. 이렇게 되면 주상 구조를 갖지 않는 TiN을 얻을 수 있다. 이 때, NH3 또는 N2 처리는 플라즈마 처리 방식을 포함하며, 이러한 질화 처리를 통하여 TiN 표면을 질소 부화(N-rich) 처리하여 줌으로써 후속 TiN과의 비연속적인 주상 구조를 만들어준다.As shown in FIG. 2C, after depositing Ti 28, NH 3 or N 2 treatment is performed to TiN 28 Ti. In this case, TiN having no columnar structure can be obtained. At this time, the NH 3 or N 2 treatment includes a plasma treatment method, and the NiN-rich treatment of the TiN surface through such nitriding treatment creates a discontinuous columnar structure with subsequent TiN.

도 2d에 도시된 바와 같이, Ti(28)가 TiN화(28a)된 결과물의 전면에 제 2 TiN(29)를 증착한다. As shown in FIG. 2D, a second TiN 29 is deposited on the entire surface of the Ti 28 converted TiN 28a.

이어서, 도면에 도시하지는 않았지만 스토리지노드홀의 내부에만 실린더형 스토리지노드를 형성하는 스토리지노드 분리(Storage Node Isolation) 공정을 진행한다. 이 때, 스토리지노드는 제 1 TiN(27), TiN화 된 Ti(28a) 및 제 2 TiN(29)의 삼중층 구조이다.Next, although not shown in the figure, a storage node isolation process of forming a cylindrical storage node only in the storage node hole is performed. At this time, the storage node has a triple layer structure of the first TiN 27, the TiNized Ti 28a, and the second TiN 29.

스토리지노드 분리 공정은 스토리지노드홀을 제외한 SN 산화막(25)을 제외한 SN 산화막(25) 표면 상부에 형성된 제 1 TiN(27), TiN화 된 Ti(28a) 및 제 2 TiN(29)을 화학적 기계적 연마(CMP) 또는 에치백으로 제거하여 실린더형 스토리지노드를 형성하는 것이다. 여기서, 화학적 기계적 연마 또는 에치백 공정시에 연마재나 식각된 입자 등의 불순물이 실린더형 스토리지노드 내부에 부착되는 우려가 있으므로, 스텝 커버리지 특성이 좋은 포토레지스트로 스토리지노드홀의 내부를 모두 채운 후에, SN 산화막(25)이 노출될 때까지 연마 또는 에치백을 수행하고, 포토레지스트를 애싱(Ashing)하여 제거하는 것이 좋다.The storage node separation process chemically modifies the first TiN 27, the TiNized Ti 28a and the second TiN 29 formed on the surface of the SN oxide 25 except for the SN oxide 25 except for the storage node. It is removed by polishing (CMP) or etch back to form a cylindrical storage node. Here, since chemical impurities such as abrasives or etched particles may adhere to the inside of the cylindrical storage node during chemical mechanical polishing or etch back process, the SN may be filled with a photoresist having good step coverage characteristics. It is preferable to perform polishing or etch back until the oxide film 25 is exposed, and ashing and removing the photoresist.

계속하여, SN 산화막(25)을 선택적으로 습식딥아웃하여 스토리지노드의 내벽 및 외벽을 모두 드러낸다. 습식딥아웃 공정은 주로 불산(HF) 용액을 이용하여 진행 하는데, 산화막으로 형성한 SN 산화막(25)이 불산 용액에 의해 식각된다.Subsequently, the SN oxide film 25 is selectively wetted out to expose both the inner and outer walls of the storage node. The wet dip-out process is mainly performed using a hydrofluoric acid (HF) solution, and the SN oxide film 25 formed of the oxide film is etched by the hydrofluoric acid solution.

위와 같은 습식 케미컬 적용시에 불산 용액이 스토리지노드의 바닥 부분을 관통하여 하부 층간절연막(22)으로 침투할 수 있으나, 본 발명의 스토리지노드가 동종 구조를 갖는 TiN(27, 29) 사이에 Ti가 질화된 TiN(28a)을 삽입한 구조를 갖기 때문에 불산 용액이 하부 구조로 침투할 수 없다.In the above wet chemical application, the hydrofluoric acid solution may penetrate through the bottom portion of the storage node and penetrate into the lower interlayer insulating layer 22, but the Ti between the TiNs 27 and 29 having the same structure as the storage node of the present invention is used. Since the nitrided TiN 28a is inserted, the hydrofluoric acid solution cannot penetrate into the underlying structure.

이어서, 제 2 TiN(29) 상에 유전막과 플레이트 전극을 순차적으로 형성한다. 이 때, 유전막은 HfO2 단독 또는 Al2O3와 HfO2의 적층 구조로 형성하고, 플레이트 전극은 TiN, 텅스텐(W) 또는 루테늄(Ru) 중에서 선택하여 형성한다.Subsequently, a dielectric film and a plate electrode are sequentially formed on the second TiN 29. At this time, the dielectric film is formed of HfO 2 alone or a laminated structure of Al 2 O 3 and HfO 2 , and the plate electrode is formed by selecting from TiN, tungsten (W) or ruthenium (Ru).

상술한 바와 같이, 주상 구조를 갖는 TiN 사이에 주상 구조를 갖지 않는 TiN이 얇게 존재하므로 후속 공정에서 케미컬이 침투하는 것을 방지할 수 있게 되어 케미컬 침투로 인한 소자의 디펙트(보이드, 핀홀 또는 크랙)를 방지할 수 있다.As described above, since TiN having no columnar structure exists thinly between TiNs having columnar structure, it is possible to prevent the chemical from penetrating in a subsequent process, so that the defect of the device due to chemical penetration (void, pinhole or crack) Can be prevented.

본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

상술한 본 발명은 기존 캐패시터 제조 방식과 대비해서 공정의 추가 없이 후 속 공정에 의해 하부 전극인 TiN막 하부에 있는 티타늄실리사이드(TiSi2)가 손상되는 것을 방지할 수 있다. The present invention described above can prevent the titanium silicide (TiSi 2 ) in the lower portion of the TiN film, which is the lower electrode, by the subsequent process without the addition of a process compared to the conventional capacitor manufacturing method.

따라서, 스토리지노드콘택 저항이 증가하면서 발생하는 디바이스 페일(Device fail)을 방지할 수 있으므로 수율 향상에 큰 효과를 얻을 수 있다.Therefore, a device fail caused by an increase in the storage node contact resistance can be prevented, and thus a large effect can be obtained in improving yield.

Claims (8)

반도체 기판 상부에 스토리지노드콘택플러그를 형성하는 단계;Forming a storage node contact plug on the semiconductor substrate; 상기 스토리지노드콘택플러그가 형성된 결과물의 상부에 상기 스토리지노드콘택플러그 표면을 오픈하는 홀을 갖는 절연막을 형성하는 단계;Forming an insulating layer having a hole for opening a surface of the storage node contact plug on an upper portion of the resultant on which the storage node contact plug is formed; 상기 홀의 내부의 상기 스토리지노드콘택플러그 상에 티타늄 실리사이드막을 형성하는 단계;Forming a titanium silicide layer on the storage node contact plug in the hole; 상기 티타늄실리사이드막이 형성된 결과물 상에 제 1 티타늄나이트라이드막을 형성하는 단계;Forming a first titanium nitride film on the resultant product on which the titanium silicide film is formed; 상기 제 1 티타늄나이트라이드막 상에 티타늄막을 형성하는 단계;Forming a titanium film on the first titanium nitride film; 상기 티타늄막을 질소분위기에서 처리하여 제 2 티타늄나이트라이드막으로 형성하는 단계;Treating the titanium film in a nitrogen atmosphere to form a second titanium nitride film; 상기 제 2 티타늄나이트라이드막 상에 제 3 티타늄나이트라이드막을 형성하는 단계;Forming a third titanium nitride film on the second titanium nitride film; 습식 케미컬을 이용하여 상기 절연막을 선택적으로 제거하는 단계;Selectively removing the insulating layer using a wet chemical; 상기 실린더형 스토리지노드 상에 유전막을 형성하는 단계; 및Forming a dielectric film on the cylindrical storage node; And 상기 유전막 상에 플레이트 전극을 형성하는 단계Forming a plate electrode on the dielectric layer 를 포함하는 반도체 소자 제조 방법.Semiconductor device manufacturing method comprising a. 제 1 항에 있어서,The method of claim 1, 상기 제 1 티타늄나이트라이드막은 50Å∼300Å의 두께로 형성하는 반도체 소자 제조 방법.And the first titanium nitride film is formed to a thickness of 50 kPa to 300 kPa. 제 1 항 또는 제 2 항에 있어서,The method according to claim 1 or 2, 상기 제 1 티타늄나이트라이드막은 NH3 또는 N2 처리를 실시하는 단계를 더 포함하는 반도체 소자 제조 방법.The first titanium nitride film further comprises the step of performing NH 3 or N 2 treatment. 제 1 항에 있어서,The method of claim 1, 상기 질소분위기는 상기 티타늄막을 포함하는 전면에 NH3 또는 N2 처리를 실시하여 티타늄나이트라이드화하는 반도체 소자 제조 방법.The nitrogen atmosphere is a semiconductor device manufacturing method of performing titanium nitride by NH 3 or N 2 treatment on the entire surface including the titanium film. 제 1 항에 있어서,The method of claim 1, 상기 제 2 티타늄나이트라이드막은 10Å∼100Å의 두께로 형성하는 반도체 소자 제조 방법.The second titanium nitride film is a semiconductor device manufacturing method to form a thickness of 10 ~ 100Å. 제 1 항에 있어서,The method of claim 1, 상기 티타늄막은 상기 제 1 티타늄나이트라이드막을 형성한 챔버 내에서 동일하게 형성하는 반도체 소자 제조 방법.And the titanium film is formed in the same chamber in which the first titanium nitride film is formed. 제 1 항에 있어서,The method of claim 1, 상기 제 1 티타늄나이트라이드막 및 상기 제 3 티타늄나이트라이드막은 TiCl4 또는 MO 소스를 사용하여 형성하는 반도체 소자 제조 방법.The first titanium nitride film and the third titanium nitride film is formed using a TiCl 4 or MO source. 제 1 항에 있어서,The method of claim 1, 상기 티타늄 실리사이드막은 살리사이드 공정, 인시튜 실리사이드 공정 또는 스퍼터링을 사용하여 형성하는 반도체 소자 제조 방법.The titanium silicide layer is formed using a salicide process, an in-situ silicide process, or sputtering.
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US8877583B2 (en) 2011-12-29 2014-11-04 Samsung Electronics Co., Ltd. Method of manufacturing a semiconductor device
WO2024147999A1 (en) * 2023-01-05 2024-07-11 Applied Materials, Inc. Contact resistance reduction by integration of molybdenum with titanium

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US8877583B2 (en) 2011-12-29 2014-11-04 Samsung Electronics Co., Ltd. Method of manufacturing a semiconductor device
WO2024147999A1 (en) * 2023-01-05 2024-07-11 Applied Materials, Inc. Contact resistance reduction by integration of molybdenum with titanium

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