KR20060116281A - A resonator structure of sigma delta analog-digital converter - Google Patents

A resonator structure of sigma delta analog-digital converter Download PDF

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KR20060116281A
KR20060116281A KR1020050038298A KR20050038298A KR20060116281A KR 20060116281 A KR20060116281 A KR 20060116281A KR 1020050038298 A KR1020050038298 A KR 1020050038298A KR 20050038298 A KR20050038298 A KR 20050038298A KR 20060116281 A KR20060116281 A KR 20060116281A
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integrator
digital converter
resonator structure
input
sigma delta
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KR1020050038298A
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KR100850420B1 (en
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강영진
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(주)다빛다인
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/458—Analogue/digital converters using delta-sigma modulation as an intermediate step
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators

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  • Compression, Expansion, Code Conversion, And Decoders (AREA)

Abstract

A resonator structure of a sigma delta analog-digital converter is provided to improve a signal to noise ratio by reducing an input constant number half and removing noise through feedback. In a resonator structure of a sigma delta analog-digital converter, an output of a first integrator(21) in a resonator structured integrator consisting two integrators is inputted to not a second integrator(22) but a third integrator(81).

Description

시그마델타 아날로그-디지털 변환기의 공진기 구조{A RESONATOR STRUCTURE OF SIGMA DELTA ANALOG-DIGITAL CONVERTER}Resonator structure of sigma delta analog-to-digital converter {A RESONATOR STRUCTURE OF SIGMA DELTA ANALOG-DIGITAL CONVERTER}

도 1은 기존의 공진기 구조의 구성도.1 is a block diagram of a conventional resonator structure.

도 2는 본 발명의 제안된 구조인 구성도.2 is a schematic view of the proposed structure of the present invention.

도 3는 본 발명의 실시예3 is an embodiment of the present invention

본 발명은 디지털오디오, 엠피3(MP3), 통신기기, 디지털앰프, 데이터변환기 등에 사용되는 아날로그-디지털 변환(Analog to digital converter) 에 필요한 기술로서 아날로그 신호를 디지털신호로 변환 시 아날로그신호를 샘플링(Sampling)하여 잘게 자르는 퀀타이징(Quantization)을 포함하는 OP-Amp 의 핵심기술로서 지금까지는 별개의 소자를 각각 큰 기판에 제작하여 만들어 왔다. 기존의 공진기 구조는 입력단이 여러개가 들어오므로 인해 잡음원천이 많아 지고 하드웨어를 많이 필요로 하며 잡음 출력이 바로 다음 단 입력으로 연속해서 연결 되는 직렬 구조로 되어 있어 신호대 잡음비가 떨어진다.The present invention is a technology required for analog-to-digital converters used in digital audio, MP3, communication devices, digital amplifiers, data converters, and the like. It is a core technology of OP-Amp that includes quantization by slicing and slicing. So far, separate devices have been manufactured on large substrates. Conventional resonator structure has many input stages, which results in more noise sources, requires more hardware, and noise-to-noise series.

본 발명은 첫번째 출력단이 다음단인 두번째 입력으로 연결되는 것이 아니라 첫 번째 출력단이 상수 입력단과 합해 져서 세 번째 입력단으로 연결 되므로 인해서 신호대 잡음비가 좋아 지며 상수 입력단이 2개단 만 들어오므로 하드웨어가 절약 될뿐만 아니라 잡음원천이 줄어든다. 본 발명은 중간 주파수를 통과시키는 밴드패스(Band pass) 필터의 역할을 하며 이 밴드패스의 구조를 위해 공진기 구조로 하고 있으며 또한 밴드패스의 위치를 프로그램을 할수 있는 프로그래밍이 가능하다.In the present invention, since the first output terminal is not connected to the second input, which is the next stage, the first output terminal is combined with the constant input terminal and connected to the third input terminal, so that the signal-to-noise ratio is improved, and the constant input terminal comes in only two stages, thereby saving hardware. In addition, the noise source is reduced. The present invention acts as a band pass filter for passing an intermediate frequency, has a resonator structure for the structure of the band pass, and can be programmed to program the position of the band pass.

본 발명은 보다 개선되고 진일보한 시그마델타 아날로그-디지털 변환기 구조를 목적으로 한다. 도 2 는 이러한 개선된 구성도를 나타낸다. 도 2에서와 같이 입력 A0(30) 는 덧셈기(70) 에 더해지며 B0(30) 는 입력과 빼어진다. 첫 번째 적분기(21) 과 두 번째 적분기(22)가 이루어져 첫 번째 공진기(20)를 구성한다. 또한 세 번째 공진기(81) 와 네 번째 공진기(82) 가 이루어져 두 번째 공진기(80)를 구성한다. 결론적으로 4개의 적분기로 이루어져 있으므로 4차인 시그마델타 아날로그-디지탈 변환기를 구성한다. 기존의 공진기 구조와는 달리 3번째 적분기(81) 입력으로 두 번째 적분기(22) 의 출력이 들어오는 것이 아니고 첫 번째(21) 적분기 출력이 가산기에 가해진 다음 들어온다. 이것 때문에 신호대 잡음비가 증가 한다. 이것은 잡음이 실린 두 번째 적분기(22) 의 출력이 다음단인 세 번째(81) 적분기에 가해지지 않고 잡음이 피디백(Feedback) 되어 가산기(70) 에 도착하여 삭제된다.  The present invention aims at a more advanced and advanced sigma delta analog-to-digital converter structure. 2 shows such an improved schematic. As in FIG. 2, input A0 30 is added to adder 70 and B0 30 is subtracted from the input. The first integrator 21 and the second integrator 22 constitute the first resonator 20. In addition, the third resonator 81 and the fourth resonator 82 are configured to constitute the second resonator 80. In conclusion, four integrators are used to construct the fourth-order sigma delta analogue-to-digital converter. Unlike the conventional resonator structure, the output of the second integrator 22 is not input to the third integrator 81, but the first (21) integrator output is applied to the adder. This increases the signal-to-noise ratio. This is not the output of the second integrator 22, which is noisy, is applied to the third 81 integrator, which is the next stage, and the noise is fed back to the adder 70 and deleted.

입력 상수 A1(30) 와 B1(30,) A0(30) 와 B0(30) 는 동일한 효과를 가진다. 세 번째(81) 출력이 아날로그-디지털 변환기(50) 로 가해 진다. 이 변환기는 출력으로 진폭이 다른 구현파 신호를 출력으로 내보낸다. 향후에 이 구형파 신호는 매시간 주파수가 다르므로 데시메시션(Decimation) 필터로 원래의 아날로그 신호를 복조 한다. 동시에 디지털-아날로그 변환기(40)는 아날로그 신호로 변환하여 이신호를 가산기(70) 에 빼어진다.The input constants A1 (30) and B1 (30,) A0 (30) and B0 (30) have the same effect. A third 81 output is applied to the analog to digital converter 50. This transducer outputs an embodied wave signal of different amplitude to the output. In the future, the square wave signal will be different every hour, demodulating the original analog signal with a decimation filter. At the same time, the digital-to-analog converter 40 converts it into an analog signal and subtracts this signal into the adder 70.

도 3은 실제 회로의 실시예를 나타낸다. Phi1 과 Phi2 는 비중첩 (Non-overlapping) 클럭킹 신호를 나타낸다. Phi1d 는 Phi1 이 조금 지연된 신호를 나타내며 Phi2d 는 Phi2 가 조금 지연된 것을 나타낸다. 도 3의 Ci0(20) 과 Ci1(20) 과 Ca01(10) 의 블록은 프로그래밍 구조에 필요한 요소를 나타낸다. 실제로 밴드패스의 위치를 프로그램 할때 이 블록들(10,20) 이 사용된다.3 shows an embodiment of an actual circuit. Phi1 and Phi2 represent non-overlapping clocking signals. Phi1d indicates that Phi1 is slightly delayed and Phi2d indicates that Phi2 is slightly delayed. Blocks of Ci0 (20), Ci1 (20), and Ca01 (10) in Fig. 3 represent elements necessary for the programming structure. In practice, these blocks 10 and 20 are used when programming the position of the bandpass.

이상 상술한 바와 같이 적분기의 출력위치를 변경 함으로써 잡음을 피드백 (Feedback) 하여 상쇄 시켰으며 입력 되어 들어오는 입력 상수를 기존 기술의 절반으로 감소 시켜 신호대 잡음비를 개선 하였음.As described above, the noise was fed back by changing the output position of the integrator, and the signal-to-noise ratio was improved by reducing the incoming input constant to half of the existing technology.

Claims (4)

아날로그-디지털 변환기에 사용되는 장치에 있어서,In the device used in the analog-to-digital converter, 적분기 두개로 이루어진 공진기 구조의 적분기가 첫 번째 적분기 출력이 두번째 적분기 입력이 아닌 세 번째 적분기 입력으로 가해지는 장치.Integrator with a two-integrator resonator structure where the first integrator output is applied to the third integrator input rather than the second integrator input. 제 1항에 있어서 공진기 구조가 첫 번째 적분기와 그다음단의 적분기 사이에 가산기가 없이 두개의 적분기가 직접 직렬 연결 되어 두 번째 적분기 출력은 첫 번째 적분기 입력 가산기로 피드백 되는 장치.2. The apparatus of claim 1, wherein the resonator structure is directly connected in series without two adders between the first integrator and the next integrator so that the second integrator output is fed back to the first integrator input adder. 제 2항 또는 제 3항에 있어서, 가산기로 들어오는 입력 신호가 첫 번째와 세 번째 적분기 입력에만 들어오는 장치 구조. 4. The device structure of claim 2 or 3, wherein the input signal to the adder enters only the first and third integrator inputs. 제 1항에 있어서 여러개의 밴드패스 위치를 프로그램밍이 가능하도록 사용하기 위해 적분기의 입력과 출력 사이에 추가된 커패시터 어레이(array) 장치.The capacitor array device of claim 1 added between the input and output of the integrator to enable programmable use of multiple bandpass positions.
KR1020050038298A 2005-05-09 2005-05-09 A resonator structure of sigma delta analog-digital converter KR100850420B1 (en)

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US5181032A (en) * 1991-09-09 1993-01-19 General Electric Company High-order, plural-bit-quantization sigma-delta modulators using single-bit digital-to-analog conversion feedback
US5392042A (en) * 1993-08-05 1995-02-21 Martin Marietta Corporation Sigma-delta analog-to-digital converter with filtration having controlled pole-zero locations, and apparatus therefor
US5673044A (en) * 1995-08-24 1997-09-30 Lockheed Martin Corporation Cascaded recursive transversal filter for sigma-delta modulators
US5982315A (en) 1997-09-12 1999-11-09 Qualcomm Incorporated Multi-loop Σ Δ analog to digital converter
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