KR20060113048A - The substrate for lcd and method for fabricating of the same - Google Patents

Abstract

An array substrate for an LCD, and a manufacturing method thereof are provided to allow a defect to be solved even after a crystal panel is completed by forming a repair line of the same material as a pixel electrode on a data line near to an intersection with a gate line. A gate line(102) and a data line(118) intersect each other on an insulating substrate(100) to define a pixel region. A first repair line(106) is placed under the data line, and is independently configured so as not to contact the gate line. A thin film transistor is constructed as an intersection of the gate line and the data line. A transparent pixel electrode(124) contacts the thin film transistor, and is placed in the pixel region. A second repair line(126) is placed on the data line near to the intersection with the gate line.

Description

Array substrate for liquid crystal display autonomous and its manufacturing method {The substrate for LCD and method for fabricating of the same}

1 is a view schematically showing a liquid crystal display panel;

2 is an enlarged plan view of a single pixel of a conventional array substrate for a liquid crystal display device including a repair wiring;

3 is a diagram for explaining a process of repairing the repaired wiring using the repair wiring when the data wiring is disconnected.

4 is an enlarged plan view of a single pixel of an array substrate for a liquid crystal display device according to the present invention including first and second repair wirings;

FIG. 5 is a diagram for describing a process of repairing a data line by using a second repair line when the data line is disconnected near the gate line.

6A to 10A and 6B to 10B are cross-sectional views illustrating a process sequence of the present invention, taken along the line VI-VI, VIII-VIII of FIG. 4.

<Brief description of the main parts of the drawing>

100: substrate 102: gate wiring

104: gate electrode 106: first repair wiring

110: active layer 112: ohmic contact layer

114: source electrode 116: drain electrode

118 data wiring 124 pixel electrode

126: second repair wiring

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an array substrate for a liquid crystal display device (LCD), and more particularly, to an array substrate for a liquid crystal display device including a repair wiring and a manufacturing method thereof.

In general, the driving principle of the liquid crystal display device uses the optical anisotropy and polarization of the liquid crystal.

Since the liquid crystal is thin and long in structure, the liquid crystal has directivity in the arrangement of molecules, and the direction of the molecular arrangement can be controlled by artificially applying an electric field to the liquid crystal.

Accordingly, if the molecular arrangement direction of the liquid crystal is arbitrarily adjusted, the molecular arrangement of the liquid crystal is changed, and light is refracted in the molecular arrangement direction of the liquid crystal by optical anisotropy to express an image.

The liquid crystal display includes a color filter substrate (upper substrate) on which a common electrode is formed, an array substrate (lower substrate) on which a pixel electrode is formed, and a liquid crystal filled between upper and lower substrates. The liquid crystal is driven by an electric field applied up and down by the pixel electrode, so that the characteristics such as transmittance and aperture ratio are excellent.

Currently, an active matrix liquid crystal display (AM-LCD: Active Matrix LCD) in which a thin film transistor and pixel electrodes connected to the thin film transistor are arranged in a matrix manner is attracting the most attention because of its excellent resolution and video performance.

Hereinafter, a configuration of a general liquid crystal display device will be described with reference to FIG. 1.

1 is a view schematically showing a liquid crystal display device.

As shown, the liquid crystal panel 51 is composed of a first substrate 5 and a second substrate 10 spaced apart from each other with the liquid crystal layer 11 therebetween, facing the second substrate 10. One surface of the first substrate 5 is composed of a color filter 8 including a black matrix 6 and a sub-color filter (red, green, blue) 7 and a transparent common electrode 9 on the color filter. do.

A plurality of pixel regions P are defined in the second substrate 10 facing the first substrate 5, and the gate wiring 14 extending through one side of the pixel region P, and the gate wirings. The data line 26 extending beyond the other side of the pixel region P where the 14 passes is not parallel.

Due to this configuration, the pixel region P becomes an area defined by the gate wiring 14 and the data wiring 26 intersecting, and the thin film transistor T is formed at the intersection of the two wirings.

The pixel region P includes a transparent pixel electrode 32 in contact with the thin film transistor T, which is transparent conductive material having excellent light transmittance, such as indium-tin-oxide (ITO). Formed of metal.

In the above-described configuration, the thin film transistor T may include a gate electrode 30 connected to the gate line 14, a semiconductor layer 32 on the gate electrode 30, and a portion of the semiconductor layer 32. And a source electrode 34 disposed above and in contact with the data line 26, and a drain electrode 36 positioned apart from the source electrode 34 and in contact with the pixel electrode 32.

The array substrate for a liquid crystal display device configured as described above is manufactured through a process of about 5 to 6 masks and briefly introduced as follows.

The following process is described using the 5 mask process as an example, and lists only the mask process.

First mask process: a gate electrode of a thin film transistor and a gate wiring forming process connected thereto.

Second mask process: an active layer and an ohmic contact layer forming process positioned over an insulating layer on the gate electrode.

A third mask process: a data line intersecting the gate line and the insulating layer therebetween, a source electrode connected to the data line and extending over the ohmic contact layer, and a drain electrode spaced apart from the data line.

4th mask process: The process of forming a contact film which forms a protective film in the whole surface of a board | substrate and exposes the said drain electrode.

Fifth mask process: forming a pixel electrode contacting through the contact hole;

An array substrate for a liquid crystal display device can be produced by the above five mask processes.

As such, since the array substrate is manufactured through a plurality of sequential processes, process problems may occur in each process. In particular, disconnection of the wiring is one of frequent process defects.

 In particular, the failure of disconnecting the data wiring is more serious than the failure of disconnecting the gate wiring.

This is because a large number of processes have already been completed before the data line is formed, which is a problem in that process cost and time are wasted, thereby lowering the process yield.

Accordingly, in order to solve such a problem, conventionally, a repair wiring is formed under the data wiring to propose a structure that can be repaired when a defect occurs in disconnecting the data wiring.

2 is an enlarged plan view of a single pixel of an array substrate for a liquid crystal display device including a repair wiring according to the related art.

As shown in the drawing, a gate wiring 62 extending in one direction on the substrate 60 and a data wiring 70 defining the pixel region P by crossing the gate wiring 62 are formed.

At the intersection of the gate line 62 and the data line 70, the gate electrode 64 connected to the gate line 62, and an active layer 68a and an ohmic contact layer on the gate electrode 64. 68b, a thin film including a source electrode 72 in contact with the ohmic contact layer 68b and in contact with the data line 70, and a drain electrode 74 spaced apart from the source electrode 72. The transistor T is configured.

In this case, in order to configure an exposed channel between the source and drain electrodes 72 and 74 in a “U” shape, the source electrode 72 is formed in a “U” shape, and the drain electrode 74 is formed in the It is configured in the shape of a bar spaced apart from and parallel to the inside of the source electrode (72).

In the pixel region P, a pixel electrode 78 in contact with the drain electrode 74 is formed.

In this case, the extension part D is formed in the pixel area P in the gate line 62, and the pixel electrode 78 is extended with an insulating film (not shown) disposed on the extension part D. In this configuration, the storage capacitor Cst can be formed.

The characteristic feature of the above-described configuration is that the repair wiring 66 is further configured under the data wiring 70.

The repair wiring 66 is to replace the upper data wiring 70 when it is disconnected.

3 is an enlarged view of A of FIG. 2 and illustrates a process of repairing a disconnected data line.

As shown in the drawing, when the data line 70 is disconnected, the point C1 and C2 are held above and below the disconnected part B of the data line 70. The process of welding the data wiring 70 and the repair wiring 66 below is performed.

In this way, the repair wiring 66 serves to transmit a signal in the portion B in which the data wiring 70 is broken.

However, when the repair wiring 66 is configured, the same mask is formed on the same layer as the gate electrode and the gate wiring 64 and 62 of FIG.

Therefore, the portion through which the gate wiring (62 in FIG. 2) passes cannot form the repair wiring 66.

In this case, when the data line 70 is disconnected at the intersection of two wires in which the repair wire 66 is not located, as shown in part B of FIG. 2, there is no method for repairing the data wire 70.

If such defects are found after completing the liquid crystal panel, repair is impossible and the liquid crystal panel must be discarded, and more than 100 defective products are actually discarded every month.

Therefore, there is a problem in that cost increase and production yield decrease in process.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and in the event of disconnection of a data line constituting one side of a pixel region of the array substrate, repair is possible regardless of the disconnection position, so that defects (defects and defects) do not occur. It is an object of the present invention to manufacture a liquid crystal display device.

An array substrate for a liquid crystal display device according to the present invention for achieving the above object is a substrate; Gate wiring and data wiring intersecting each other on the insulating substrate to define a pixel region; A first repair wiring positioned below the data wiring and independently configured to be in contact with the gate wiring; A thin film transistor configured at an intersection point of the gate line and the data line; A transparent pixel electrode in the pixel area in contact with the thin film transistor; And a second repair wiring located above the data wiring in the vicinity of the gate wiring.

The thin film transistor may include a gate electrode connected to the gate line, an active layer and an ohmic contact layer on the gate electrode, a source electrode spaced apart from the ohmic contact layer and in contact with the data line, and a drain electrode in contact with the pixel electrode. Include.

The first repair wiring is made of the same material as the gate wiring, and the second repair wiring is made of the same material as the pixel electrode.

According to an aspect of the present invention, there is provided a method of manufacturing an array substrate for a liquid crystal display device, the method comprising: defining a plurality of pixel areas on a substrate; Forming a gate wiring formed on one side of the pixel region on the substrate and a first repair wiring for each region between the pixel regions so as not to contact the gate wiring; Forming a data wiring crossing the gate wiring and configured to extend over the first repair wiring; Forming a thin film transistor at an intersection point of the gate line and the data line; Forming a second repair wiring on the transparent pixel electrode in contact with the thin film transistor and positioned in the pixel region, and a second repair wiring on an upper portion of the data wiring which intersects the gate wiring and is not located below the first repair wiring. .

The thin film transistor may include a gate electrode connected to the gate line, an active layer and an ohmic contact layer on the gate electrode, a source electrode spaced apart from the ohmic contact layer and in contact with the data line, and a drain electrode in contact with the pixel electrode. Include.

The first repair wiring is formed of the same material as the gate wiring, and the second repair wiring is formed of the same material as the pixel electrode.

The pixel electrode and the second repair line are formed of one selected from a group of transparent conductive metals including indium tin oxide (ITO) and indium zinc oxide (IZO).

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

Example

4 is an enlarged plan view of one pixel of an array substrate for a liquid crystal display according to the present invention including a repair wiring.

As shown in the drawing, the gate wiring 102 extending in one direction on the substrate 100 and the data wiring 118 defining the pixel region P by crossing the gate wiring 102 are formed.

At the intersection of the gate wiring 102 and the data wiring 118, the gate electrode 104 connected to the gate wiring 102, the active layer 110 and the ohmic contact layer 112 on the gate electrode 104 are disposed. And a source electrode 116 disposed on the ohmic contact layer 112 and in contact with the data line 118, and a drain electrode 116 exposing the lower active layer 110 spaced apart from the predetermined distance. The transistor T is constituted.

At this time, the source electrode 114 is configured in a "U" shape and the drain electrode 116 is configured in a rod shape so as to be located in parallel with the inside of the source electrode 114.

In this way, the active channel exposed between the source and drain electrodes 114 and 116 may be formed in a “U” shape.

In this case, since the length of the channel through which the carrier moves can be shortened and the width of the channel can be widened, the on current increases.

The pixel region P includes a pixel electrode 124 made of a transparent material in contact with the drain electrode 116.

In this case, the extension part D is formed in the pixel area P in the gate line 102, and the pixel electrode 124 is extended with an insulating film (not shown) interposed over the extension part D. In this configuration, the storage capacitor Cst can be formed.

In the above-described configuration, it is characteristic that the first repair wiring 106 is made of the same material as the gate wiring 102 under the data wiring 120 corresponding to the pixel region P, and the The second repair line 126 is formed on the data line 118 where the gate line 102 intersects with the same material as that of the pixel electrode 124.

This configuration has a shape in which the second repair wiring 126 is interposed between the first repair wiring 106 positioned up and down about the upper and lower pixel areas, respectively.

Due to the above-described second repair wiring 126, it is possible to repair the data wire 118 disconnected near the intersection with the gate wiring 102, that is, the area which has not been repaired by the first repair wiring 106 alone.

5 is a view for explaining a process of repairing using the second repair wiring 126 when the data wiring 118 is disconnected in the vicinity of the gate wiring 102.

As shown in FIG. 4, the data wiring 118 is disconnected by forming the second repair wiring 126 on the data wiring 118 in the region where the first repair wiring 106 is not formed. In this case, the data line 118 and the second repair wiring 126 are connected to each other by holding the points C1 and C2 at the top and the bottom of the disconnected portion F and irradiating a laser. Connect.

In this case, since the data signal flows through the second repair wiring 126 in the disconnected portion, a defect in which the pixel is not driven because the signal is broken does not occur.

Hereinafter, a manufacturing process of an array substrate for a liquid crystal display device according to the present invention having the planar structure as described above with reference to the process drawings.

6A to 10A and 6B to 10B are cross-sectional views taken along the line VI-VI, VIII-VIII of FIG. 4 and shown in the process sequence of the present invention.

6A and 6B are balls forming the gate wiring 102, the gate electrode 104, and the first repair wiring 106. The substrate defining the pixel region P including the switching region S, as illustrated, is illustrated. A single metal such as aluminum (Al), aluminum alloy (AlNd), tungsten (W), chromium (Cr), molybdenum (Mo) or aluminum (Al) / chromium (Cr) (or molybdenum (Mo)) The gate wiring 102 having a double metal layer structure and extending in the horizontal direction, and the gate electrode 104 connected to the gate wiring 102 and positioned in the switching region S are formed.

At the same time, the rod-shaped first repair wiring 106 is formed in the area between the pixel areas P neighboring left and right.

The first repair wiring 106 is independently configured for each pixel region P adjacent to the left and right at a length that does not contact the gate wiring 102.

Next, a gate insulating film 108 is formed on the entire surface of the substrate 100 on which the gate wiring 102, the gate electrode 104, and the first repair wiring 106 are formed.

The gate insulating layer 108 may be formed of an inorganic insulating material including silicon nitride (SiN _x ) and silicon oxide (SiO ₂ ), or in some cases, benzocyclobutene (BCB) and acrylic resin (resin). It is formed by depositing one of the included organic insulating materials.

7A and 7B illustrate a process of forming an active layer and an ohmic contact layer. As illustrated, the active layer is formed on the gate insulating layer 108 corresponding to the gate electrode 104. 110 and an ohmic contact layer 112 are formed.

The active layer 110 and the ohmic contact layer 112 include pure amorphous silicon (a-Si: H) and amorphous silicon (n + or p + a-Si: H) containing impurities on the gate insulating layer 108. It can be formed by depositing and patterning it.

8A and 8B illustrate a process of forming a source electrode 114, a drain electrode 116, and a data line 118. As illustrated, the active layer 110 and the ohmic contact layer 112 are illustrated. Depositing and patterning a selected one of the above-mentioned conductive metal materials on top of the, to extend the source electrode 114 and the drain electrode 116, the source electrode 114, and intersect the gate wiring 102. The data line 118 extending above the first repair line 106 is formed.

Subsequently, the ohmic contact layer 112 exposed between the source electrode 114 and the data line 118 is removed to expose the lower active layer 110.

In this case, the source electrode 114 is formed in a “U” shape, and the drain electrode 116 is formed in a bar shape positioned parallel to the inside of the source electrode 114.

In this way, the active layer 110 exposed between the source and drain electrodes 114 and 116 due to the shape of the source and drain electrodes 114 and 116 is formed as a “U” channel.

This shape has the advantage that the on current increases because the channel length is short and the channel width is wide.

9A and 9B illustrate a process of forming a passivation layer 120 including a contact hole, and silicon nitride is formed on the entire surface of the substrate 100 on which the source and drain electrodes 114 and 116 and the data line 118 are formed. Organic insulating material including benzocyclobutene (BCB) and acrylic resin (resin), or depositing one selected from the group of inorganic insulating material containing (SiN _X ) or silicon oxide (SiO ₂ ) A protective film 120 is formed by applying one selected from the group.

Subsequently, the passivation layer 120 is patterned to form a drain contact hole 122 exposing a part of the drain electrode 116.

10A and 10B illustrate a process of forming the pixel electrode 124 and the second repair wiring 126. Indium tin oxide (ITO) is formed on the entire surface of the substrate 100 on which the passivation layer 120 is formed. Depositing and patterning a selected one of a transparent conductive metal group including and indium-ink-oxide (IZO) to form a pixel electrode 124 positioned in the pixel region P while contacting the drain electrode 116. do.

At the same time, the second repair wiring 126 is formed on the data wiring 118 where the first repair wiring 106 is not located so as to overlap with the plan.

In this case, the second repair wiring 126 is independently formed in each region of the region where the first repair wiring 106 is not formed, that is, in the upper portion of the data wiring 118 that crosses the gate wiring 102.

The second repair wiring 126 has a shape formed over the first repair wiring 106 configured as above and below.

As described above, the array substrate for the transverse electric field type liquid crystal display device according to the present invention can be manufactured.

The configuration of the repair wiring according to the present invention as described above is applicable to all active matrix type liquid crystal display array substrates regardless of the driving method.

Therefore, the liquid crystal display array substrate according to the present invention further comprises a repair wiring made of the same material as the pixel electrode on the upper part of the data wiring near the gate wiring so that the repair wiring can be used when the data wiring is disconnected. Since it can be repaired, even if a defect is found after the completion of the liquid crystal panel can be repaired to lower the defect of the panel has the effect of improving the production yield.

Claims (10)

A substrate; Gate wiring and data wiring intersecting each other on the insulating substrate to define a pixel region; A first repair wiring positioned below the data wiring and independently configured to be in contact with the gate wiring; A thin film transistor configured at an intersection point of the gate line and the data line; A transparent pixel electrode in the pixel area in contact with the thin film transistor; Second repair wiring located above the data wiring near the gate wiring Array substrate for a liquid crystal display device comprising a. The method of claim 1, The thin film transistor may include a gate electrode connected to the gate line, an active layer and an ohmic contact layer on the gate electrode, a source electrode spaced apart from the ohmic contact layer and in contact with the data line, and a drain electrode in contact with the pixel electrode. Array substrate for a liquid crystal display device comprising. The method of claim 2, And the source electrode is formed in a “U” shape, and the drain electrode is formed in a bar shape parallel to the inside of the source electrode. The method of claim 1, And the first repair wiring is formed of the same material as the gate wiring. The method of claim 1, And the second repair wiring is formed of the same material as the pixel electrode. Defining a plurality of pixel regions on the substrate; Forming a gate wiring formed on one side of the pixel region on the substrate and a first repair wiring for each region between the pixel regions so as not to contact the gate wiring; Forming a data wiring crossing the gate wiring and configured to extend over the first repair wiring; Forming a thin film transistor at an intersection point of the gate line and the data line; Forming a second repair wiring on the transparent pixel electrode in contact with the thin film transistor and positioned in the pixel region, and a second repair wiring on an upper portion of the data wiring which intersects the gate wiring and the first repair wiring is not located below. Array substrate manufacturing method for a liquid crystal display device comprising a. The method of claim 6, The thin film transistor may include a gate electrode connected to the gate line, an active layer and an ohmic contact layer on the gate electrode, a source electrode spaced apart from the ohmic contact layer and in contact with the data line, and a drain electrode in contact with the pixel electrode. Array substrate manufacturing method for a liquid crystal display device comprising a. The method of claim 6, And the first repair wiring is formed of the same material as the gate wiring. The method of claim 6, And the second repair wiring is formed of the same material as the pixel electrode. The method of claim 9, And the pixel electrode and the second repair line are formed of one selected from the group of transparent conductive metals including indium tin oxide (ITO) and indium zinc oxide (IZO).

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