KR20060106197A - Liquid crystal display - Google Patents

Abstract

A liquid crystal display device having an anti-lock structure is provided. The liquid crystal display includes a gate line, a data line crossing the gate line, a thin film transistor connected to the gate line and the data line, a pixel electrode connected to the thin film transistor, and one of the data line and the gate line. The pad electrode is connected to one line and includes a pad electrode made of a metal material including a pad opening, and a protection electrode made of the same material as the pixel electrode and electrically connected to the pad electrode.

LCD, aluminum, hillock, pad opening

Description

Liquid crystal display

1 is a schematic diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

2 is a cross-sectional view illustrating a liquid crystal display according to an exemplary embodiment of the present invention.

3 and 4 are layouts illustrating gate pad electrodes included in a liquid crystal display according to an exemplary embodiment of the present invention.

5 to 7 illustrate layouts of gate pads included in the liquid crystal display according to the exemplary embodiment.

8A to 8E are cross-sectional views of intermediate structures in each step of a method of manufacturing a liquid crystal display according to an exemplary embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

31 substrate 36 pixel electrode

40: gate electrode 44: protective electrode

48: gate insulating layer 50: active layer

52: gate pad electrode 56: ohmic connection layer

58: protective layer 61: pad opening

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device having a hillock preventing structure.

In today's information society, the role of electronic display devices becomes more and more important, and various electronic display devices are widely used in various industrial fields.

Rapid advances in semiconductor technology have resulted in low-voltage and low-power electronic devices, as well as smaller and lighter electronic devices, making them suitable for new environments, namely flat panel panels with thin, light, low drive voltages and low power consumption. The demand for flat panel display devices is rapidly increasing.

Among the various flat panel display devices currently developed, liquid crystal displays are thinner and lighter than other display devices, have low power consumption and low driving voltage, and are widely used in various electronic devices because they are capable of displaying images close to cathode ray tubes. Is being used.

Among the liquid crystal display devices, one of the most commonly used liquid crystal display devices includes a thin film transistor (TFT) that has electrodes formed on two substrates and switches a voltage applied to each electrode. It is common to be formed in one. Liquid crystal displays using thin film transistors in the pixel portion are classified into an amorphous type and a polycrystalline type.

As the size of liquid crystal displays increases, it is required to form wiring with a material having low resistance in order to prevent signal delay. Therefore, in order to implement a liquid crystal display of a large area screen, a gate wiring is formed using a low resistance metal material such as aluminum (Al).

However, aluminum (Al) has a high coefficient of thermal expansion, so when the material has a small coefficient of thermal expansion, for example, when connected to an interface with a glass substrate, it generates a hillock due to compressive stress due to a difference in thermal expansion. .

Hillock refers to a needle-like protrusion that occurs on the surface of aluminum (Al), and the protrusion penetrates the insulating film laminated on the aluminum (Al), and there is a risk of shorting with other conductive layers or causing poor insulation.

An object of the present invention is to provide a liquid crystal display device having a hillock preventing structure.

Technical problems to be achieved by the present invention are not limited to the above-mentioned technical problems, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

According to an exemplary embodiment of the present invention, a liquid crystal display device includes a gate line, a data line crossing the gate line, a thin film transistor connected to the gate line and the data line, and a thin film transistor. A pixel electrode connected to any one of the data line and the gate line, the pad electrode made of a metallic material including a pad opening, and the same material as the pixel electrode and electrically connected to the pad electrode. And a protective electrode to be connected.

Specific details of other embodiments are included in the detailed description and the drawings.

Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention, and the general knowledge in the art to which the present invention pertains. It is provided to fully convey the scope of the invention to those skilled in the art, and the present invention is defined only by the scope of the claims. Like reference numerals refer to like elements throughout.

Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. 1 to 8E.

1 is a schematic diagram of a liquid crystal display according to an exemplary embodiment of the present invention. Referring to FIG. 1, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal display panel 100, a gate driver 200, and a data driver 300.

The liquid crystal display panel 100 includes a plurality of pixels connected to a plurality of gate lines G1 to Gn and a plurality of data lines D1 to Dm, and each pixel includes a plurality of gate lines G1 to Gn. A switching element M connected to the data lines D1 to Dm, a liquid crystal capacitor Clc, and a storage capacitor Cst connected thereto are included.

The plurality of gate lines G1 to Gn formed in the row direction transmit a gate signal to the switching element M, and the plurality of data lines D1 to Dm formed in the column direction transmit data to the switching element M. The gray voltage corresponding to the signal is transmitted. The switching element M is a three-terminal element, the control terminal is connected to the gate lines G1 to Gn, the input terminal is connected to the data lines D1 to Dm, and the output terminal is the liquid crystal capacitor Clc. And one terminal of the storage capacitor Cst. The liquid crystal capacitor Clc is connected between the output terminal of the switching element M and the common electrode (not shown), and the storage capacitor Cst is connected between the output terminal of the switching element M and the common electrode (independent wiring). Method) or a connection (shear gate method) between the output terminal of the switching element M and the gate lines G1 to Gn directly above.

The gate driver 200 is connected to the plurality of gate lines G1 to Gn, and provides a gate signal for activating the switching element M to the plurality of gate lines G1 to Gn, and the data driver 300 It is connected to a plurality of data lines D1 to Dm.

Here, the MOS transistor is used as the switching element M, and the MOS transistor may be implemented as, for example, a thin film transistor. In addition, the gate driver 200 or the data driver 300 may also be configured as MOS transistors. Such MOS transistors may be implemented as thin film transistors, for example.

Subsequently, a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to FIG. 2. 2 is a cross-sectional view illustrating a liquid crystal display according to an exemplary embodiment of the present invention.

Referring to FIG. 2, the lower substrate 31 includes a thin film transistor positioned at an intersection of a data line (not shown) and a gate line (not shown), and a pixel electrode connected to the drain electrode 42 of the thin film transistor. 14, a gate pad GP and a data pad DP (not shown) connected to a driving circuit (not shown) are provided at one end of each of the gate line and the data line.

The thin film transistor includes a gate electrode 40 connected to a gate line, a source electrode 38 connected to a data line, and a drain electrode 42 connected to the pixel electrode 36 through a contact hole 46a. In addition, the thin film transistor includes an active layer 50 for forming a channel between the source electrode 38 and the drain electrode 42 by the gate voltage supplied to the gate electrode 40. This thin film transistor selectively supplies the data signal from the data line to the pixel electrode 36 in response to the gate signal from the gate line.

The pixel electrode 36 is located in a cell region defined by the data line and the gate line and is made of an ITO material having high light transmittance. The pixel electrode 36 generates a potential difference from a common transparent electrode (not shown) formed on the upper substrate by a data signal supplied through the contact hole 46a. This potential difference causes the liquid crystal located between the lower substrate and the upper substrate to rotate by dielectric anisotropy, and transmits light supplied from the light source via the pixel electrode 36 toward the upper substrate.

The gate pad GP is formed through the gate pad electrode 52 formed on the substrate 31, the contact holes 46b and 46c formed through the gate insulating layer 48 and the passivation layer 58 on the gate pad electrode 52. The protective electrode 44 connected via the same is provided.

The data pad DP may include a contact hole formed through a data pad electrode (not shown) formed on the gate insulating layer 48 and a passivation layer (not shown) formed to cover the data pad electrode. A protective electrode connected through) is provided.

The gate pad GP as described above will be described in more detail with reference to FIGS. 3 to 7. 3 and 4 are layouts illustrating gate pad electrodes included in a liquid crystal display according to an exemplary embodiment of the present invention. 4 to 7 illustrate layouts of gate pads included in the liquid crystal display according to the exemplary embodiment.

For convenience of description, the description is limited to the gate pad GP. However, the data pad DP can also be applied.

The gate pad electrode 52 of the gate pad GP may be made of a low resistance metal material such as aluminum (Al). Since aluminum (Al) has a large coefficient of thermal expansion, when it forms an interface with a substrate made of glass or the like having a small coefficient of thermal expansion, heel lock may occur due to compressive stress caused by a difference in thermal expansion. That is, when subjected to compressive stress, a weak strength material such as aluminum (Al) generates a heel lock to relieve the stress, and the stress starts to decrease by the generation of the heel lock. In particular, as the unit area of the gate pad electrode increases, more compressive stress is generated, and accordingly, more heel lock is generated.

In order to prevent the hillock as described above, the gate pad electrode 52 may have a structure including a pad opening 61 having an opening having an I shape as shown in FIG. 3. In addition, as shown in FIG. 4, the gate pad electrode 52 may have a structure including a pad opening 61 in which two or more I-shaped openings 61a and 62b are aligned in a straight line. The shape and the number of the openings of the gate pad portion 61 are not particularly limited.

As shown in FIGS. 3 and 4, the gate pad electrode 52 having the structure including the pad opening 61 is formed in the gate pad electrode 52 by reducing the unit area of the gate pad electrode 52. There is an effect of dispersing the compressive stress. In addition, the pad opening 61 of the gate pad electrode 52 may serve as a buffer zone in which stress applied to the gate pad electrode 52 can be released. Therefore, the gate pad electrode 52 including the pad opening 61 having at least one opening can prevent hillock generation, which has occurred when the gate pad electrode is formed of aluminum.

3 and 4, the width w1 of the pad opening 61 of the gate pad electrode 52 may have a width equal to or smaller than the width w2 of the metal part of the gate pad electrode 52. have.

5 to 7, the gate pad GP is formed on the gate pad electrode 52 with the gate insulating layer (see 48 in FIG. 2) and the protective layer (see 58 in FIG. 2) and the gate insulating layer. A contact hole formed through the 48 and the protective film 58;

The contact hole is a part for the electrical connection between the gate pad electrode 52 and the protection electrode 44, and the shape and number of the contact holes as long as it has a structure that enables the electrical connection between the pad electrode 52 and the protection electrode 44. Is not particularly limited. For example, when the gate pad electrode 52 has a pad opening 61 including one opening, as shown in FIG. 5, the contact holes 46b and 46c are centered around the pad opening 61. The gate pad electrode 52 may be exposed at both sides in a direction parallel to the pad opening 61. 6, contact holes 46b ', 46b ", 46c', and 46c" are formed on both sides of the pad opening 61, respectively, and are aligned in a row. The gate pad electrode 52 may be exposed by being formed parallel to the 61. For example, when the gate pad electrode 52 has a pad opening 61 including two openings 61a and 61b, as shown in FIG. 7, the contact holes 46b ', 46b ", 46c 46c &quot; are formed on both sides of each of the openings 61a and 61b, respectively, and are aligned in a row and in parallel with the pad opening 61 to expose the gate pad electrode 52. have. In addition, various types of contact holes may be formed.

5 to 7 are cross-sectional views taken along the lines I-I ', II-II' and III-III ', respectively, as shown in FIG.

Hereinafter, a method of manufacturing a liquid crystal display according to an exemplary embodiment of the present invention will be described with reference to FIGS. 8A to 8E. For convenience of description, the manufacturing method of the liquid crystal display device will be described by exemplifying the gate pad GP. However, the present invention is not limited thereto. 8A to 8E are cross-sectional views of intermediate structures in each step of a method of manufacturing a liquid crystal display according to an exemplary embodiment of the present invention.

Referring to FIG. 8A, a gate electrode 40 and a gate pad electrode 52 are formed on the substrate 31.

The gate electrode 40 and the gate pad electrode 52 are deposited on the substrate 31 by a method such as sputtering to deposit aluminum (Al) or the like to form a metal thin film by a photolithography method including a wet method. Patterned to form a single metal layer.

In this case, the gate pad electrode 52 is formed to include the pad opening 61. At this time, the number and shape of the openings included in the pad opening 61 are not particularly limited.

Referring to FIG. 8B, a gate insulating layer 48, an active layer 50, and an ohmic connecting layer 56 are formed on the substrate 31. The gate insulating layer 48, the active layer 50, and the ohmic contact layer 56 are formed at a low temperature with a plasma enhanced chemical vapor deposition (PECVD) to cover the gate pad electrode 52 and the gate electrode 40 on the substrate 31. Are formed sequentially. The ohmic connection layer 56 and the active layer 50 are patterned to expose the gate insulating layer 48 by a photolithography method including etching.

The gate insulating layer 48 is formed by depositing an insulating material such as silicon nitride (SiN _x ) or silicon oxide (SiO _x ). The active layer 50 may be formed of amorphous silicon that is not doped with impurities. In addition, the ohmic connection layer 56 may be formed of amorphous silicon doped with N-type or P-type impurities.

Referring to FIG. 8C, source and drain electrodes 38 and 42 are formed on the gate insulating layer 48. The source and drain electrodes 38 and 42 may be formed of chromium (Cr) or molybdenum (Mo). The source and drain electrodes 38 and 42 are deposited by a CVD method or a sputtering method so as to cover the ohmic connection layer 26, and then patterned by a photolithography method so that the gate insulating layer 48 is exposed. Is formed.

During patterning of the source and drain electrodes 38 and 42, the ohmic connection layer 56 corresponding to the gate electrode 40 is also patterned to expose the active layer 50. The portion of the active layer 50 corresponding to the gate electrode 40 between the source and drain electrodes 38 and 42 becomes a channel.

Referring to FIG. 8D, a protective layer 58, a contact hole 46a and a contact hole 46b or 46b ', 46c or 46c' are formed on the gate insulating layer 48. The protective layer 58 covers the gate pad electrode 52, the source and drain electrodes 38 and 42, and an inorganic insulating material such as silicon nitride and silicon oxide, an acryl organic compound, teflon, and BCB ( It may be formed by depositing an organic insulator having a small dielectric constant such as BenzoCycloButene), cyto or PFCB (PerFluoroCycloButane).

The contact hole 46a and the contact hole 46b or 46b ', 46c or 46c' are formed by patterning the protective layer 58 by photolithography to expose the drain electrode 42 and the gate pad electrode 52. .

Referring to FIG. 8E, the protective electrode 44 and the pixel electrode 36 are formed on the protective layer 58.

One of ITO and IZO, which are transparent conductive materials, may be deposited on the protective layer 58. Then, a photoresist is applied, the photoresist is exposed using an exposure mask having a predetermined pattern, and developed to form a photoresist pattern. The substrate 31 on which the photoresist pattern is formed is dipped in an etchant of HCl + HNO ₃ + deionized water. The etchant simultaneously etches the transparent conductive material to form the protective electrode 44. After etching, the photoresist pattern remaining on the pixel electrode 36 and the protective electrode 44 is removed.

The pixel electrode 36 is connected to the drain electrode 42 through the contact hole 46a, and the protective electrode 44 is connected to the gate pad electrode 52 through the contact hole 46b or 46b ', 46c or 46c'. Electrically connected.

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention pertains can realize that the present invention can be implemented in other specific forms without changing the technical spirit or essential features. I can understand that. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive.

According to the liquid crystal display according to the exemplary embodiment of the present invention as described above, the pad electrode has a structure including a pad opening having at least one opening, thereby preventing heel lock even when the pad electrode is formed of aluminum. The defect of the liquid crystal display device can be reduced.

Claims (6)

Gate lines; A data line crossing the gate line; A thin film transistor connected to the gate line and the data line, respectively; A pixel electrode connected to the thin film transistor; A pad electrode connected to any one of the data line and the gate line, the pad electrode including a pad opening; And And a protective electrode made of the same material as the pixel electrode and electrically connected to the pad electrode. The method of claim 1, The pad electrode is made of aluminum. The method of claim 1, The pad opening has an I-shape. The method of claim 3, wherein The pad opening may include two or more I-shaped openings. The method of claim 1, And a gate insulating layer and a protective layer on the pad electrode and the protective electrode. The method of claim 5, And the pad electrode is electrically connected to the protective electrode through a contact hole formed through the gate insulating layer and the protective layer.

Images