KR20060105223A - An array substrate for fringe field switching mode lcd and method of fabricating of the same - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a structure of a fringe field switching (FFS) type array substrate for a liquid crystal display device and a method of manufacturing the same.

The FFS type liquid crystal display array substrate according to the present invention is characterized in that the common electrodes are individually patterned so as to have a minimum separation space (1 μm) between the common electrode and the pixel electrode. An array substrate for a liquid crystal display device is produced by a four mask process.

As described above, there is an advantage that the afterimage problem caused by the overlapping structure of the conventional pixel and the common electrode can be solved by spacing the gap between the common electrode and the pixel electrode to a minimum.

In addition, the above-described configuration can be produced in a four-mask process using a lift-off method using a photosensitive layer, it is effective to improve the process yield by reducing the process time and process cost through the process simplification have.

Description

An array substrate for fringe field switching mode LCD and method of fabricating of the same}

1 is a cross-sectional view schematically showing a part of a general transverse electric field type liquid crystal display device,

2 is an enlarged plan view showing one pixel of a conventional array substrate for a transverse electric field type liquid crystal display device;

3 is an enlarged plan view of a portion of an array substrate for a general FFS type liquid crystal display device;

4A to 9A and 4B to 9B and 4C to 9C and 4D to 9D are cut along the lines IV-IV, V-V, VI-VI, VIII-V of FIG. It is a process sectional drawing shown in order of a process,

10 is an enlarged plan view illustrating an enlarged portion of an array substrate for an FFS type liquid crystal display device according to the present invention;

11A to 22A, 11B to 22B, 11C to 22C, and 11D to 22D illustrate the process sequence of the present invention by cutting VIII-VIII, VIII-VIII, VIII-XI, VIII-XI of FIG. It is the process cross section shown according to the

FIG. 23 is a diagram illustrating a process of removing the passivation layer on the gate pad electrode and the data pad electrode.

<Brief description of the main parts of the drawing>

200: substrate 202: gate wiring

204: gate electrode 206: gate pad

207: common wiring 222: data wiring

224: data pad 228: second pattern (semiconductor layer)

230a: active layer 232: source electrode

234: drain electrode 252: pixel electrode

254 common electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to an array substrate for a high quality FFS liquid crystal display device having no afterimage and a manufacturing method thereof.

In general, the driving principle of the liquid crystal display device uses the optical anisotropy and polarization of the liquid crystal. Since the liquid crystal is thin and long in structure, the liquid crystal has directivity in the arrangement of molecules, and the direction of the molecular arrangement can be controlled by artificially applying an electric field to the liquid crystal.

Accordingly, if the molecular arrangement direction of the liquid crystal is arbitrarily adjusted, the molecular arrangement of the liquid crystal is changed, and light is refracted in the molecular arrangement direction of the liquid crystal due to optical anisotropy to express image information.

Currently, an active matrix liquid crystal display device (AM-LCD: below Active Matrix LCD, abbreviated as liquid crystal display device) in which a thin film transistor and pixel electrodes connected to the thin film transistor are arranged in a matrix manner has the best resolution and video performance. It is attracting attention.

The liquid crystal display includes a color filter substrate (upper substrate) on which a common electrode is formed, an array substrate (lower substrate) on which a pixel electrode is formed, and a liquid crystal filled between upper and lower substrates. In such a manner that the liquid crystal is driven by an electric field applied up and down, the pixel electrode has excellent characteristics such as transmittance and aperture ratio.

However, the liquid crystal drive by the electric field applied up-down has a disadvantage that the viewing angle characteristics are not excellent. Therefore, new techniques have been proposed to overcome the above disadvantages. The liquid crystal display device to be described below has an advantage of excellent viewing angle characteristics by a liquid crystal driving method using a transverse electric field.

Hereinafter, a general transverse electric field type liquid crystal display device will be described in detail with reference to FIG. 1.

1 is an enlarged cross-sectional view illustrating a cross section of a general transverse electric field type liquid crystal display device.

As shown, the conventional transverse electric field type liquid crystal display device (B) is composed of a color filter substrate B1 and an array substrate B2 facing each other, and a liquid crystal between the color filter substrate and the array substrates B1 and B2. The layer LC is interposed.

The array substrate B2 includes a thin film transistor T, a common electrode 30, and a pixel electrode 32 for each of the pixels P1 and P2 defined in the transparent insulating substrate 10.

The thin film transistor T may include a gate electrode 14, a semiconductor layer 18 having an insulating layer 16 disposed on the gate electrode 14, and a source configured to be spaced apart from each other on the semiconductor layer 18. And drain electrodes 20 and 22.

In the above-described configuration, the common electrode 30 and the pixel electrode 32 are configured to be spaced apart from each other in parallel on the same substrate.

In general, the common electrode 30 is made of the same material as the gate electrode 14, and the pixel electrode 32 is made of the same material as the source and drain electrodes 20 and 22. However, as shown in order to increase the aperture ratio, the pixel electrode 32 may be formed as a transparent electrode.

Although not shown, a gate line (not shown) extending along one side of the pixel P and a data line (not shown) extending in a direction perpendicular thereto are formed, and a voltage is applied to the common electrode 30. The common wiring (not shown) to apply is comprised.

The color filter substrate B1 has a black matrix 42 formed at a portion corresponding to the gate wiring (not shown), the data wiring (not shown), and the thin film transistor T on the transparent insulating substrate 10. The color filters 34a and 34b are configured to correspond to the pixels P.

The liquid crystal layer LC is operated by the horizontal electric field 45 of the common electrode 30 and the pixel electrode 32.

Hereinafter, with reference to FIG. 2, the structure of the array substrate which comprises a transverse electric field type liquid crystal display device is demonstrated.

2 is a plan view schematically illustrating a configuration of a conventional array substrate for a transverse electric field type liquid crystal display device.

As shown in the drawing, the gate wiring 12 extending in one direction on the substrate 10 and the data wiring 24 defining the pixel region P by crossing the gate wiring 12 perpendicularly are formed. .

In addition, the common wiring 15 is formed to cross the pixel region P while being spaced in parallel with the gate wiring 12.

At the intersection of the gate wiring 12 and the data wiring 24, the gate electrode 14 connected to the gate wiring 12, the semiconductor layer 28 on the gate electrode 14, and the semiconductor layer 28 The thin film transistor T including the upper source electrode 20 and the drain electrode 22 is configured.

In the pixel region P, a common electrode 30 extending vertically to the pixel region P while contacting the common wiring 15 is formed, and the common electrode 30 is in contact with the drain electrode 22. ), A pixel electrode 32 extending to a position spaced in parallel with each other is formed.

 In the above-described configuration, the common electrode 30 and the pixel electrode 32 are formed as a transparent electrode in order to ensure luminance, but by design, by the separation distance between the common electrode 30 and the pixel electrode 32, Only a part of both of the common electrode 30 and the pixel electrode 32 contributes to the improvement of luminance, and most of the regions result in blocking light.

Therefore, the minimum brightness improvement effect can be obtained.

Proposed to improve this problem is the FFS (Fringe Field Switching) technology.

The FFS technology precisely controls the liquid crystal to obtain a high contrast ratio without high color shift and high contrast ratio even at the side viewing angle with a 180 degree wide viewing angle. There is an advantage to realizing quality.

3 is an enlarged plan view of a part of an array substrate for a conventional FFS type liquid crystal display device according to the related art.

As shown, the FFS method includes a gate line 106 extending in one direction on the transparent insulating substrate 100 and including a gate pad 110 at one end thereof, and a pixel area crossing the gate line 106. A data line 122 defining (P) and including a data pad 124 at one end is formed.

The gate pad electrode 136 and the data pad electrode 138 are formed on the gate pad 110 and the data pad 124 to contact them.

At the intersection of the gate wiring 106 and the data wiring 122, the gate electrode 108 in contact with the gate wiring 106, the semiconductor layer 114 over the gate electrode 108, and the semiconductor layer 114 A thin film transistor (T) including a source electrode 118 positioned on the upper side of the ()) and in contact with the data line 122 and a drain electrode 120 spaced apart from the predetermined distance.

The common electrode 102 is formed in the pixel region P, and the pixel electrode 134 is formed on the common electrode 102 by patterning a plurality of vertical portions spaced apart from each other.

In the above-described configuration, a liquid crystal layer (not shown) is driven by an electric field generated between the lower common electrode 102 and the upper pixel electrode 134, and between the common electrode 102 and the pixel electrode 134. The electric field causes normal operation even for a liquid crystal (not shown) located at the center of the pixel electrode 134 due to the effect of becoming very close (this is called a "fringe field effect").

Therefore, unlike the conventional IPS technology, a high luminance can be obtained due to the effect of extending the transmission area.

Hereinafter, a manufacturing process of an array substrate for a conventional FFS liquid crystal display device will be described with reference to the drawings.

4A to 9A, 4B to 9B, 4C to 9C, and 4D to 9D are cut along the lines IV-IV, V-V, VI-VI, VIII-V of FIG. It is process sectional drawing shown in order.

4A to 4D are diagrams illustrating a first mask process, and an indium tin oxide on a transparent insulating substrate 50 having a plurality of pixel regions P, a gate region G, and a data region D defined therein. One selected from a group of transparent conductive metals including ITO and indium zinc oxide (IZO) is deposited and patterned by a first mask process to form a common electrode 102 corresponding to the pixel region P. .

Next, one or more materials selected from the group of transparent conductive metals including silicon nitride (SiN _X ) and silicon oxide (SiO ₂ ) are deposited on the entire surface of the substrate 100 on which the common electrode 102 is formed. The insulating film 104 is formed.

5A to 5D are diagrams illustrating a second mask process, wherein aluminum (Al), tungsten (W), copper (Cu), and molybdenum (Mo) are formed on the entire surface of the substrate 100 on which the first insulating film 104 is formed. And depositing one selected from a group of conductive metals including chromium (Cr) and titanium (Ti) and patterning the same by a second mask process to extend in one direction to the gate region G and at one end of the gate pad 110. The gate wiring 106 including the gate wiring 106 and the gate electrode 108 connected to the gate wiring 106 and positioned in the switching region S are formed.

At the same time, a common wiring (105 in FIG. 3) spaced in parallel with the gate wiring 106 is formed.

Next, one selected from the group of organic insulating materials including silicon nitride (SiN _X ) and silicon oxide (SiO ₂ ) is deposited on the entire surface of the substrate 100 on which the gate pad, the gate wiring, and the gate electrodes 110, 106, and 108 are formed. The gate insulating film 112 is formed.

6A to 6D illustrate a third mask process, wherein amorphous silicon (a: Si—H) and an amorphous silicon (n + or p) containing impurities are formed on the entire surface of the substrate 100 on which the gate insulating layer 112 is formed. + a-Si: H) is deposited and patterned by a third mask process to form an active layer 114 and an ohmic contact layer 116 on the gate insulating layer 112 corresponding to the gate electrode 108.

7A to 7D illustrate a fourth mask process, in which one or more materials selected from the above-described conductive metal group are deposited on the entire surface of the substrate 100 on which the active layer and the ohmic contact layers 114 and 116 are formed. Patterned by a four-mask process, the source electrode 118 and the drain electrode 120 spaced apart on the ohmic contact layer 116, and connected to the source electrode 118 and includes a data pad 124 at one end; The data line 122 is formed to intersect with the gate line 106.

8A to 8D illustrate a fifth mask process, wherein one or more selected ones of the aforementioned organic insulating material groups are formed on the front surface of the substrate 100 on which the source and drain electrodes 118 and 120, the data lines and the data pad are formed. The protective film 126 is formed by depositing one or more materials selected from the group of organic insulating materials including benzocyclobutene (BCB) and an acrylic resin (resin).

Next, the passivation layer 126 is patterned in a fifth mask process to expose the drain electrode 120, the drain contact hole 128 exposing the gate pad 110, and the gate pad contact hole 130 exposing the gate pad 110. In addition, a data pad contact hole 132 exposing the data pad 124 is formed.

9A to 9D are views illustrating a sixth mask process, and includes transparent indium tin oxide (ITO) and indium zinc oxide (IZO) on the entire surface of the substrate 100 on which the passivation layer 126 is formed. A selected one of the conductive metal groups is deposited and patterned by a sixth mask process to form a pixel electrode 134 in contact with the drain electrode 120, a gate pad electrode 136 in contact with the gate pad 110, and the A data pad electrode 138 is formed in contact with the data pad 124.

In this case, the pixel electrode 134 is formed in a state in which a plurality of bar shapes are spaced apart from each other to correspond to the pixel area P, and is formed to overlap the common electrode 102 in plan view.

Through the above-described process, it is possible to manufacture an array substrate for a liquid crystal display device of the conventional FFS method.

However, in the conventional FFS type liquid crystal display array substrate, since a parasitic cap is generated due to the overlapping portion of the pixel electrode 134 and the common electrode 102, there is a problem of remaining afterimage. have.

In addition, since it is manufactured in the six mask process as described above, the process time is delayed and the process cost increases due to a number of mask processes, there is a problem that the competitiveness of the product is lowered.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to propose a method of manufacturing a high-quality FFS liquid crystal display array substrate without afterimages by a low mask process.

The FFS type liquid crystal display device according to the present invention for achieving the above object is characterized in that the pixel electrode and the common electrode are configured to maintain the minimum separation distance, and the array substrate configured as described above is manufactured by a four mask process. It is done.

According to another aspect of the present invention, there is provided an array substrate for an FFS type liquid crystal display device, the method including: defining a plurality of pixel areas including a switching area on a substrate; A first mask process step of forming a gate electrode extending in one direction, a common wiring spaced apart from the substrate, and a gate electrode corresponding to the switching region; Forming a gate insulating film on an entire surface of the substrate on which the gate wiring, the common wiring and the gate electrode are formed; A second mask process step of forming a semiconductor layer on the gate insulating film above the gate electrode, source and drain electrodes spaced apart on the semiconductor layer, and a data wire crossing the gate wire; A third mask process step of forming a first transparent electrode pattern positioned in the pixel region while being in contact with the drain electrode; A fourth mask process step of forming a first photosensitive layer on an entire surface of the substrate on which the first transparent electrode pattern is formed, and forming a plurality of rod-shaped etching holes corresponding to the pixel region; Removing the first transparent electrode layer and the gate insulating layer below the first transparent electrode layer exposed by the etching hole, wherein the first projection electrode layer is over-etched under the photosensitive layer; Forming a transparent electrode layer on an entire surface of the photosensitive layer including the plurality of etching holes; Removing the photosensitive layer to form a common electrode formed in the etching hole and a pixel electrode disposed on the gate insulating layer; Forming a passivation layer on an entire surface of the substrate on which the common electrode, the pixel electrode, and the source and drain electrodes are formed.

The second mask process may include depositing an amorphous silicon layer, an impurity amorphous silicon layer, and a conductive metal layer on the gate insulating layer; Forming a photosensitive layer on top of the conductive metal layer, and placing a mask composed of a transmissive part, a blocking part, and a semi-transmissive part spaced apart from the photosensitive layer; Irradiating light from the upper portion of the mask to expose the lower photosensitive layer and developing the first photosensitive pattern having a different height corresponding to the switching region, and forming a second photosensitive pattern extending from the first photosensitive pattern. Steps; The conductive metal layer, the impurity amorphous silicon layer, and the pure amorphous silicon layer exposed to the periphery of the first and second photosensitive patterns are removed, thereby forming a data line connected to the metal layer corresponding to the gate electrode and intersecting the gate wiring. Forming; Ashing the first and second photosensitive patterns to completely remove a lower portion of the first photosensitive pattern to expose a lower conductive metal layer; Removing the exposed conductive metal layer and an impurity amorphous silicon layer below the source and drain electrodes, the source and drain electrodes spaced apart corresponding to the upper portion of the gate electrode, and the ohmic contact layer and the lower portion thereof. Forming an active layer.

In the process of removing the photosensitive layer, it is characterized in that the transparent electrode layer on the surface of the photosensitive layer is removed at the same time.

The transparent electrode layer is removed through a wet etching process, and includes forming a gate pad at one end of the gate line and a data pad at one end of the data line.

And forming a second transparent electrode pattern and a third transparent electrode pattern on the gate pad and the data pad while forming the first transparent electrode pattern.

Simultaneously forming the common electrode, and forming a transparent gate pad electrode in contact with the gate pad and a transparent data pad electrode (third transparent electrode pattern) in contact with the data pad.

The forming of the gate pad electrode and the data pad electrode may include forming a photosensitive layer on top of the second and third transparent electrode patterns, etching the photosensitive layer and forming a portion corresponding to the gate pad. Etching the gate insulating film; Forming a transparent electrode layer on a surface of the photosensitive layer, an exposed side surface of the etched gate insulating layer, and the gate pad; Removing the photosensitive layer to form a gate pad electrode in contact with the gate pad and a data pad electrode (third transparent electrode pattern) in contact with the data pad.

The pixel electrode and the common electrode are spaced apart at a maximum of 1 μm.

According to an aspect of the present invention, there is provided a method of manufacturing an FFS type liquid crystal display device, comprising: forming a liquid crystal panel by bonding an array substrate for a liquid crystal display device and a separate color filter substrate; Cutting the color filter substrate in a portion corresponding to the gate pad electrode and the data pad electrode formed on the array substrate to expose a lower protective film; And removing the passivation layer using a plasma etching method to expose the lower gate pad electrode and the data pad electrode.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

Example

10 is an enlarged plan view of a portion of an array substrate for an FFS type liquid crystal display device according to the present invention.

As shown, a gate line 202 extending in one direction and including a gate pad 206 at one end and a gate electrode 204 connected to the gate line 202 are formed on the substrate 200. .

The data line 222 including the data pad 224 is formed at one end of the pixel region P by crossing the gate line 202.

A transparent gate pad electrode 256 in contact with the gate pad 224 is formed on the gate pad 224, and a transparent data pad electrode 258 in contact with the data pad electrode 224 is formed on the gate pad 224.

A thin film transistor T including a gate electrode 204, an active layer 23a and an ohmic contact layer, and source and drain electrodes 232 and 234 is formed at an intersection point of the gate line 202 and the data line 222. Make up.

In the pixel region P, a rod-shaped common electrode 254 and a pixel electrode 252 are configured, but the separation distance between the two electrodes is configured to be 1 μm or less at most.

In this configuration, the transparent common electrode and the liquid crystal (not shown) located above the pixel electrodes 254 and 252 may also operate normally due to the fringe field effect, thereby widening the transmission region and thus obtaining high transmission characteristics. have.

In addition, since there is no overlap area between the common electrode 254 and the pixel electrode 252, there is an advantage of preventing afterimages.

In the above-described configuration, the semiconductor layer 230a and the source and drain electrodes 232 and 234 are formed in the same process, and the common electrode 254 is formed using a contact hole filling method, thereby fabricating a four mask process. It is possible.

Hereinafter, a manufacturing method of an array substrate for an FFS liquid crystal display device according to the present invention will be described with reference to the process drawings.

11A to 23A, 11B to 23B, 11C to 23C, and 11D and 23D are cut along the lines VII-VII, VIII-VII, VIII-XI, VI-XI of FIG. It is process sectional drawing shown according to a process sequence.

11A to 11D are diagrams illustrating a first mask process, and as illustrated, a substrate 200 in which a switching region S, a pixel region P including the same, a gate region G, and a data region D are defined. ) Selected from the group of conductive metals including aluminum (Al), aluminum alloy (AlNd), tungsten (W), copper (Cu), molybdenum (Mo), chromium (Cr), molybdenum (MoW) and the like. By depositing and patterning, a gate line 202 is formed to extend in one direction corresponding to the gate region G and include a gate pad 206 at one end thereof.

At this time, a portion of the gate wiring 202 or an extension portion extending from the gate wiring 204 is used as the gate electrode 204.

Next, an inorganic insulating material group including silicon nitride (SiN _X ) and silicon oxide (SiO ₂ ) on the entire surface of the substrate 200 on which the gate wiring 202, the gate electrode 204, and the gate pad 206 are formed. One or more selected materials are deposited to form the gate insulating layer 208.

12 (a, b, c, d) to 16 (a, b, c, d) show a second mask process.

12A to 12D, an amorphous silicon layer 210, an ohmic contact layer 212, and a conductive metal layer 214 are stacked on the gate insulating layer 208.

Next, a photoresist is applied to the upper portion of the conductive metal layer 214 to form a photosensitive layer 216, and a transmissive portion B1 and a transflective layer B2 are disposed on the photosensitive layer 216. And a mask M composed of a blocking portion B3.

In this case, the cutoff portion B3 is disposed around the transflective portion B2 and the transflective portion B2 in correspondence with the upper portion of the switching region S, and the ultraviolet ray UV is formed at the upper portion of the mask M. ) Is irradiated to expose the lower photosensitive layer 216.

At this time, the portion corresponding to the blocking portion B3 is not exposed, the portion corresponding to the transflective portion B2 is partially exposed from the surface, and the portion corresponding to the transmissive portion B1 is completely exposed.

In the process of developing the photosensitive layer 216 in such a state, as shown in FIGS. 13A to 13D, the first photosensitive pattern 218a having a different height corresponding to the switching region S, and the data The second photosensitive pattern 218b remains in the region D.

As shown in FIGS. 14A to 14D, the metal layers exposed to the outside of the first and second photosensitive patterns 218a and 218b are removed to be disposed below the first and second photosensitive patterns 218a and 218b. The data line 222 including the data pad 224 is formed at one end of the first metal pattern 220 and extends in one direction from the first metal pattern.

Next, a process of removing the impurity amorphous silicon layer 212 and the pure amorphous silicon layer 210 exposed to the periphery of the metal layer 220, the data pad, and the data lines 224 and 222 is performed.

In this manner, a first pattern 226 is formed under the metal layer 220, and a second pattern 228 is formed under the data lines and the data pads 222 and 224.

As shown in FIGS. 15A to 15D, a process of ashing the first photosensitive pattern 218a and the second photosensitive pattern 218b is performed to perform a process of ashing the first photosensitive pattern 218a of the switching region. The process of exposing a portion of the lower metal layer 220 is performed by completely removing the low height portion.

In the ashing process, the periphery of the first metal layer 220, the data line 222, and the data pad 224 is exposed to the periphery of the first and second photosensitive patterns 218a and 218b.

Next, when the exposed metal layer 220 is etched, as shown in FIGS. 16A through 16D, the source electrode 232 and the drain electrode 234 spaced apart from each other corresponding to the switching region S may be formed. Form.

In this case, a process of exposing the lower amorphous silicon layer 210 is performed by removing the impurity amorphous silicon layer 212 exposed to the spaced lower portions of the source and drain electrodes 232 and 234.

In this process, the patterned impurity amorphous silicon layer under the source and drain electrodes 232 and 234 is called an ohmic contact layer 230b, and the patterned pure amorphous silicon layer under the ohmic contact layer 230b is an active layer 230a. It is called).

In the above-described process, the amorphous silicon layer 210 is exposed to the periphery of the first and second photosensitive patterns 218a and 218b.

Through the above-described second mask process, the active layer 230a, the ohmic contact layer 230b, the source and drain electrodes 232 and 234, the data lines and the data pads 222 and 224 may be formed.

17A to 17D are diagrams illustrating a third mask process. As shown in FIG. 17A to 17D, an indium tin tin layer may be formed on a front surface of a substrate 200 on which the source and drain electrodes 232 and 234, the data lines and the data pads 222 and 224 are formed. A first transparent electrode pattern 236 in contact with the drain electrode 234 is deposited by depositing one selected from a group of transparent conductive metals including oxide (ITO) and indium-ink-oxide (IZO) and patterning the same by using a third mask process. ), A second transparent electrode pattern 238a on the gate pad, and a third transparent electrode pattern 238b in contact with the data pad 222.

18 (a, b, c, d) to 24 (a, b, c, d) show a fourth mask process.

First, as shown in FIGS. 18A to 18D, a photoresist is formed on the entire surface of the substrate 00 on which the first transparent electrode patterns 236 and the second and third transparent electrode patterns 238a and 238b are formed. -resist is applied to form the photosensitive layer 240 and is patterned by a fourth mask process to expose the first transparent electrode pattern 236 corresponding to the pixel region P to form a plurality of first stripe shapes. A second etching hole 244 is formed to expose the etching hole 242 and the second transparent electrode pattern 238a on the gate pad 206.

In this case, although not shown, one end of the first etching hole 242 is formed over the common wiring 207 fabricated in the first mask process to expose the gate insulating layer 208.

A process of removing the first transparent electrode pattern 236 and the second transparent electrode pattern 238a of the lower portion exposed through the first and second etching holes 242 and 244 of the photosensitive layer 240 is performed.

This removal process is generally performed by a wet etching process.

In this case, as illustrated in FIGS. 19A to 19D, the first and second transparent electrode patterns 236 and 238a exposed through the etching holes 222 and 224 are removed, and at the bottom of the photosensitive layer 240. The portion located is also overetched into the photosensitive layer 240.

This is because the etchant penetrates to the lower part of the photosensitive layer while removing the exposed first and second transparent electrode patterns 136 and 138a.

Next, after removing the lower first and second transparent electrode patterns 236 and 238 exposed between the first and second etching holes 242 and 244 of the photosensitive layer 240, the first and second etching holes are removed. A process of etching the gate insulating layer 208 exposed through 242 and 244 is performed.

In this case, the common wiring 207 of FIG. 10 is exposed to a lower portion of one end of the plurality of first etching holes 242 that extend across the common wiring 207 of FIG. 10, and the lower portion of the second etching hole 244. A portion of the gate pad 206 is exposed.

Next, as shown in FIGS. 20A to 20D, indium tin oxide (ITO) is formed on the entire surface of the substrate 100 from which the gate insulating layer 208 exposed through the first and second etching holes 242 and 244 is removed. A transparent electrode layer 246 is formed by depositing one selected from a group of transparent conductive metals including and indium zinc oxide (IZO).

In this case, the transparent electrode layer 246 is deposited on the upper side and the etched side of the photosensitive layer 240, but the etching hole in the lower part in the state of being cut off from the over-etched portion of the lower photosensitive layer 240 This results in the formation at 242.

Next, a process of removing the photosensitive layer 240 is performed.

In this case, as illustrated in FIGS. 22A to 22D, the transparent electrode layer (or the transparent electrode layer 246) is removed in all regions except for the transparent electrode layers 246 remaining in the first and second etching holes 242 and 244 while the photosensitive layer 240 is removed. 246 is removed.

Accordingly, the transparent electrode layer 246 having a rod shape while contacting the drain electrode 234 on the gate insulating layer 208 functions as the pixel electrode 250, and corresponds to the pixel region P. FIG. The transparent electrode layer 246 remaining in the first etching hole 242 functions as the common electrode 252 in contact with the common wiring 207 of FIG. 10, and the second etching hole of the gate pad 206 The transparent electrode layer 246 left at 244 in contact with the gate pad 206 functions as a gate pad electrode 254, and the third transparent electrode pattern 238b in contact with the data pad 224 may have data. The pad electrode 256 serves as a function.

Next, as shown in FIGS. 22A to 22D, a benzocyclobutene (BCB) and an acrylic resin (resin) are formed on the entire surface of the substrate 200 on which the common electrode 252 and the pixel electrode 250 are formed. The protective layer 260 is formed by depositing one selected from the group of organic insulating materials including).

Next, the passivation layer 260 disposed on the gate pad and the data pad 206 and 224 may be removed by completing a liquid crystal panel, and then removing the passivation layer through a separate plasma etching method.

This will be described below with reference to FIG. 23.

FIG. 24 is a diagram illustrating a process of removing a passivation layer on the gate pad electrode and the data pad electrode.

As illustrated, the liquid crystal panel 400 is formed by bonding the array substrate 200 and the color filter substrate 300 prepared above.

Next, the upper color filter substrate 300 corresponding to the gate pad electrode 254 and the data pad electrode 256 is cut to expose a lower passivation layer (not shown).

Next, the protective layer (not shown) is removed by a plasma etching method using the plasma apparatus to expose the lower gate pad electrode 254 and the data pad electrode 256.

Accordingly, a separate mask process is not required to remove the protective layer (not shown) for exposing the gate and data pad electrodes 254 and 256.

Through the four-mask process as described above it can be produced an array substrate for the FFS liquid crystal display device according to the present invention.

When manufacturing the array substrate for the FFS type liquid crystal display device as described above has the following effects.

First, since the portion in which the pixel electrode and the common electrode overlap each other is eliminated, afterimages are not generated due to overlap between the electrodes, thereby achieving high quality.

Second, since the array substrate for the FFS type liquid crystal display device can be manufactured through the four mask process, the process time can be shortened through the process simplification, thereby improving the production yield.

Third, the process cost can be reduced by simplifying the process, thereby improving the competitiveness of the product.

Claims (10)

Defining a plurality of pixel regions comprising a switching region on the substrate; A first mask process step of forming a gate electrode extending in one direction, a common wiring spaced apart from the substrate, and a gate electrode corresponding to the switching region; Forming a gate insulating film on an entire surface of the substrate on which the gate wiring, the common wiring and the gate electrode are formed; A second mask process step of forming a semiconductor layer on the gate insulating film above the gate electrode, source and drain electrodes spaced apart on the semiconductor layer, and a data wire crossing the gate wire; A third mask process step of forming a first transparent electrode pattern positioned in the pixel region while being in contact with the drain electrode; A fourth mask process step of forming a first photosensitive layer on an entire surface of the substrate on which the first transparent electrode pattern is formed, and forming a plurality of rod-shaped etching holes corresponding to the pixel region; Removing the first transparent electrode layer and the gate insulating layer below the first transparent electrode layer exposed by the etching hole, wherein the first projection electrode layer is over-etched under the photosensitive layer; Forming a transparent electrode layer on an entire surface of the photosensitive layer including the plurality of etching holes; Removing the photosensitive layer to form a common electrode formed in the etching hole and a pixel electrode disposed on the gate insulating layer; Forming a passivation layer on an entire surface of the substrate on which the common electrode, the pixel electrode, and the source and drain electrodes are formed; Array substrate manufacturing method for a FFS liquid crystal display device comprising a. The method of claim 1, The second mask process step Stacking an amorphous silicon layer, an impurity amorphous silicon layer, and a conductive metal layer on the gate insulating film; Forming a photosensitive layer on top of the conductive metal layer, and placing a mask composed of a transmissive part, a blocking part, and a semi-transmissive part spaced apart from the photosensitive layer; Irradiating light from the upper portion of the mask to expose the lower photosensitive layer and developing the first photosensitive pattern having a different height corresponding to the switching region, and forming a second photosensitive pattern extending from the first photosensitive pattern. Steps; The conductive metal layer, the impurity amorphous silicon layer, and the pure amorphous silicon layer exposed to the periphery of the first and second photosensitive patterns are removed, thereby forming a data line connected to the metal layer corresponding to the gate electrode and intersecting the gate wiring. Forming; Ashing the first and second photosensitive patterns to completely remove a lower portion of the first photosensitive pattern to expose a lower conductive metal layer; Removing the exposed conductive metal layer and an impurity amorphous silicon layer below the source and drain electrodes, the source and drain electrodes spaced apart corresponding to the upper portion of the gate electrode, and the ohmic contact layer and the lower portion thereof. Forming an active layer of Array substrate manufacturing method for a FFS liquid crystal display device comprising a. The method of claim 1, And a transparent electrode layer on the surface of the photosensitive layer is removed at the same time in the process of removing the photosensitive layer. The method of claim 1, An array substrate manufacturing method for an FFS liquid crystal display device, wherein the transparent electrode layer is removed through a wet etching process. The method of claim 1, And forming a data pad at one end of the gate line and a data pad at one end of the data line. The method of claim 5, And forming a second transparent electrode pattern and a third transparent electrode pattern on the gate pad and the data pad while simultaneously forming the first transparent electrode pattern. The method of claim 6, And forming a transparent gate pad electrode in contact with the gate pad and a transparent data pad electrode (third transparent electrode pattern) in contact with the data pad while forming the common electrode. Array substrate manufacturing method. The method of claim 7, wherein Forming the gate pad electrode and the data pad electrode may include Stacking a photosensitive layer on top of the second and third transparent electrode patterns, etching the photosensitive layer and etching the second transparent electrode pattern and the gate insulating layer on a portion corresponding to the gate pad; Forming a transparent electrode layer on a surface of the photosensitive layer, an exposed side surface of the etched gate insulating layer, and the gate pad; Removing the photosensitive layer to form a gate pad electrode in contact with the gate pad and a data pad electrode (third transparent electrode pattern) in contact with the data pad Array substrate manufacturing method for a FFS liquid crystal display device comprising a. The method of claim 1, The pixel electrode and the common electrode is spaced apart by a maximum 1㎛ array substrate manufacturing method for an FFS type liquid crystal display device. The method of claim 1, Forming a liquid crystal panel by bonding the array substrate for the liquid crystal display and the separate color filter substrate; Cutting the color filter substrate in a portion corresponding to the gate pad electrode and the data pad electrode formed on the array substrate to expose a lower protective film; Removing the passivation layer using a plasma etching method to expose a lower gate pad electrode and a data pad electrode; FFS type liquid crystal display device manufacturing method comprising a.

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