KR20040085583A - An array substrate for In-Plane Switching mode LCD and method for fabricating of the same - Google Patents

Abstract

PURPOSE: An array substrate for an in-plane switching mode liquid crystal display, and a method for manufacturing the same are provided to improve an aperture ratio by forming transparent common and pixel electrodes, and improve a transmittance by removing a thick insulation film between the common and pixel electrodes, thereby realizing high brightness. CONSTITUTION: Gate lines(102) are extended on a substrate(100) in one direction. A first common line(106) and a second common line(108) are separated from each other in parallel on both sides of the gate lines. Data lines(120) vertically cross the gate lines for defining a pixel area. Thin film transistors(T) are placed at cross points of the gate lines and the data lines. The thin film transistor is formed of a gate electrode(104), a semiconductor layer, a source electrode(116), and a drain electrode(118) separated from the source electrode and includes an extended part extended over the second common line. A plurality of transparent pixel electrodes(134) are formed on the pixel area, contacting with the drain electrode. A plurality of common electrodes(136) are separated from the pixel electrodes in parallel, connected with the first common line.

Description

An array substrate for In-Plane Switching mode LCD and method for fabricating of the same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to an array substrate for an in-plane switching mode liquid crystal display device that realizes high aperture ratio and high image quality, and a manufacturing method thereof. It is about.

In general, the driving principle of the liquid crystal display device uses the optical anisotropy and polarization of the liquid crystal.

Since the liquid crystal is thin and long in structure, the liquid crystal has directivity in the arrangement of molecules, and the direction of the molecular arrangement can be controlled by artificially applying an electric field to the liquid crystal.

Accordingly, if the molecular arrangement direction of the liquid crystal is arbitrarily adjusted, the molecular arrangement of the liquid crystal is changed, and light is refracted in the molecular arrangement direction of the liquid crystal due to optical anisotropy to express image information.

Currently, an active matrix liquid crystal display device (AM-LCD: below Active Matrix LCD, abbreviated as liquid crystal display device) in which a thin film transistor and pixel electrodes connected to the thin film transistor are arranged in a matrix manner has the best resolution and video performance. It is attracting attention.

The liquid crystal display includes a color filter substrate (upper substrate) on which a common electrode is formed, an array substrate (lower substrate) on which a pixel electrode is formed, and a liquid crystal filled between the upper and lower substrates. And a method in which the liquid crystal is driven by an electric field applied up and down by the pixel electrode, and has excellent characteristics such as transmittance and aperture ratio.

However, the liquid crystal drive by the electric field applied up-down has a disadvantage that the viewing angle characteristics are not excellent. Therefore, new techniques have been proposed to overcome the above disadvantages. The liquid crystal display device to be described below has an advantage of excellent viewing angle characteristics by a liquid crystal driving method using a transverse electric field.

1 is a plan view schematically showing the configuration of an array substrate for a transverse electric field type liquid crystal display device according to a first conventional example.

As shown in the drawing, the gate wiring 14 is formed on one side of the substrate 10 and vertically intersects with the data wiring 30 to define the pixel region P. As shown in FIG.

The common wiring 16 is configured to be spaced apart in parallel with the gate wiring 14.

The thin film transistor T including the gate electrode 12, the active layer 22, the source electrode 26, and the drain electrode 28 is formed at the intersection of the gate line 14 and the data line 30. .

In the pixel region P, a plurality of common electrodes 18 vertically extending from the common wiring 16 and spaced apart from each other are disposed between the plurality of common electrodes 18 while being in contact with the drain electrode 28. A plurality of pixel electrodes 32 positioned at predetermined intervals are configured.

Although not represented, a passivation layer 34 is formed on the common electrode 18 and the pixel electrode 32, and an alignment layer (not shown) on which a surface is rubbed is formed on the passivation layer (not shown).

However, since the pixel electrode 32 and the common electrode 18 are formed on different layers, the surface of the array substrate described above causes severe stepping.

As such, when an alignment film (not shown) is applied to the surface of the substrate 10 having the step difference and rubbed, the rubbing defect is caused by the alignment film agglomeration in the step portion.

Since the initial alignment state is different from other regions, the liquid crystal positioned in the region in which rubbing defects occur cannot be normally arranged even under the same horizontal electric field as other regions of the pixel.

As a result, a disclination that appears brighter than the surrounding area or vice versa in the stepped portion may occur, resulting in non-uniformity of image quality.

Hereinafter, the process cross-sectional view of FIGS. 2A to 2D will be described in more detail.

2A to 2D are sectional views taken along the line II-II 'and III-III' of FIG. 1 and showing the process steps according to the first example of the related art. (II-II 'is a cutting line of the thin film transistor. And III-III` are cut lines between the common electrode and the pixel electrode.)

As shown in FIG. 2A, one selected from the group of conductive metals including aluminum (Al) and aluminum alloy (AlNd) is deposited on the substrate 10 to be connected to the gate electrode 12 and the gate electrode 12. And a gate wiring (FIG. 1 14) extending in one direction.

At the same time, the common wiring (16 in FIG. 1) spaced in parallel with the gate wiring (14 in FIG. 1) and extending in one direction, and the plurality of vertically extending and spaced apart from each other in the common wiring (16 in FIG. 1). The common electrode 18 of is formed.

As shown in FIG. 2B, an inorganic insulating material group including silicon nitride (SiN _x ), silicon oxide (SiO ₂ ), and the like on the entire surface of the substrate 10 on which the gate electrode 12 and the common electrode 18 are formed. One of them is deposited to form a gate insulating film 20.

Next, the active layer 22 and the ohmic contact layer 24 are stacked on the gate insulating layer 20 on the gate electrode 12.

In general, the active layer 22 is formed by depositing pure amorphous silicon (a-Si: H), and the ohmic contact layer 24 is deposited by impurity amorphous silicon (n + a-Si: H), The surface of the active layer 22 may be formed by doping impurity ions.

In the above-described configuration, the gate insulating film 20 is configured to be stepped to correspond to the side surface of the common electrode by the common electrode 18.

As shown in FIG. 2C, tungsten (W), chromium (Cr), copper (Cu), molybdenum (Mo), and the like are formed on the entire surface of the substrate 10 on which the active layer 22 and the ohmic contact layer 24 are formed. One selected from a group of conductive metals including titanium (Ti), tantalum (Ta), and the like is deposited and patterned to form a source electrode 26 and a drain electrode 28 to be spaced apart from each other by a predetermined distance.

At the same time, a data line (30 in FIG. 1) connected to the source electrode 26 and perpendicularly intersecting with the gate line (14 in FIG. 1) is formed and is in contact with the drain electrode 28 to form a pixel region ( A plurality of pixel electrodes 32 positioned at P) of FIG. 1 are formed.

The plurality of pixel electrodes 32 are configured to be spaced apart in parallel between the plurality of common electrodes 18.

As shown in FIG. 2D, a group of inorganic insulating materials including silicon nitride (SiN _x ) and silicon oxide (SiO ₂ ) on the entire surface of the substrate 10 on which the common electrode 18 and the pixel electrode 32 are formed. The protective film 34 is formed by the selected one.

In this case, since the passivation layer 34 is formed on both sides of the common electrode 18 and the pixel electrode 32, the passivation layer 34 is configured to have a step K corresponding to the side of each electrode.

Due to such a step, if not shown, when the alignment film is applied to the upper portion of the protective film 34 and the rubbing process is performed in one direction, the protective film 34 is located at each electrode 18 and 32 in the direction in which the rubbing means passes. Partially agglomerated in the stepped portion K of, thus rubbing defects occur in the stepped portion K.

Due to this rubbing failure, the foreground is generated in a portion corresponding to the common electrode 18 and the pixel electrode 32.

This problem is observed not only in the structure of the conventional first example described above, but also in the structure of the conventional second example described below.

3 is a cross-sectional view schematically showing the configuration of an array substrate for a transverse electric field type liquid crystal display device according to a second conventional example.

As shown in the figure, a gate electrode 52 patterned in a predetermined shape is first formed in the switching region S of the substrate 50 in which the switching region S and the pixel region P are defined.

The gate insulating film 54 is formed on the entire surface of the substrate 50 having the gate electrode 52.

The active layer 56 and the ohmic contact layer 58 are stacked on the gate insulating layer 54 on the gate electrode 52, and the source electrode 60 and the drain electrode spaced apart from each other by a predetermined interval on the ohmic contact layer 58. 62 is configured.

A protective film 64 exposing a part of the drain electrode 62 is formed on the entire surface of the substrate 50 including the source electrode 60 and the drain electrode 62.

The pixel region P includes a plurality of transparent pixel electrodes 66 in contact with the drain electrode 62, and a plurality of transparent common electrodes 68 spaced apart in parallel by a predetermined interval.

An alignment layer (not shown) is formed on the entire surface of the substrate 50 including the common electrode 68 and the pixel electrode 66.

The structure of the conventional second example configured as described above has the advantage that the aperture ratio is improved compared to the structure of the first example by forming the transparent conductive metal between the common electrode 66 and the pixel electrode 68.

In addition, in the structure of the conventional second example, since the common electrode 68 and the pixel electrode 66 are configured on the same plane, the step difference can be lowered as compared with the conventional first example.

That is, in the conventional first example, since the common electrode and the pixel electrode are formed in different layers, the height of the step is increased by the sum of the heights of the metal layers, but the conventional second example is the same as the common electrode. Since the pixel electrode is made of the same material as the same layer, a step may be lower than in the related art.

However, there is a problem that the foreground along the rubbing direction still occurs.

The present invention has been proposed for the purpose of solving the above-mentioned problems, and the pixel electrode and the common electrode are formed of a transparent metal on the same plane, but the two electrodes have a round shape in cross section.

In order to form the common electrode and the pixel electrode in a round shape, a round organic film pattern is formed under the two electrodes. In this case, the organic layer does not exist in the separation region of the two electrodes.

As described above, first, since the two electrodes are configured in a round shape, a phenomenon in which the alignment layers partially aggregate during the rubbing process does not occur.

Therefore, the foreground due to the abnormal arrangement of the liquid crystal does not occur.

Secondly, the common electrode and the pixel electrode may be configured to be transparent, and at the same time, the organic layer may not be present between the two electrodes, thereby achieving high opening ratio and high brightness.

1 is a plan view schematically showing one pixel of an array substrate for a transverse electric field type liquid crystal display device according to a first example of the related art;

2A to 2D are sectional views taken along the line II-II` and III-III` of FIG. 1 and shown according to a conventional process sequence.

3 is a cross-sectional view schematically showing one pixel of an array substrate for a transverse electric field type liquid crystal display device according to a second example of the prior art;

4 is a plan view schematically showing one pixel of an array substrate for a transverse electric field type liquid crystal display device according to the present invention;

FIG. 5 is a cross-sectional view taken along lines VV ′ and VIV of FIG. 4;

6A to 6H are cross-sectional views taken along the lines VV ′ and VIV of FIG. 4 and shown in the process sequence of the present invention.

<Brief description of the main parts of the drawing>

100: substrate 102: gate wiring

104: gate electrode 106: first common wiring

108: second common wiring 114: active layer

116: source electrode 118: drain electrode

120: data wiring 134: pixel electrode

136: common electrode

According to an aspect of the present invention, there is provided an array substrate for a liquid crystal display device comprising: a gate wiring extending in one direction on a substrate; A first common line and a second common line configured to be spaced apart in parallel with the gate line therebetween, and to receive the same signal; A data line defining a pixel area crossing the gate line perpendicularly; A thin film transistor disposed at an intersection point of the gate line and the data line, the thin film transistor comprising a gate electrode, a semiconductor layer, and a drain electrode including an extension part spaced apart from the source electrode and extending above the second common line; A plurality of transparent pixel electrodes configured on the pixel region while in contact with the drain electrode; A plurality of common electrodes configured to be spaced apart in parallel to the pixel electrode and connected to the first common wiring are included.

The semiconductor layer is formed by stacking an active layer of amorphous silicon (a-Si: H) and an ohmic contact layer of amorphous silicon (n + a-Si: H) containing impurities.

The common electrode and the pixel electrode may have a round cross section.

An insulating film is further formed between the first common wiring and the extension of the drain electrode to form the storage capacitor.

According to another aspect of the present invention, an array substrate for a transverse electric field type liquid crystal display device includes: a substrate in which a switching region and a pixel region are defined; A gate electrode configured to correspond to the switching region; A gate insulating film formed on the gate electrode; A semiconductor layer formed on the gate insulating film; A source electrode and a drain electrode spaced apart from each other above the semiconductor layer; A protective film formed over the source electrode and the drain electrode and exposing a part of the drain electrode; A plurality of insulating patterns positioned corresponding to the pixel areas and having a round cross section; A plurality of transparent pixel electrodes in contact with the drain electrode and configured to have a round shape along the insulating pattern; A plurality of common electrodes spaced apart in parallel to the pixel electrode and configured to have a round shape along the insulating pattern.

The pixel electrode and the common electrode having a round cross-section are bar-shaped in plan.

The insulating pattern may be configured to correspond to the pixel electrode and the common electrode.

According to an aspect of the present invention, there is provided a method of manufacturing an array substrate for a transverse electric field type liquid crystal display device, including forming a gate wiring extending in one direction, a gate electrode, and a first common wiring spaced in parallel with the gate wiring; ; Forming a gate insulating film on an entire surface of the substrate on which the gate wiring is formed; Forming a semiconductor layer on the gate insulating film; Forming a data line on the semiconductor layer, a drain electrode spaced apart from the source electrode, a data line connected to the drain electrode and vertically intersecting with the gate line to define a pixel region; Forming a passivation layer on a front surface of the substrate on which the source and drain electrodes are formed, exposing a portion of the drain electrode and a portion of the first common wiring; Forming a plurality of insulating patterns having a round cross section on the passivation layer corresponding to the pixel region; Forming a plurality of transparent pixel electrodes having a round shape along the insulating pattern while in contact with the drain electrode, and forming a plurality of transparent common electrodes having a round shape along the insulating pattern while in contact with the first common wiring. do.

The protective layer is formed of one selected from the group of inorganic insulating materials including silicon nitride (SiN _X ) and silicon oxide (SiO ₂ ), and the insulating pattern is formed of a photosensitive organic insulating material.

The method of manufacturing an array substrate for a transverse electric field type liquid crystal display device includes forming an organic insulating film by applying a photosensitive organic insulating material on the protective film; Positioning a mask including a plurality of transmissive portions and blocking portions alternately spaced apart from each other on the photosensitive organic layer; Irradiating light on the upper portion of the mask to expose the lower organic insulating layer and developing the organic insulating pattern, the organic layer pattern having a rectangular cross section; The method may further include forming heat into the organic film pattern having a round cross section by applying heat to the organic film pattern having a rectangular cross section.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

Example

The present invention is characterized in that the cross-sections of the common electrode and the pixel electrode are configured in a round shape.

4 is a plan view schematically showing the configuration of an array substrate for a transverse electric field type liquid crystal display device.

4 is only one example for explaining a cross-sectional structure of the common electrode and the pixel electrode according to the present invention, and the configuration of the common electrode and the pixel electrode and the configuration of the auxiliary capacitor may be modified in various shapes.

As shown in the drawing, a gate line 102 extending in one direction is formed on the substrate 100, and a data line 120 is formed to cross the gate line 102 to define the pixel region P. As shown in FIG. do.

The first common wiring 106 and the second common wiring 108 spaced apart in parallel with the gate wiring 102 and extending in one direction and spaced apart in parallel with the gate wiring 102 interposed therebetween.

The thin film transistor T including the gate electrode 104, the active layer 112, the source electrode 116, and the drain electrode 118 is formed at the intersection of the two wires 106 and 108.

In the pixel region P, a plurality of pixel electrodes 134 contacting the drain electrode 118 are formed to be spaced apart from each other in parallel, connected to the first common wire 106, and the plurality of pixel electrodes 134. A plurality of common electrodes 132 are configured to be positioned in parallel with each other.

In this case, the drain electrode 118 extends above the second common wiring 108 to form the storage capacitor C _ST together with the common wiring 108.

In other words, a portion of the first common wiring 108 becomes a storage first electrode, and an extension A of the drain electrode 118 overlapping the storage electrode becomes a storage second electrode.

In this case, although not expressed in plan, the common electrode 132 and the pixel electrode 134 have a round shape (semi-circular shape) in cross section.

Hereinafter, the planar configuration of FIG. 4 will be described with reference to FIG. 5.

As shown in FIG. 5, a gate electrode patterned first in a predetermined shape in the switching region S of the substrate 100 in which the switching region S, the pixel region P, and the storage capacitor C _ST are defined. A storage first electrode (part of the second common wiring in the configuration of FIG. 4) 108 is formed in the 104 and the storage capacitor region C. FIG.

The gate insulating layer 110 is formed on the entire surface of the substrate 100 including the gate electrode 104 and the storage first electrode 108.

The active layer 112 and the ohmic contact layer 114 are formed on the gate insulating layer 110 on the gate electrode 104, and the source and drain electrodes 116 and the drain electrode spaced apart from each other by a predetermined interval on the ohmic contact layer 114. Constitute 118.

In this case, the drain electrode 118 includes an extension A extending above the storage first electrode 108, which functions as a storage second electrode.

The passivation layer 122 exposing a part of the drain electrode 118 is formed on the entire surface of the substrate 100 including the source electrode 116 and the drain electrode 118.

A plurality of organic film patterns 128 having a round shape (semi-circular shape) are spaced apart from each other at predetermined intervals on the passivation film 122 corresponding to the pixel region P.

In the pixel region P, a plurality of transparent pixel electrodes 134 formed on the organic layer pattern 128 are formed in contact with the drain electrode 118, and are spaced apart by a predetermined interval in parallel to the organic layer. A plurality of transparent common electrodes 136 is formed on the pattern 128.

The pixel electrode 134 and the common electrode 136 may each be formed in a round shape by the plurality of round organic layer patterns 128.

Therefore, since the common electrode 136 and the pixel electrode 134 have a round shape as described above, during the process of applying and rubbing the alignment layer in a subsequent process, the rubbing means (not shown) is the two electrodes 134. , 136) can pass flexibly along the round shape, so that rubbing defects in which the alignment layer is agglomerated in the stepped portion at right angles as in the prior art do not occur.

Hereinafter, a manufacturing process of an array substrate for a transverse electric field type liquid crystal display device according to the present invention will be described with reference to FIGS. 6A to 6H.

6A to 6H are cross-sectional views taken along the line VV ′ and VIV of FIG. 4, and according to the process sequence of the present invention.

First, as shown in FIG. 6A, one or two metals selected from conductive metal groups including aluminum (Al) and aluminum alloy (AlNd) are deposited on the substrate 100 to form a single layer or a double metal layer. By patterning, the gate wiring 102 in FIG. 1 and the gate electrode 104 connected thereto are formed.

At the same time, the first common wiring 106 and the second common wiring 108 spaced apart in parallel by predetermined intervals with the gate wiring 102 in between are formed. In this case, the first common wiring 106 and the second common wiring 108 may be connected to each other to receive the same signal from one input terminal, or in some cases, may be configured to receive the same signal separately.

As shown in FIG. 6B, silicon nitride (SiN _X ) and silicon oxide (SiO ₂ ) are formed on the entire surface of the substrate 100 on which the first and second common wirings 106 and 108 and the gate electrode 104 are formed. The gate insulating layer 110 is formed by depositing one selected from the group of inorganic insulating materials or by applying one selected from the group of organic insulating materials including benzocyclobutene (BCB) and an acrylic resin.

In this case, in some cases, the inorganic insulating material and the organic insulating material may be stacked.

Next, an active layer 112 and an ohmic contact layer 114 are formed on the gate insulating layer 110 on the gate electrode 104.

The active layer 112 is generally formed by depositing pure amorphous silicon (a-Si: H), and the ohmic contact layer 114 deposits amorphous silicon (n + a-Si: H) containing impurities or the The surface of the active layer 112 may be formed by doping impurity ions.

As shown in FIG. 6C, antimony (Sb), chromium (Cr), tungsten (W), molybdenum (Mo), titanium (Ti), and copper are formed on the entire surface of the substrate 100 on which the ohmic contact layer 114 is formed. One selected from the group of conductive metals including Cu and the like is deposited and patterned to form source and drain electrodes 116 and 118 spaced apart on the ohmic contact layer 114.

At the same time, a data line 120 connected to the source electrode 116 and perpendicularly intersecting with the gate line 102 of FIG. 4 to define the pixel region P is formed.

In this case, the drain electrode 118 includes an extension portion A extending above the second common wiring 108.

With the above-described configuration, an auxiliary capacitor C _ST having the second common wiring 108 as the storage first electrode and the extension A of the drain electrode 118 as the storage second electrode may be formed. Can be.

After the above-described process, the ohmic contact layer 114 exposed to the spaced apart regions of the source and drain electrodes 116 and 118 is removed to expose the lower active layer 112.

As shown in FIG. 6D, one selected from the group of inorganic insulating materials including silicon nitride (SiN _x ) and silicon oxide (SiO ₂ ) is deposited on the entire surface of the substrate 100 on which the source and drain electrodes 116 and 118 are formed. The protective film 122 is formed.

Next, a photosensitive organic insulating material is coated on the passivation layer 122 to form a thick organic insulating layer 124. (At this time, it is assumed that the photosensitive organic insulating layer is a positive type.)

At this time, the protective film 122 is configured to preserve the characteristics of the thin film transistor.

In this regard, since the active layer 112 formed of amorphous silicon has poor interface characteristics with the organic film, a trap level capable of trapping electrons at the interface is generated.

As a result, an operation characteristic of the thin film transistor T is lowered. In order to prevent this, an inorganic film (the protective film) having good interface characteristics with the active layer 112 is used.

As shown in FIG. 6E, a mask 200 having a plurality of transmissive portions D and blocking portions E is alternately positioned on the photosensitive organic insulating layer 124.

Subsequently, light is irradiated to an upper portion of the mask 200 to expose a lower photosensitive organic insulating layer 124.

Next, when the process of developing the photosensitive organic insulating film 124 is progressed, as shown in FIG. 6F, the cross section is rectangular in cross section at a portion corresponding to the blocking portion E of the mask (M in FIG. 6E). The organic film pattern 126 is formed.

Next, a process of applying heat to the rectangular organic film pattern 126 is performed.

As shown in FIG. 6G, when the heat applying step is performed, the organic film pattern 128 having a round (semi-circular) shape in cross section is obtained.

In this case, the organic film pattern having a round shape (semi-circular shape) is composed of a plurality of bar shapes spaced apart from each other by a predetermined distance in plan view, and the lower passivation film 122 is exposed to the spaced area of the organic insulating film pattern.

The exposed protective layer 122 is etched to expose the first contact hole 130 exposing the extension portion A of the drain electrode 118 and the second contact exposing a part of the first common wiring 106. The hole 132 is formed.

In this case, during the process of forming the first and second contact holes 130 and 132, the passivation layer 122 and the gate insulating layer 110 below the protective layer 122 are formed in a region corresponding to the separation distance L of the organic layer pattern 128. The removal may be performed to expose the substrate 100.

The contact holes 130 and 132 may be formed before forming the organic layer pattern 128.

As illustrated in FIG. 6H, a selected one of a transparent conductive metal group including indium tin oxide (ITO) and indium zinc oxide (IZO) is deposited on the entire surface of the substrate on which the organic layer pattern 128 is formed. And a plurality of pixel electrodes 134 contacting the exposed drain electrode 118 and the pixel electrodes 134 while being in contact with the exposed first common wiring 106 and spaced apart in parallel. A plurality of common electrodes 136 are formed.

In this case, the common electrode 136 and the pixel electrode 134 may be formed in a round shape by the round organic film pattern 128 formed below.

As described above, when the common electrode 135 and the pixel electrode 134 are formed in a round shape, the rubbing means may easily cross the round shape of the two electrodes during the process of applying and rubbing an alignment layer (not shown). Therefore, the phenomenon of aggregation of the alignment layers does not occur.

Therefore, the disclination does not occur due to poor rubbing.

In addition, the above-described process may be formed in a structure in which the insulating layer does not exist in correspondence to the separation region between the common electrode and the pixel electrode, thereby improving the transmittance and thus, achieving high brightness.

Therefore, the array substrate for a transverse electric field type liquid crystal display device according to the present invention has the following effects.

First, since the common electrode and the pixel electrode are both formed as transparent electrodes, the aperture ratio is improved as compared with the related art.

Second, since the pixel electrode and the common electrode are formed to be bent in a round shape, rubbing defects do not occur, and thus, the occurrence of foreground can be prevented, thereby improving contrast and realizing high image quality.

Third, since a thick insulating film does not exist in a portion corresponding to the separation area between the common electrode and the pixel electrode, the transmittance is improved, thereby achieving high luminance.

Claims (15)

A gate wiring extending in one direction on the substrate; A first common line and a second common line configured to be spaced apart in parallel with the gate line therebetween, and to receive the same signal; A data line defining a pixel area crossing the gate line perpendicularly; A thin film transistor disposed at an intersection point of the gate line and the data line, the thin film transistor comprising a gate electrode, a semiconductor layer, and a drain electrode including an extension part spaced apart from the source electrode and extending above the second common line; A plurality of transparent pixel electrodes configured on the pixel region while in contact with the drain electrode; A plurality of common electrodes configured to be spaced apart from and parallel to the pixel electrode and connected to the first common wiring Array substrate for a transverse electric field type liquid crystal display device comprising a. The method of claim 1, The semiconductor layer is an array substrate for a transverse electric field type liquid crystal display device formed by stacking an active layer of amorphous silicon (a-Si: H) and an ohmic contact layer of amorphous silicon (n + a-Si: H) containing impurities. . The method of claim 1, And the common electrode and the pixel electrode have a round cross section. The method of claim 1, And an insulating film is further formed between the first common wiring and an extension of the drain electrode to form an auxiliary capacitor. A substrate in which a switching region and a pixel region are defined; A gate electrode configured to correspond to the switching region; A gate insulating film formed on the gate electrode; A semiconductor layer formed on the gate insulating film; A source electrode and a drain electrode spaced apart from each other above the semiconductor layer; A protective film formed over the source electrode and the drain electrode and exposing a part of the drain electrode; A plurality of insulating patterns positioned corresponding to the pixel areas and having a round cross section; A plurality of transparent pixel electrodes in contact with the drain electrode and configured to have a round shape along the insulating pattern; A plurality of common electrodes spaced apart in parallel to the pixel electrode and configured to have a round shape along the insulating pattern; Array substrate for a transverse electric field type liquid crystal display device comprising a. The method of claim 5, wherein The semiconductor layer is an array substrate for a transverse electric field type liquid crystal display device formed by stacking an active layer of amorphous silicon (a-Si: H) and an ohmic contact layer of amorphous silicon (n + a-Si: H) containing impurities. . The method of claim 5, wherein And the insulating pattern corresponds to the pixel electrode and the common electrode. Forming a gate wiring extending in one direction, a gate electrode, and a first common wiring spaced in parallel with the gate wiring on the substrate; Forming a gate insulating film on an entire surface of the substrate on which the gate wiring is formed; Forming a semiconductor layer on the gate insulating film; Forming a data line on the semiconductor layer, a drain electrode spaced apart from the source electrode, a data line connected to the drain electrode and vertically intersecting with the gate line to define a pixel region; Forming a protective film on a front surface of the substrate on which the source and drain electrodes are formed, exposing a portion of the drain electrode and a portion of the first common wiring; Forming a plurality of insulating patterns having a round cross section on the passivation layer corresponding to the pixel region; Forming a plurality of transparent pixel electrodes having a round shape along the insulating pattern while being in contact with the drain electrode, and forming a plurality of transparent common electrodes having a round shape along the insulating pattern while being in contact with the first common wiring. Array substrate manufacturing method for a transverse electric field type liquid crystal display device comprising. The method of claim 8, The semiconductor layer is a transverse electric field liquid crystal display device formed by stacking an active layer formed of amorphous silicon (a-Si: H) and an ohmic contact layer formed of amorphous silicon (n + a-Si: H) containing impurities. Array substrate manufacturing method. The method of claim 8, And the protective layer is formed of one selected from the group of inorganic insulating materials including silicon nitride (SiN _X ) and silicon oxide (SiO ₂ ). The method of claim 8, And the insulating pattern is formed of a photosensitive organic insulating material. The method of claim 8, And wherein the transparent common electrode and the transparent pixel electrode are formed of one selected from a group of transparent conductive metal materials including indium tin oxide (ITO) and indium zinc oxide (IZO). The method of claim 8, Forming the plurality of insulating patterns Forming an organic insulating layer on the passivation layer; Placing a mask comprising a plurality of transmissive portions and blocking portions alternately spaced apart from each other on the organic insulating layer; Irradiating light on the upper portion of the mask to expose the lower organic insulating layer and developing the organic insulating pattern, the organic layer pattern having a rectangular cross section; And applying heat to the organic film pattern having a rectangular cross section, thereby forming an organic film pattern having a round cross section. The method of claim 8, And forming a second common line spaced apart from and parallel to the gate line. The method of claim 14, And the drain electrode further includes an extension part extending above the second common wiring.