KR20060097235A - The manufacturing method of light emission display - Google Patents

Abstract

The present invention relates to a method of manufacturing a light emitting display device.

A method of manufacturing a light emitting display device includes forming a semiconductor layer on a substrate, forming a gate insulating film on the semiconductor layer, and using a mask to mask a first region of the semiconductor layer on the gate insulating film. Forming a region, depositing a metal layer on the gate insulating layer, and then forming a gate electrode, and using a gate electrode as a mask, a second region between the first doped region and the channel region of the semiconductor layer. And forming a second doped region, and then forming a second doped region, and then using a mask that covers a second region other than the first region on the gate electrode and the gate insulating film. Forming a third doped region, which is a doped region, forming at least one interlayer insulating film on the gate electrode, and then forming the gate Forming a plurality of contact holes through the insulating layer and the interlayer insulating layer to expose the first and third doped regions, and electrically contacting the first and third doped regions on the interlayer insulating layer. Forming a first electrode of the light emitting device and a source and drain electrode of the light emitting device; and an opening at least partially exposing the first electrode of the light emitting device on the source and drain electrodes and the first electrode of the light emitting device. Forming a positive layer.

Accordingly, not only the number of processes required for the manufacturing process of the light emitting display device can be reduced, but also cost reduction and productivity can be improved due to the reduction of the number of processes.

Description

Manufacturing Method of Light Emission Display

1 is a block diagram illustrating a manufacturing process of a conventional light emitting display device.

2A through 2L are cross-sectional side views of the light emitting display device of FIG.

3 is a block diagram illustrating a manufacturing process of a light emitting display device according to an exemplary embodiment of the present invention.

4A through 4J are cross-sectional side views of a light emitting display device according to the manufacturing process of FIG. 3.

♣ Reference numerals for main components ♣

401: substrate 402: buffer layer

403: semiconductor layer 404: gate insulating film

405: thin film transistor 406: first interlayer insulating film

407: Second interlayer insulating film 408: Contact hole

409: Light emitting element 410: First electrode

411: light emitting layer 412: second electrode

413: Pixel Definition Film

The present invention relates to a method of manufacturing a light emitting display device, and more particularly, to a method of manufacturing a light emitting display device which can improve productivity by reducing process steps.

Recently, various flat panel display devices having a lighter weight and a smaller volume than a cathode ray tube have been developed. In particular, a light emitting display device having excellent luminous efficiency, brightness, viewing angle, and fast response speed has been attracting attention.

Hereinafter, a manufacturing process of a conventional light emitting display device will be described in detail with reference to the accompanying drawings. 1 is a block diagram illustrating a manufacturing process of a conventional light emitting display device, and FIGS. 2A to 2L are side cross-sectional views of stages of forming the light emitting display device of FIG. 1.

1 and 2A to 2L, in order to manufacture the conventional light emitting display device 200, a substrate 201 is first prepared (P1).

After the substrate 201 is prepared, a buffer layer is formed on the substrate 201. The buffer layer may be formed of a single layer or a plurality of layers as an optional component, and may use a nitride film or an oxide film. The light emitting display device 200 illustrated in FIGS. 2A to 2L includes a first buffer layer 202 formed of a nitride film and a second buffer layer 203 formed of an oxide film. An amorphous silicon layer (a-si) is formed on the second buffer layer 203, and the formed amorphous silicon layer is crystallized by a laser or the like. When the amorphous silicon layer is crystallized, the crystallized amorphous silicon layer is patterned to form the semiconductor layer 204 (see P2, FIG. 2 (a)).

After the semiconductor layer 204 is formed, a gate insulating film 205 is formed on the semiconductor layer 204. After the gate insulating layer 205 is formed, the semiconductor layer 204 is doped by using a mask 220 that covers one region (first region) of the semiconductor layer 204 on the gate insulating layer 205. A doped region 204b is formed (see P3, Fig. 2 (b)). In this embodiment, an n-type dopant n + is implanted to form the first doped region 204b. When the first doped region 204b is formed, the mask 220 is removed.

Next, a metal layer (not shown) is formed on the gate insulating film 205, and the gate electrode 206a is formed on the gate insulating film 205 by patterning the formed metal layer (see P4 and FIG. 2C). After the gate electrode 206a is formed, the second doped region 204c is formed in the semiconductor layer 204 using the gate electrode 206a as a mask. The second doped region 204c is a lightly doped drain (LDD) doped region formed between the first doped region 204b and the channel region 204a of the semiconductor layer 204 (see P5, FIG. 2 (d)). .

Next, the third doped region 204d is formed on the gate electrode 206a by using a mask 225 covering the region other than the first region, that is, the second region (P6, FIG. 2E). )Reference). In this embodiment, the p-type dopant p + is implanted to form the third doped region 204d. When the third doped region 204d is formed, the mask 225 is removed. After the mask 225 is removed, a first interlayer insulating film 207 is formed on the gate electrode 206a (see P7, FIG. 2 (f)). Next, the first interlayer insulating layer 207 includes a plurality of first contact holes 208 penetrating through the first interlayer insulating layer 207 and exposing source and drain regions which are first and third doped regions 204b and 204d. (P8, see FIG. 2 (g)).

After the first contact hole 208 is formed, the source and drain electrodes 206b of the thin film transistor 206 electrically connected to the first and third doped regions 204b and 204d through the first contact hole 208. (P9, see FIG. 2 (h)). After the source and drain electrodes 206b are formed, a second interlayer insulating film 209 is formed on the source and drain electrodes 206b (P10), and then a first via hole 210 is formed on the second interlayer insulating film 207. (P11, see FIG. 2 (i)). Next, a passivation layer 211 is formed on the second interlayer insulating layer 209 (P12), and a second via hole 212 penetrating the passivation layer 211 is formed to be connected to the first via hole 210 using a mask. (See P13, Fig. 2 (j)).

In the next step, the first electrode 214 (anode electrode) of the light emitting element 213 is brought into electrical contact with one of the first via hole 210 and the second via hole 212 and one of the source and drain electrodes 206b. It is formed (see P14, Fig. 2 (k)). The first electrode 214 of the light emitting element 213 includes an ITO electrode layer 214a, a reflective conductive layer 214b formed of a reflective metal (eg, Ag, Al, etc.), and an ITO electrode layer 214c. It may consist of multiple layers. After the first electrode 214 is formed, a pixel definition layer 217 having an opening 217a exposing the light emitting layer 215 is formed on the first electrode 214 (see P15 and FIG. 2 (l)). Although not disclosed in the process step of FIG. 1, after the pixel definition layer 217 is formed, the emission layer 215 of the light emitting element 213 and the second electrode 216 (cathode electrode) are sequentially formed on the pixel definition layer 217. The process of forming is carried out.

However, when the light emitting display device is manufactured using the above-described conventional manufacturing process, a large number of process steps are required, and the number of processes increases by using a separate mask for each step. In addition, when a separate mask is used for each step, the cleaning process, the etching process, and the strip process must be added in each step, so that similar and similar processes are repeated, and the work is cumbersome. As a result, the number of operations increases according to unnecessary processes, thereby increasing manufacturing costs and lowering productivity.

Accordingly, the present invention is directed to a method for manufacturing a light emitting display device which can reduce the number of masks used in the manufacturing process, reduce unnecessary work, and improve productivity.

In order to achieve the above object, according to an aspect of the present invention, the method of manufacturing a light emitting display device comprises the steps of forming a semiconductor layer on a substrate, forming a gate insulating film on the semiconductor layer, Forming a first doped region by using a mask covering the first region of the semiconductor layer, depositing a metal layer on the gate insulating layer, and then forming a gate electrode, using the gate electrode as a mask Forming a second doped region between the first doped region and the channel region of the semiconductor layer, forming the second doped region, and then forming a region other than the first region on the gate electrode and the gate insulating layer. Forming a third doped region which is a doped region different from the first doped region by using a mask covering the second region, and before the gate Forming at least one interlayer insulating film thereon, and forming a plurality of contact holes through the gate insulating film and the interlayer insulating film to expose the first and third doped regions; Forming a first electrode of the light emitting device and a source and drain electrode in electrical contact with a first doped region and the third doped region, and the light emitting device on the source and drain electrodes and the first electrode of the light emitting device. Forming a pixel definition layer having an opening at least partially exposing the first electrode of the substrate.

Preferably, the source and drain electrodes are formed together with the first electrode of the light emitting device by using the same material as the first electrode of the light emitting device. The first electrode of the light emitting device has a multilayer structure including a reflective conductive layer formed of a reflective material.

The contact hole is formed by simultaneously etching the gate insulating film and the interlayer insulating film.

The interlayer dielectric layer includes a first interlayer dielectric layer formed on the gate electrode, and a second interlayer dielectric layer formed to have a flat top surface on the first interlayer dielectric layer. The interlayer insulating film includes at least one of silicon, benzocyclobutene (BCB), acryl, and polyimide.

The light emitting layer and the second electrode of the light emitting device are formed on the pixel defining layer and the first electrode of the light emitting device.

More preferably, the step of forming the semiconductor layer, forming a buffer layer on the substrate, applying an amorphous silicon layer on the buffer layer, crystallizing the amorphous silicon layer and the crystallized silicon layer Patterning further using a mask.

In the forming of the first doped region, n-type doping is performed, and in the forming of the third doped region, p-type doping is performed. The second doped region is a lightly doped drain (LDD) doped region.

Hereinafter, a manufacturing process of a light emitting display device according to the present invention will be described in detail with reference to the drawings showing an embodiment of the present invention.

3 is a block diagram illustrating a manufacturing process of a light emitting display device according to an exemplary embodiment of the present invention. Referring to FIG. 3, in the manufacturing process of the light emitting display device 400, a semiconductor layer is formed on a substrate (S2), a gate insulating layer is formed on the semiconductor layer, and a first doped region is formed (S3). Forming a gate electrode on the gate insulating film (S4), forming a second doped region using the gate electrode (S5), and forming a third doped region on the gate electrode and the gate insulating film in a region other than the first doped region. (S6), forming an interlayer insulating film on the gate electrode (S7), forming a plurality of contact holes in the interlayer insulating film (S8), forming source and drain electrodes and the first electrode of the light emitting device. And forming a predetermined film (S10).

Hereinafter, the manufacturing process of the light emitting display device according to the present exemplary embodiment will be described in detail with reference to FIG. 4, which is a side cross-sectional view of forming the light emitting display device according to the manufacturing process of FIG. 3.

In order to manufacture the light emitting display device 400 according to an embodiment of the present invention, first, a substrate 401 is prepared (S1). When the substrate 401 is prepared in step S1, the buffer layer 402 is formed on the substrate 401. The buffer layer 402 is an optional component and is formed of a nitride film, an oxide film, or the like. In this embodiment, the buffer layer 402 includes a first buffer layer 402a composed of a nitride film and a second buffer layer 402b composed of an oxide film. Then, an amorphous silicon layer (armorphous si) is deposited on the second buffer layer 402b, and the deposited amorphous silicon layer is crystallized by an excimer laser method or the like. When the amorphous silicon layer is crystallized, the semiconductor layer 403 is formed using a mask (S2, see Fig. 4A).

After the semiconductor layer 403 is formed, a gate insulating film 404 is formed on the semiconductor layer 403. After the gate insulating layer 404 is formed, a mask 420 is formed on the gate insulating layer 404 to cover a partial region (first region) of the semiconductor layer 403, and the semiconductor layer 403 is formed using the mask 420. By doping the region, the first doped region 403b is formed (see S3, Fig. 4B). In this embodiment, to form the first doped region 403b, an n-type dopant (n +) is implanted. When the first doped region 403b is formed, the mask 420 is removed.

 Next, a metal layer (not shown) is formed on the gate insulating film 404, and the gate electrode 405a is formed by patterning the metal layer formed on the gate insulating film 404 (S4, FIG. 4C). In the next step, the second doped region 403c, which is another doped region, is formed in the semiconductor layer 403 using the gate electrode 405a as a mask. The second doped region 403c is a region formed between the first doped region 403b and the channel region 403a of the semiconductor layer 403 and is a lightly doped drain (LDD) doped region (S5, FIG. 4 (d)). Reference).

 Next, the third doped region 403d is formed on the gate electrode 405a and the gate insulating film 404 by using a mask 425 that covers a region other than the first region, that is, the second region (see FIG. S6, see FIG. 4 (e)). In this embodiment, the p-type dopant p + is implanted to form the third doped region 403d. When the third doped region 403d is formed, the mask 425 is removed. After the mask 425 is removed, a first interlayer insulating film 406 and a second interlayer insulating film 407 are formed on the gate electrode 405a (see S7, Figs. 4F and 4G). The first and second interlayer insulating films 406 and 407 include at least one of silicon, benzocyclobutene (BCB), acrylic, and polyimide. In the present embodiment, the first interlayer insulating film 406 is formed of SiN, The second interlayer insulating film 407 is formed using an acrylic organic film.

Next, a plurality of contact holes 408 are formed in the first and second interlayer insulating films 406 and 404 and the gate insulating film 404 to expose the source and drain regions, which are the first and third doped regions 403b and 403d, respectively. (S8, see FIG. 4 (h)). In this case, the contact hole 408 may be formed at a time by simultaneously etching the gate insulating film 404 and the first and second interlayer insulating films 406 and 407.

After the contact hole 408 is formed, the source and drain electrodes 405b of the thin film transistor 405 and the first electrode (anode electrode 410) of the light emitting device 409 are formed. Specifically, they are formed to be electrically connected to the first and third doped regions 403b and 403d on the second interlayer insulating film 407. In this case, the source and drain electrodes 405b and the first electrode 410 of the light emitting device 409 are simultaneously formed using the same material. The first electrode 410 is a multilayer including an ITO electrode layer 410a having transparency, a reflective conductive layer 410b made of a reflective metal (eg, Ag, Al, etc.), and an ITO electrode layer 410c. Can be done. Accordingly, when the first electrode 410 is formed of multiple layers, the source and drain electrodes 405b are also formed of multiple layers (see S9 and FIG. 4 (i)).

After the first electrode 410 is formed, a pixel definition layer 413 having an opening 413a exposing the light emitting layer 411 of the light emitting element 409 is formed on the first electrode 410 (S10 and FIG. 4). (j) See). Although not specifically disclosed in the block diagram illustrating the manufacturing process of FIG. 3, the process of forming the light emitting layer 411 of the light emitting element 409 and the second electrode (2) may be performed after the pixel definition film 413 is formed. 412 is followed by a process of forming a cathode electrode.

As shown in the manufacturing process according to the present invention, since the source and drain electrodes 405b and the first electrode 410 of the light emitting device 409 are formed of the same material and are formed at the same time, the number of masks can be reduced. In addition, a contact hole 408 connecting the first and third doped regions 403b and 403d and the source and drain electrodes 405b and the first electrode 410 and the first and third doped regions 403b of the light emitting device. , The contact holes 408 for electrically connecting the 403d can be simultaneously formed, so that the number of masks can be significantly reduced.

In the above-described embodiment, the n-type doping is performed first and the p-type doping is performed. However, the order of these processes can be changed.

Although the technical spirit of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, the number of steps can be significantly reduced by using a significantly smaller number of masks than the number of masks used in the manufacturing process of the light emitting display device. In addition, since the number of masks is reduced, the detailed processes (e.g., cleaning, etching, strip, etc.) used in each mask step can also be reduced. As a result, the number of steps can be significantly reduced, which can reduce the cost and significantly improve the productivity.

Claims (11)

Forming a semiconductor layer on the substrate, Forming a gate insulating layer on the semiconductor layer, and forming a first doped region on the gate insulating layer using a mask covering a first region of the semiconductor layer; Depositing a metal layer on the gate insulating film, and then forming a gate electrode; Forming a second doped region between the first doped region and the channel region of the semiconductor layer using the gate electrode as a mask; After the second doped region is formed, a third doped region, which is a different doped region from the first doped region, is formed by using a mask covering the second region, which is a region other than the first region, on the gate electrode and the gate insulating layer. Forming step, Forming at least one interlayer insulating film on the gate electrode, and then forming a plurality of contact holes through the gate insulating film and the interlayer insulating film to expose the first and third doped regions; Forming a source and a drain electrode and a first electrode of the light emitting device in electrical contact with the first doped region and the third doped region on the interlayer insulating film; Forming a pixel definition layer on the source and drain electrodes and the first electrode of the light emitting device, the opening having at least partially exposing the first electrode of the light emitting device; Method of manufacturing a light emitting display device comprising a.  The method of claim 1, And the source and drain electrodes are formed together with the first electrode of the light emitting element by using the same material as the first electrode of the light emitting element. The method of claim 2, The first electrode of the light emitting device has a multilayer structure including a reflective conductive layer formed of a reflective material. The method of claim 1, And the contact hole is formed by simultaneously etching the gate insulating film and the interlayer insulating film. The method of claim 4, wherein The interlayer dielectric layer includes a first interlayer dielectric layer formed on the gate electrode and a second interlayer dielectric layer formed on the first interlayer dielectric layer to have a flat upper surface. The method of claim 5, The interlayer insulating layer may include at least one of silicon, benzocyclobutene (BCB), acryl, and polyimide. The method of claim 1, And a light emitting layer and a second electrode of the light emitting device are formed on the pixel defining layer and the first electrode of the light emitting device. The method of claim 1, Forming the semiconductor layer, Forming a buffer layer on the substrate, applying an amorphous silicon layer on the buffer layer, crystallizing the amorphous silicon layer, and patterning the crystallized silicon layer using a mask. Method of manufacturing the device. The method of claim 1, And forming the first doped region to perform n-type doping. The method of claim 1, And forming a third doped region to perform p type doping. The method of claim 1, The second doped region is a lightly doped drain (LDD) doped region.

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