KR20060095339A - Timing recovery apparatus and its method in digital broadcasting receiver - Google Patents

Abstract

The present invention relates to an apparatus and method for symbol timing recovery in a digital broadcast receiver for receiving and demodulating a signal modulated and transmitted in a VSB scheme. In particular, the present invention enables reconstruction of the overall demodulator structure by extracting only symbol timing information from an input signal even when the carrier frequency offset is not completely removed. In this case, the timing recovery apparatus operates regardless of the carrier phase, thereby recovering the existing carrier recovery. Acquisition and tracking is superior to most symbol timing recovery devices premised. The overall demodulator performance can be improved by not being affected by the instability of the carrier recovery circuit.

Passband Symbol Timing Recovery, CFLL, Fine PLL

Description

Timing recovery apparatus and its method in digital broadcasting receiver

1 is a block diagram of a general digital broadcast receiver

2 is a block diagram illustrating a digital broadcast receiver according to the present invention.

3 is a block diagram showing an embodiment of a symbol timing recovery apparatus according to the present invention;

4 (a) and 4 (b) show examples of the preprocessing unit, the conjugate multiplier, the post-processing unit, and the frequency response for each step.

FIG. 5 is a detailed block diagram illustrating an embodiment of the gain normalization unit of FIG. 4. FIG.

Explanation of symbols for main parts of the drawings

200: VSB demodulation section 201: CFLL section

202: passband symbol timing recovery unit

203: Fine PLL section 301: Resampler

302: preprocessing unit 303: conjugate multiplier

304: post-processing unit 305: timing error detection unit

306 loop filter 307 NCO

The present invention relates to a digital broadcast receiver, and more particularly, to an apparatus and method for recovering symbol timing in a digital broadcast receiver for receiving and demodulating a signal modulated and transmitted in a VSB scheme.

In general, the ATSC A / 53 digital television standard, proposed by the Grand Alliance and adopted as the SDTV / HDTV terrestrial transmission standard in the United States and Korea, delivers payload data at 19.4 MHz over 8VSB (8 MHz) on 6 MHz channels. -level Vestigial SideBand) modulates and transmits. The VSB method modulates only the remaining part when one sideband signal of the two sidebands generated up and down about a carrier is greatly attenuated when the signal is amplitude modulated. In other words, it takes one side waveband spectrum of the baseband and transfers it to the passband to transmit the band.

In this case, when the DC spectrum of the base band is shifted to the pass band during the VSB modulation, it is converted into the tone spectrum, and this signal is often called a pilot signal. In other words, when VSB modulation is performed in a broadcasting station, a small size pilot signal is sent to the air to facilitate carrier recovery in a receiver.

According to the above specification, the data frame is composed of two fields, and each field is composed of 313 segments. The 313 segment again consists of a two-level field sync segment and 312 data segments. The first four symbols of each data segment consist of a two-level Data Segment Sync pattern.

1 is a general block diagram of a digital broadcast receiver for receiving and restoring such a VSB signal.

First, the airwave signal input to the antenna 101 is converted into a passband signal of an intermediate frequency (IF) by the tuner 102. This signal is input to the A / D converter 104 via the analog processor 103. The analog processor 103 is composed of a SAW filter for removing high frequency components generated from adjacent channel interference and a tuner, a gain control unit (AGC) for adjusting the level of an input signal, and the like.

The A / D converter 104 converts the analog passband signal output from the analog processor 103 into a digital passband signal and outputs the signal to the phase separator 105. For example, when the fixed oscillator is used in the A / D converter 104, the analog signal is converted into a digital signal having a fixed frequency.

The phase separator 105 separates the digital passband signal into a passband signal having a real component and an imaginary component whose phases are 90 ° to each other, and outputs the digital passband signal to the carrier recovery unit 106. Here, for convenience of description, the real component signal output from the phase separator 105 is called an I signal, and the imaginary component signal is called a Q signal.

The carrier recovery unit 106 transitions the I, Q digital passband signal output from the phase separation unit 105 to an I, Q digital baseband signal, and then returns to the symbol timing recovery unit 107 for symbol clock recovery. Output

The symbol timing recovery unit 107 synchronizes a clock of a transmitter and a clock of a receiver, and ultimately, a decision error at an equalizer output by sampling a baseband or passband signal at an optimal point in time. Should be operated to minimize

The output of the symbol timing recovery unit 107 is input to the channel equalizer 108. The channel equalizer 108 removes Inter-Symbol Interference (ISI) included in the signal that has passed through the symbol timing recovery unit 107 and outputs it to the phase tracking unit 109. That is, in a digital transmission system such as HDTV, a bit detection error occurs at a receiving side due to distortion caused by a transmission signal passing through a multi-path channel, interference by an NTSC signal, and distortion by a transmission / reception system. In particular, propagation of signals through multipaths causes intersymbol interference (ISI), which is a major cause of bit detection errors. Thus, the channel equalizer 108 eliminates such inter-symbol interference (ISI).

The phase tracker 109 corrects a residual phase of a carrier that is not completely removed by the carrier recovery unit 106 and outputs the residual phase to a forward error correction 110.

The FEC unit 110 corrects an error of the phase-corrected signal and outputs it to the A / V signal processor 111. That is, a transmitter such as a broadcast station selects an appropriate technique for the system and encodes and transmits a transmission signal, and a receiver, such as a digital broadcast receiver, decodes the transmitted signal and corrects an error generated while passing through a channel. The block for performing the decoding process is the FEC unit 110.

The A / V signal processing unit 111 restores the video and audio signals compressed by MPEG-2 and Dolby AC-3 methods to their original state, and transmits the video signals to a monitor so that the screen can be viewed and the audio signal is a speaker. To be heard.

However, when using the digital broadcast receiver structure as shown in FIG. 1, the performance of the symbol timing recovery unit 107 depends on the performance of the carrier recovery unit 106. In particular, in the case of the prior art in which the carrier recovery unit 106 and the symbol timing recovery unit 107 use different sidebands of the frequency spectrum, even if the situation can operate well by the symbol timing recovery unit 107 itself, the carrier wave If the restoration is unstable, this immediately adversely affects the symbol timing restoration unit 107.

In addition, the FPLL (Frequency & Phase Locked Loop), which is a carrier recovery algorithm used in the conventional structure, uses a pilot signal of the VSB spectrum. When long ghost is applied, the jitter becomes severe due to the data pattern. do. This also results in degrading the performance of the symbol timing recovery unit 107. This results in performance degradation of the overall system.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a symbol timing recovery apparatus and method for extracting accurate symbol timing information from an input signal even in a situation where a carrier frequency offset remains. .

In order to achieve the above object, the timing recovery apparatus of the digital broadcast receiver according to the present invention, the pre-processing unit for receiving the digital signal recovered only the carrier frequency components to filter both bands; A conjugate multiplier for performing a conjugate multiplication on the output of the preprocessor to remove the influence of the carrier; A timing error detector for detecting a timing error from an output of the conjugate multiplier; And a loop filter and an NCO for generating a sampling clock proportional to the low band component of the detected timing error.

When the digital signal recovered only by the carrier frequency component is sampled and generated by a fixed frequency, a resampler for correcting and outputting the digital signal with a sampling clock output from the NCO may be further included.

And a post-processing unit which removes jitter due to DC and data from the output of the conjugate multiplier and outputs it to the timing error detector.

The timing error detector may further include a gain normalization unit configured to perform a complex gain normalization on an input signal at the front end.

The gain normalizer may include: a phase separator converting an input signal into a real component and an imaginary component; An arithmetic unit for multiplying a real signal and an imaginary signal output from the phase separator by each square and adding a root to the addition result and dividing by a constant 1; A delayer for delaying the real signal output from the phase separator by the processing time of the operation unit; And a multiplier for multiplying the real signal delayed by the delay unit with the output of the operation unit and outputting the multiplier to the timing error detector.

Timing recovery method of the digital broadcast receiver according to the present invention,

(a) receiving the recovered digital signal with only carrier frequency components and filtering both bands;

(b) performing conjugate multiplication on the output of step (a) to remove the influence of the carrier;

(c) detecting timing error through zero crossing after removing jitter from the output of step (b); And

(d) generating a sampling clock proportional to the low band component of the timing error detected in step (c).

Step (c) is

(c-1) converting the jitter-free input signal into a real component and an imaginary component;

(c-2) squaring and adding the real and imaginary signals transformed in step (c-1), respectively, and taking the root of the addition result and dividing by a constant 1; And

and (c-3) multiplying the real signal of step (c-1) by the operation result of step (c-2) and outputting the result for timing error detection.

Other objects, features and advantages of the present invention will become apparent from the following detailed description of embodiments taken in conjunction with the accompanying drawings.

Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention that can specifically realize the above object will be described. At this time, the configuration and operation of the present invention shown in the drawings and described by it will be described as at least one embodiment, by which the technical spirit of the present invention and its core configuration and operation is not limited.

The same components as in the related art are denoted by the same names and the same reference numerals for convenience of description, and detailed description thereof will be omitted.

2 is a schematic diagram of a digital broadcast receiver according to the present invention, which has been previously filed by the present applicant (Domestic Application No .: P04-77817, filing date: September 30, 2004).

2 is a structure for improving performance of a digital broadcast receiver by preventing a carrier recovery block from affecting a symbol timing recovery block even under a severe fading channel.

That is, the analog IF signal having a center frequency of about 6 MHz or 5.38 MHz is digitized by the A / D converter 104 and then input to the coarse frequency locked loop (CFLL) unit 201 of the VSB demodulator 200. Unlike the FPLL of the prior art, the CFLL unit 201 does not track the phase component in the carrier but only tracks the frequency component of the carrier. The data passing through the CFLL unit 201 is close to the baseband signal, but may be referred to as a passband signal because it includes a residual phase of a carrier wave. When the CFLL unit 201 tracks only the frequency components of the carrier, it is possible to secure fast acquisition time during carrier recovery, thereby making it possible to quickly track the frequency of the carrier in a dynamic channel environment. In addition, by allowing the CFLL unit 201 to capture only the frequency of the carrier, it can bring a much wider pull-in characteristics than the prior art.

The data passing through the CFLL unit 201 is input to the symbol timing recovery unit 202. In this case, since the input signal includes a carrier residual phase component, the symbol timing recovery unit 202 should be designed to operate in a passband, which is referred to as pass-band TR in FIG. 2. The data passing through the symbol timing recovery unit 202 is applied to a fine phase locked loop (PLL) unit 203 to track the residual carrier phase component. Since the Fine PLL unit 203 does not have to cope with the frequency offset of the large carrier, an algorithm optimized for the phase tracking performance of the carrier can be applied. Therefore, it is possible to improve the performance of the digital broadcast receiver as a whole.

The present invention relates to a symbol timing recovery unit of the digital broadcast receiver of FIG. 2 that can obtain accurate symbol timing information from a signal including a carrier residual phase.

The apparatus and method for recovering symbol timing according to the present invention can be robustly operated even in the presence of carrier frequency offset of about several tens of KHz as well as carrier phase.

FIG. 3 is a block diagram illustrating an embodiment of a symbol timing recovery apparatus according to the present invention, and includes a re-sampler 301, a pre-processing unit 302, and a conjugate multiplication unit. 303), a post-processing unit 304, a timing error detection (TED) unit 305, a loop filter 306, and a NCO (Numerically Controlled Oscillator) 307.

The reason why the resampler 301 is needed in FIG. 3 is because it is assumed that the A / D converter 104 samples an analog signal using a fixed frequency. If the A / D converter 104 samples the analog signal using a variable frequency, no resampler is required, and instead, the output of the NCO 307 is input to the A / D converter 104.

That is, the resampler 301 receives a passband complex signal corrected only for a carrier frequency offset from the CFLL unit 201 and generates a sample corresponding to twice the symbol frequency (fs = 10.76 MHz).

The output of the resampler 301 is output to the preprocessing unit 302 and to the Fine PLL unit 203. The fine PLL unit 203 corrects the residual phase, performs DC elimination, matched filtering, and outputs the same to the channel equalizer 108.

The preprocessor 302 carefully filters the output of the resampler 301 and outputs it to the conjugate multiplier 303 to reduce jitter. The conjugate multiplier 303 performs a conjugate product on the output of the preprocessor 302 and outputs the result to the post processor 304 to remove the influence of the carrier wave.

That is, the upper side band of the spectrum of the signal generated by the conjugate multiplier 303 is determined by the bandwidth of the input spectrum regardless of the carrier frequency of the input signal. Therefore, the present invention makes it possible to implement a passband symbol timing recovery apparatus by using a simple zero-crossing detector using this characteristic.

에 심벌 타이밍 옵셋이 더해진 정현파가 되며, 이 정현파는 TED부(305)로 입력된다. 상기 TED부(305)는 입력 정현파의 제로-크로싱(zero-crossing)을 감지하는 어떠한 형태의 제로 크로싱 에러 검출기를 사용해도 무방하다. In the post processor 304, in order to remove jitter due to DC and data generated by the conjugate multiplier 303, a gain for maintaining a constant frequency acquisition performance even in the presence of a post filtering function and severe channel fading. It will perform the control function. The output signal of the post processor 304 is the center frequency

A symbol timing offset is added to the sine wave, and the sine wave is input to the TED unit 305. The TED unit 305 may use any type of zero crossing error detector that detects zero-crossing of the input sinusoid.

The timing error signal detected by the TED unit 305 is low pass filtered through a second loop filter 306 operating at a symbol frequency (fs, 10.76 MHz). The low pass filtered signal output from the loop filter 306 becomes a DC component, and the DC signal is input to the NCO 307. The NCO 307 provides the sampling clock according to the input DC to the resampler 301.

As described above, the symbol timing recovery is performed when the center frequency of the sine wave input to the TED unit 305 becomes 1/4 of the sampling clock. Control parameters of the second-order loop filter 306 may be variably applied in an acquisition mode and a tracking mode. For example, it is adjusted to facilitate sampling frequency recovery in the acquisition mode and to minimize the influence of noise in the tracking mode.

FIG. 4A shows the preprocessor 302, the conjugate multiplier 303, and the postprocessor 304, and FIG. 4B shows the frequency response characteristics of each step of (a) in detail. have.

First, the frequency response of the output terminal of the resampler 301 is shown including the residual frequency response to emphasize that there is no problem in symbol timing recovery even when there is a residual carrier frequency offset. For example, if the residual carrier frequency offset is Δ, the lower sideband of the signal spectrum output from the resampler 301 is located at Δ and the upper sideband is at Δ + fbw. At this time, the symbol timing error should be purely determined by fbw regardless of Δ.

As described above, when detecting the timing side error by detecting the upper sideband of the conjugate multiplication signal, it is finally necessary to determine the position and roll-off of the upper sideband. Since both bands of the output frequency response 401 of the PMI are filtered by the preprocessor 302 before the conjugate multiplication, the tracking performance can be improved by reducing the amount of timing error jitter.

로 주파수 변조(modulation)한 후 전치 필터로 출력한다. 상기 전치 필터는 송신단에서 사용한 것과 동일한 롤-오프 인자(roll-off factor)를 갖는 제곱근 상승 코사인(Square-root Raised Cosine ; SRC) 필터를 이용하며, 도 4의 (b)와 같이 주파수 변조된 신호의 양측대역을 도 4의 (b)의 주파수 응답(403)과 같이 필터링한다. 즉 상기 전치 필터는 데이터에 의한 지터를 줄이기 위해 유한 임펄스 응답(FIR) SRC 필터를 사용하는 것을 실시예로 한다. In this case, the preprocessor 302 includes a modulator and a prefilter BPF1. That is, the modulator outputs the output of the resampler 301 as indicated by the dotted line in the frequency response 402 of FIG.

After modulating the frequency, it outputs to the prefilter. The pre-filter uses a Square-root Raised Cosine (SRC) filter having the same roll-off factor as that used at the transmitter, and a frequency-modulated signal as shown in FIG. Both bands of are filtered as shown in the frequency response 403 of FIG. In other words, the prefilter uses a finite impulse response (FIR) SRC filter to reduce jitter caused by data.

In this case, similar performance can be obtained by using a passband filter of an infinite impulse response (IIR) type as a prefilter of the preprocessor 302. However, in the case of the IIR type, a small amount of DC is applied to the timing error. If the sideband is severely attenuated and the information of the timing error is very small, the clock may be pushed in one direction regardless of the timing offset. Can be.

When the conjugate multiplication is performed by the conjugate multiplier 303 for the signal from which both bands are filtered by the preprocessor 302, the DC and fbw are centered as shown in the frequency response 404 of FIG. Frequency components are created due to the convolution of the sidebands. At this time, the components around the DC are due to convolution between the same side bands and are not related to the actual timing offset. Also, the frequency components generated around ± fbw are the convolutions between the lower sideband and the upper sideband, and have information of the frequency bandwidth fbw of the input spectrum, regardless of the amount of carrier frequency offset. Of course, since the amount of carrier frequency offset that can be tolerated is determined by the prefilter of the preprocessor 302 provided to reduce jitter, the type and bandwidth of the prefilter are designed in consideration of the maximum value of the carrier frequency offset of the input signal. Should be.

인 IIR 타입의 통과대역 필터(BPF2)를 사 용한다. 상기 후치 필터의 대역폭은 안정적인 포착 성능을 위하여 발생 가능한 타이밍 옵셋의 최대값을 포함하여야 하며, 추적 지터(tracking jitter)의 양을 충분히 줄일 수 있도록 설계되어야 한다. 상기 후치 필터(BPF2)의 출력 신호는 도 4의 (b)의 405와 같은 주파수 응답을 갖는다.In this case, a post filter of the post processor 304 is passed to further remove DC values and jitter from the timing information obtained through the conjugate multiplication. The post filter is the center frequency

An IIR type passband filter (BPF2) is used. The bandwidth of the post filter should include the maximum value of the timing offset that can be generated for stable acquisition performance, and should be designed to sufficiently reduce the amount of tracking jitter. The output signal of the post filter BPF2 has a frequency response such as 405 of FIG. 4B.

The symbol timing recovery apparatus according to the present invention is affected by the degree of attenuation at both ends of the spectrum as in the method of using sidebands of other spectrums. In other words, when the side ends of the spectrum are attenuated by the channel, the magnitude of the TED input sinusoid is attenuated and thus the magnitude of the timing error is also reduced. In this case, the timing recovery time becomes too long or, in severe cases, the restoration is impossible.

Therefore, in order to prevent this, the present invention proposes a timing error gain normalization unit 400.

5 is a detailed block diagram of a gain normalization unit according to the present invention, and includes a phase separator 501, a complex squarer 502, a divider 503, first and second delayers 504 and 505, and a first and a second agent. It consists of two multipliers (506, 507).

For example, if the complex input signal of the gain normalization unit 400 is C, the gain normalization unit 400 generates Cnorm by performing gain normalization as shown in Equation 1 below. Output to the TED unit 305.

That is, since the output signal of the post processor 304 is a real number, it is input to a phase splitter 501 to perform complex normalization. The phase separator 501 generates the imaginary signal Q from the real signal I, and then outputs the real signal I to the complex squarer 502 and the first delayer 504, and then the imaginary signal ( Q) outputs to the complex squarer 502 and the second delayer 505.

The complex squarer 502 squares each of the real signal I and the imaginary signal Q, adds them (I ² + Q ² ), and outputs them to the divider 503. The divider 503 loops the output of the complex squarer 502 and outputs it to the first and second multipliers 506 and 507 using this value as a denominator. That is, the complex squarer 502 and the divider 503 output 1 / | C | of Equation 1, and the blocks 502 and 503 may be implemented using a pre-calculated ROM table. The first and second delayers 504 and 505 delay the real signal I and the imaginary signal Q by the processing time of the complex squarer 502 and the divider 503, respectively. Output to multipliers 506 and 507.

The first multiplier 506 multiplies the output 1 / | C | of the divider 503 by the delayed real signal I to output a gain normalized real signal Cnorm, I, and the second multiplier 507 outputs the The gain normalized imaginary signal Cnorm, Q is output by multiplying the output 1 / | C | of the divider 503 by the delayed imaginary signal Q.

The normalized sinusoids obtained by the first and second multipliers 506 and 507 are superior to the method of increasing the gain when the average power is small by obtaining the average power of the existing input sinusoid. In other words, in order to accurately calculate the average power, it is necessary to take an average with more samples. In this case, since the delay time is increased, the performance may be degraded when the channel change is fast. In contrast, the complex gain normalization method of the present invention normalizes the complex envelope of the input sinusoid to 1 without delay, and thus it is applicable to a channel change faster than the method using the average power.

In addition, the symbol timing recovery apparatus according to the present invention can recover timing even in the presence of residual carrier frequency offset, and in particular, by applying the gain normalization unit 400, the symbol timing frequency acquisition performance is excellent even in multiple interference channels. Do.

Also, in order to reduce jitter caused by data, the pre-filter uses an FIR SRC filter, which can be replaced by an IIR passband filter to reduce implementation complexity and loop delay. The gain normalization unit 400 may be replaced with other methods such as a method using average power.

In this case, if the TED unit 305 is a general zero-crossing detector, the TED unit 305 may be applied without significant performance difference. For example, the TED unit 305 may use a modified Gardner type timing error detector.

And a data communication system typically consists of a transmission path between a transmitter, a receiver and a transmitter / receiver. Although the present invention can be applied to various communication systems, the present invention has been described in accordance with the HDTV terrestrial transmission method. This is only one example of a communication system and can be applied to many other communication fields.

On the other hand, the terms used in the present invention (terminology) are terms defined in consideration of the functions in the present invention may vary according to the intention or practice of those skilled in the art, the definitions are the overall contents of the present invention It should be based on.

The present invention is not limited to the above-described embodiments, and as can be seen in the appended claims, modifications can be made by those skilled in the art to which the invention pertains, and such modifications are within the scope of the present invention.

The effects of the symbol timing recovery apparatus and method of the digital broadcast receiver according to the present invention described above are as follows.

First, even when the carrier frequency offset is not completely removed, the entire demodulator structure can be reconstructed by extracting only symbol timing information from an input signal.

Secondly, since the timing recovery apparatus operates regardless of the carrier phase, the capturing and tracking performance is superior to most symbol timing recovery apparatuses based on the existing carrier recovery.

Third, it can be applied to improve the overall demodulator performance by not being affected by the instability of the carrier recovery circuit.

Fourth, it is possible to apply a carrier recovery apparatus on the premise of timing recovery. For example, a carrier recovery algorithm using both side bands may be applied. And by restoring the symbol timing before the carrier recovery is completed, it is possible to apply the carrier recovery algorithm using the channel estimation.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present invention.

Therefore, the technical scope of the present invention should not be limited to the contents described in the embodiments, but should be defined by the claims.

Claims (11)

A preprocessor configured to filter the both bands by receiving the recovered digital signal with only carrier frequency components; A conjugate multiplier for performing a conjugate multiplication on the output of the preprocessor to remove the influence of the carrier; A timing error detector for detecting a timing error from an output of the conjugate multiplier; And And a NCO and a loop filter to generate a sampling clock proportional to the low band component of the detected timing error. The method of claim 1, And a resampler for correcting and outputting the digital signal using a sampling clock output from the NCO when the digital signal recovered only by the carrier frequency component is sampled by a fixed frequency. . The method of claim 1, wherein the pretreatment unit The output of the resampler

And frequency band-modulating the two bands of the frequency-modulated signal with a square root rising cosine (SRC) filter having the same roll-off factor as used at the transmitting end. The method of claim 1, And a post-processing unit which removes jitter by DC and data from the output of the conjugate multiplier and outputs it to the timing error detector. The method of claim 4, wherein the post-processing unit Center frequency

and fs is a passband filter of type IIR, wherein fs is a symbol frequency. The method according to any one of claims 1 to 4, A gain normalizer for performing complex gain normalization on an input signal is further included in front of the timing error detector; The gain normalization unit A phase separator for converting an input signal into a real component and an imaginary component; An arithmetic unit for multiplying the real signal and the imaginary signal output from the phase separator by each square and taking a root of the addition result and dividing by a constant 1; A delayer for delaying the real signal output from the phase separator by the processing time of the operation unit; And And a multiplier configured to multiply the real signal delayed by the delay unit to an output of the operation unit and output the multiplier to the timing error detector. In the timing recovery apparatus of the digital broadcast receiver comprising a CFLL unit for tracking only the frequency component of the carrier from the digitized signal, and a demodulator including a Fine PLL unit for tracking the residual carrier phase component, A pre-processing unit for filtering both side bands of the digital signal outputted by recovering only a carrier frequency component from the CFLL unit; A conjugate multiplier for performing a conjugate multiplication on the output of the preprocessor to remove the influence of the carrier; A post processor which removes jitter by DC and data from an output of the conjugate multiplier; A timing error detector for detecting a zero crossing of the signal output from the post processor and generating a timing error; And And a NCO and a loop filter for generating a sampling clock proportional to the low band component of the timing error output from the timing error detector. The method of claim 7, wherein the pretreatment unit The output of the resampler

And frequency band-modulating the two bands of the frequency-modulated signal with a square root rising cosine (SRC) filter having the same roll-off factor as used at the transmitting end. The method of claim 7, wherein A gain normalization unit configured to perform complex gain normalization on an input signal is further included between the post processor and a timing error detector; The gain normalization unit A phase separator for converting an input signal into a real component and an imaginary component; An arithmetic unit for multiplying a real signal and an imaginary signal output from the phase separator by each square and adding a root to the addition result and dividing by a constant 1; A delayer for delaying the real signal output from the phase separator by the processing time of the operation unit; And And a multiplier configured to multiply the real signal delayed by the delay unit to an output of the operation unit and output the multiplier to the timing error detector. (a) receiving the recovered digital signal with only carrier frequency components and filtering both bands; (b) performing conjugate multiplication on the output of step (a) to remove the influence of the carrier; (c) detecting timing error through zero crossing after removing jitter from the output of step (b); And (d) generating a sampling clock proportional to the low band component of the timing error detected in step (c). The method of claim 10, wherein step (c) (c-1) converting the jitter-free input signal into a real component and an imaginary component; (c-2) squaring and adding the real and imaginary signals transformed in step (c-1), respectively, and taking the root of the addition result and dividing by a constant 1; And and (c-3) multiplying the real signal of step (c-1) by the operation result of step (c-2) and outputting the result for timing error detection.

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