KR20060092014A - Method for manufacturing contact in semiconductor device - Google Patents

Abstract

The present invention provides a method for manufacturing a contact of a semiconductor device suitable for preventing an increase in contact resistance when forming a contact, comprising the steps of: forming a plurality of gate electrode patterns having spacers attached on a semiconductor substrate; Forming a landing plug contact between the gate patterns; And forming a selective epitaxially grown silicon and metal material in the landing plug contact.

Solid Phase Epitaxy, Landing Plug Contact, Epitaxial Silicon, Regrowth, Contact Resistance

Description

Method for manufacturing a contact of a semiconductor device {METHOD FOR MANUFACTURING CONTACT IN SEMICONDUCTOR DEVICE}

1 is a process cross-sectional view showing a method for manufacturing a contact of a semiconductor device according to the prior art;

2 is a TEM photograph of the SPE deposited on the contact,

3A to 3D are cross-sectional views illustrating a method for manufacturing a contact of a semiconductor device according to an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

31 semiconductor substrate 32 device isolation film

33: gate electrode pattern 34: gate spacer

35 source / drain junction 36 landing plug contact

37 epitaxial silicon 38 metal material

TECHNICAL FIELD The present invention relates to semiconductor manufacturing technology, and more particularly, to a method for manufacturing a contact of a semiconductor device.

As semiconductor devices become smaller and more integrated, the contact area decreases, resulting in an increase in contact resistance, a decrease in drive current, a word line defect in a transistor, and a decrease in device yield.

In this situation, to reduce the contact resistance of the device and to improve the operating current, a method of increasing the dopant concentration of the silicon substrate junction portion or the phosphorus (phosphorus) concentration of the dopant in the current contact polysilicon is being used. Here, polysilicon is polysilicon deposited at a batch type furnace (500 ° C. to 600 ° C., using SiH ₄ / Ph ₃ gas, phosphorus concentration of 0.1e ²⁰ atoms / cm ^{3 to} 0.3e ²⁰ atoms / cm ³ ). However, it is known that increasing the dopant in the junction or the doping concentration in polysilicon tends to lower the refresh (tREF) and refresh characteristics of the device. Also, poly-silicon is deposited on the furnace under atmospheric pressure during deposition. When loading, it is confirmed and reported that a fine oxide film is formed at the interface between the poly-silicon and the silicon substrate by the oxygen concentration (tens of ppm) present, which is one cause of increasing the contact resistance of the device. have. The problem in the method of forming a contact using polysilicon is a situation in which it is difficult to lower the contact resistance and improve the characteristics of the device as the semiconductor device continues to be highly integrated in the future.

1 is a process cross-sectional view showing a method for manufacturing a contact of a semiconductor device according to the prior art.

As shown in FIG. 1, a plurality of gate patterns 13 having spacers 14 are formed on the semiconductor substrate 11 on which the device isolation layer 12 is formed. An ion implantation process (not shown) for forming the source / drain regions 15 is performed, and the epitaxial silicon 16 is grown in the contacts between the gate patterns 13.

In order to overcome the above problems and lower the contact resistance of the device as well as to improve the device characteristics, epitaxial silicon (epitaxial Si) is being developed and applied to existing semiconductor device manufacturing processes in addition to selective epitaxial growth (SEG). At the same time, low-temperature deposition is possible, and even at low concentrations of doping concentrations, SPE (solid phase epitaxy) is enough to overcome the problems of conventional polysilicon. Initial SPE is SiH ₄ / PH ₃ gas by using the doping-in 500 ℃ ~650 ℃ temperature range is formed at a relatively low 1e ¹⁹ ~1e ²⁰ amorphous silicon (amorphous Si) having a concentration of atoms / cm ^3. The initial deposited SPE is followed by a thermal process at a relatively low temperature (550 ° C. to 650 ° C., 10 hours to 30 minutes, nitrogen atmosphere) to cause epitaxial silicon to regrowth from the substrate interface to the upper contact region. . In the case of polysilicon, phosphorus concentration must be increased to reduce contact resistance, but this causes deterioration of the refresh characteristics of the device. In the epitaxial silicon used to overcome this problem, the interfacial properties are improved, so that the contact resistance can be kept low even when phosphorus is doped at a low concentration. However, as the device becomes more integrated to the sub 100 nm level, it is necessary to maintain lower contact resistance, so epitaxial silicon also has a limit in terms of the resistivity of the material itself, so even if the epitaxial silicon is doped to 1e ²⁰ atoms / cm ³ , 1e ^-3 It shows a specific resistance value of about mΩ-cm and it is difficult to lower it. Therefore, in the next-generation semiconductor device of sub 100 nm or smaller, a contact resistance lower than that of epitaxial silicon is required, and the reliability and yield of the device must be sufficiently secured.

As described above, the reason why the contact resistance for forming a contact increases in the prior art is that a fine oxide film is formed at the interface between the polysilicon and the semiconductor substrate.

The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a method for manufacturing a contact of a semiconductor device suitable for preventing an increase in contact resistance during contact formation.

The contact manufacturing method of the present invention for achieving the above object comprises the steps of forming a plurality of gate patterns attached to the spacer on a semiconductor substrate, forming a landing plug contact between the gate pattern, and selectively to the landing plug contact Forming epitaxial sheet silicon and a metal material in turn.

Hereinafter, the most preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. .

2 is a TEM photograph of epitaxial silicon formed using solid phase epitaxy (SPE) in a contact region.

SPE is deposited in a single-type CVD apparatus for 220 seconds at 610 ° C. without a high temperature in-situ H ₂ -bake process. Partial epitaxial silicon (a) is grown on the interface between the gate electrodes (c) formed on the semiconductor substrate. It can be seen that amorphous silicon (b) is deposited thereon. Subsequently, when the low temperature thermal process (550 ° C. to 650 ° C., 10 hours to 30 minutes) is performed, the epitaxial silicon (b) is grown from the epitaxial silicon (a) that has already been grown on the substrate interface to the upper amorphous silicon (b) region. a) is regrown to fill the contact region with epitaxial silicon (a). However, this SPE also has an amorphous silicon (b) on the lower epitaxial silicon (a), there is a problem that the upper amorphous silicon (b) must be removed to form the SPE / metal contact.

3A to 3D are cross-sectional views illustrating a method for manufacturing a contact of a semiconductor device according to an embodiment of the present invention.

As shown in FIG. 3A, after forming the isolation layer 32 on the semiconductor substrate 31 through a shallow trench isolation (STI) process, a plurality of gate patterns 33 are formed.

Subsequently, as shown in FIG. 3B, gate spacers 34 are formed on both sides of the gate pattern 32. Thereafter, an ion implantation process is performed on the gate pattern 34 to form a source / drain junction 35 region, and a landing plug contact (not shown) is formed in the region using a landing plug mask (LPC) (not shown). Form 36). Thereafter, wet or dry cleaning is performed as a pretreatment process to form the contact material. Wet cleaning is HF-last cleaning, and dry cleaning is carried out in the range of 25 ° C. to 400 ° C. in a plasma process using hydrogen or a mixed gas of hydrogen / nitrogen.

Subsequently, as shown in FIG. 3C, after forming the landing plug contact 36, the first contact material 37 and the second contact material 38 to be used as the pretreatment process and the landing plug are sequentially deposited. These contact materials include Pow Pressure CVD (LPCVD), Very Low Pressure CVD (VLPCVD), Plasma Enhanced CVD (PECVD), Ultra High Vacuum CVD (UHVCVD), Rapid Thermal CVD (RTCVD), Atmosphere Pressure CVD (APCVD), and MBE (MBE). Molecular Beam Epitaxy) is formed in any one device selected from the group of.

The first contact material 37 formed in such equipment is epitaxial silicon, and the second contact material 38 is a metal material, which serves to further lower the contact resistance of the device. In this case, the specific resistance of the metal itself is about 1000 times lower than that of silicon, which is very advantageous in terms of resistance. If only metal is used as the plug material, the problem due to the deep level impurity caused by the metal atoms directly contacting the active silicon is to form a metal material after growing a thickness of epitaxial silicon on the active silicon. By applying SEG as a metal and epitaxial silicon with a small thickness, it is possible to easily form epitaxial silicon / metal material contact by depositing a metal material directly on it. However, SEG undergoes this pre-treatment process and SEG growth at high temperature (800 ° C.) at H ₂ -ake, 850 ° C., and ₂ min in high temperature in-situ before growth. Silver has dopant diffusion in the channel and junction of the device. Therefore, in the present embodiment, the epitaxial silicon and the metal material are formed by using a solid phase epitaxy (SPE) that realizes epitaxial silicon at a low temperature without undergoing a high temperature process such as SEG.

Meanwhile, any material selected from the group of silicon (Si), germanium (Ge), and silicon germanium (SiGe) may be used as the first contact material 37, and HCl gas may be added in the process of forming the first contact material 37. It can be formed into a selectivity epitaxial silicon. In addition, the first contact material 37 is doped with phosphorus (P) or arsenic (As), wherein the doping concentration of the dopant is in the range of 1e ¹⁸ atoms / cm ^{3 to} 1e ²¹ atoms / cm ³ . The thickness of the first contact material 37 is 100 kPa to 1000 kPa, and is formed at a temperature of 400C to 700C.

Subsequently, the surface of the first contact material 37 is subjected to a pre-treatment process by wet or dry cleaning, and the second contact material 38 is formed. In this case, the second contact material 38 is any one metal material selected from the group of Ti, TiN, Ni, Co, and W, using a method such as chemical vapor deposition (CVD) or physical vapor deposition (PVD). Form.

In addition, the second contact material 38 may be double deposited with different metals, and in order to fill the contact of the cell region, Ti or TiN of the second contact material 38 is formed first, and the contact of the peripheral circuit region is formed. Tungsten is formed later in the second contact material 38 to fill.

As shown in FIG. 3D, after the contact plug process is completed with subsequent etch back and chemical mechanical polishing, the subsequent process is continued to form a semiconductor device.

In this embodiment, the SPE is a low temperature process using only thin selective epitaxial silicon already formed on a semiconductor substrate even in an as-deposited state without a high temperature in situ H ₂ -bake process, and for SPE regrowth. There is no need to proceed with subsequent thermal processes (550 ° C. to 650 ° C., 10 hours to 30 minutes). In addition, it is possible to fill the DRAM cell and peripheral circuit area (Peri) contact at once.The cell is titanium silicide / titanium nitride (TiN), and the peripheral circuit area is titanium silicide / titanium. Filled with nitride (TiN) / tungsten (W).

That is, when Ti / TiN is first deposited, the cell is filled with Ti / TiN because the contact size is small, but since T / TiN is not filled in the peripheral circuit region, tungsten (W) is deposited again to fill the peripheral circuit region. Thereafter, tungsten etchback and chemical mechanical polishing (CMP) may be used to fill the cell as well as the peripheral circuit region with a metal material.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

The present invention described above is formed by stacking epitaxial silicon and a metal material in a contact region of a semiconductor device, thereby reducing the contact resistance of the device, thereby improving device reliability and device yield.

Claims (19)

A contact for connecting the lower conductive layer and the upper conductive layer is a semiconductor device having a dual structure in which a selective epitaxial growth silicon and a metal material are laminated. The method of claim 1, The metal material is a semiconductor device, characterized in that using any one selected from the group of Ti, TiN, Ni, Co, W. The method of claim 1, The metal material is a semiconductor device, characterized in that formed in two different metal. The method of claim 1, And the selective epitaxially grown silicon is doped with an impurity. The method of claim 4, wherein The impurity is a semiconductor device, characterized in that the phosphorus or arsenic. The method of claim 5, The impurity is doped at a concentration of 1e ¹⁸ atoms / cm ^{3 to} 1e ²¹ atoms / cm ³ . The method of claim 1, The metal material is a semiconductor device, characterized in that formed by chemical vapor deposition or physical vapor deposition. Forming a plurality of gate electrode patterns attached with spacers on the semiconductor substrate; Forming a landing plug contact between the gate patterns; And Selectively forming epitaxially grown silicon and a metal material on the landing plug contact A semiconductor device manufacturing method characterized in that. The method of claim 8, The metal material is a semiconductor device manufacturing method, characterized in that using any one material selected from the group of Ti, TiN, Ni, Co, W. The method of claim 8, The metal material is a semiconductor device manufacturing method, characterized in that to form a double with a different metal. The method of claim 8, The second contact material is a semiconductor device manufacturing method, characterized in that formed by any one method selected from chemical vapor deposition, physical vapor deposition.  The method of claim 8, The selective epitaxial growth silicon is a semiconductor device manufacturing method, characterized in that replaceable with a material of silicon, germanium, silicon germanium. The method of claim 8, The selective epitaxially grown silicon is formed at a thickness of 100 kPa to 1000 kPa and a temperature of 400C to 700C. The method of claim 8, And the selective epitaxially grown silicon is doped with an impurity. The method of claim 14, The impurity is a manufacturing method of a semiconductor device, characterized in that the phosphorus or arsenic. The method of claim 14, The impurity is doped at a concentration of 1e ¹⁸ atoms / cm ^{3 to} 1e ²¹ atoms / cm ³ . The method of claim 8, The selective epitaxially grown silicon may be formed by adding HCl gas during the formation process. The method of claim 8, The selective epitaxial growth silicon is a semiconductor device manufacturing method, characterized in that it is possible to proceed with or without a high temperature in situ H ₂ -bake process before formation. The method of claim 8, The selective epitaxially grown silicon and metal material may be formed in any one device selected from the group of LPCVD, VLPCVD, PECVD, UHVCVD, APCVD, and MBE.

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