KR20080042262A - Method for fabricating contact in semiconductor device using solid phase epitaxy process - Google Patents

Abstract

A method for manufacturing a contact of a semiconductor device using a solid phase epitaxy process is provided to realize contact interface characteristic of high quality and to reduce contact resistance by reducing an interface oxide layer through a physical destruction. An ion implantation is performed by using ion implantation energy passing through an interface oxide layer. Inert gas, argon, nitrogen, silicon or phosphorous is implanted in order to pass through the interface oxide layer and physically breakdown the interface oxide layer. The ion implantation energy is 10-50 keV. Ion implantation dose is 5E14-1E16 atoms/cm^2. The interface oxide layer becomes a physically destroyed state(32A). An amorphous layer(33) is formed under a surface of a semiconductor substrate(21) by an ion implantation.

Description

Method for forming contact of semiconductor device using solid phase epitaxy process {METHOD FOR FABRICATING CONTACT IN SEMICONDUCTOR DEVICE USING SOLID PHASE EPITAXY PROCESS}

1 is a view showing a method for forming a contact of a semiconductor device using a solid-phase epitaxy process according to the prior art.

2A to 2D are cross-sectional views illustrating a method for forming a contact in a semiconductor device according to an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

21 semiconductor substrate 22 device isolation film

23: gate insulating film 24: gate electrode

25: gate hard mask 26: gate spacer

27 source / drain junction 28 interlayer insulating film

29: contact hole 30: epitaxial silicon layer

31: amorphous silicon layer 32: interfacial oxide film

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a method for forming a contact of a semiconductor device using a solid phase epitaxy (SPE) process.

In a situation where semiconductor devices are becoming more and more direct, contact formation of DRAMs is also affected. In other words, as semiconductor devices become smaller and more direct, the contact area gradually decreases, resulting in an increase in contact resistance and a decrease in drive current, which causes a write recovery time (tWR) of the semiconductor device. Device degradation such as defects is appearing. In this situation, to reduce the contact resistance of the device and improve the operating current, the dopant concentration of the junction of the silicon substrate may be increased or polysilicon (deposited in a batch-type furnace, 500 to 600 ° C.) SiH ₄ / PH ₃ gas is used. Phosphorus concentration is increased by 0.1 ~ 3.0E20 atoms / cm ^2. However, if excessively increased, the data retention time of the device is increased. tends to degrade retention time characteristics.

However, as long as the silicon oxide is formed at the interface between the polysilicon and the silicon substrate due to the oxygen concentration (approximately tens of ppm) present when loaded into the furnace under atmospheric pressure during polysilicon deposition, this increases the contact resistance of the device. It is the cause. When the polysilicon is continuously applied, it is difficult to lower the contact resistance and improve the characteristics of the device according to the trend that the semiconductor devices continue to be directly integrated in the future.

In order to overcome the above problems and lower the contact resistance of the device as well as to improve the device characteristics, epitaxial silicon is being developed. Among them, there is a solid phase epitaxy (SPE) process that can be applied to an existing semiconductor device manufacturing process as it is, at low temperature, and can sufficiently overcome the problems of existing polysilicon even at a low concentration of doping.

1 is a view showing a method for forming a contact of a semiconductor device using a solid-phase epitaxy process according to the prior art.

Referring to FIG. 1, a gate pattern stacked in the order of a gate insulating layer, a gate electrode, and a gate hard mask is formed on a semiconductor substrate 11, and a gate spacer is formed on sidewalls of the gate pattern.

Subsequently, the source / drain junction 16 is formed on the semiconductor substrate 11 between the gate patterns through ion implantation, and then a contact layer is formed using a solid phase epitaxy process. Here, an amorphous silicon layer 18 is simultaneously formed on the epitaxial silicon layer 17 and the epitaxial silicon layer 17 at an initial stage as-deposited due to the characteristics of the solid phase epitaxy process. Subsequently, when the heat treatment is performed in a subsequent process, the lower epitaxial silicon layer 17 serves as a seed layer to regrow the amorphous silicon layer 18 into the epitaxial silicon layer.

In the prior art as described above, a pretreatment is performed before the solid phase epitaxy process to improve contact resistance. The prior art pretreatment uses Ex-situ wet cleaning.

However, the prior art cannot avoid the formation of the interfacial oxide film 19 at the interface between the source / drain junction 16 and the epitaxial silicon layer 17 as the pretreatment before the solid phase epitaxy process uses Exitus wet cleaning. . That is, after exitu wet cleaning, movement to the chamber in the furnace is inevitably exposed to the air, thereby forming an interfacial oxide film 19 such as SiO ₂ .

Such an interfacial oxide film 19 not only acts as an insulating film between the junction or the source / drain junction 16 and the epitaxial silicon layer 17 but also increases the contact resistance of the device by interfering with the diffusion of the dopant and eventually the device. It may deteriorate characteristics.

Therefore, it is necessary to reduce such an interface oxide film and to further improve device characteristics.

The present invention has been proposed to solve the above problems of the prior art, it is possible to further improve the contact resistance and characteristics of the device by further reducing the interfacial oxide film that may remain when forming a contact layer using a solid-phase epitaxy process. It is an object of the present invention to provide a method for forming a contact of a semiconductor device.

The method of forming a contact of a semiconductor device of the present invention for achieving the above object comprises the steps of forming a contact hole exposing a portion of the surface of the substrate; Preprocessing the contact hole; Forming a contact layer partially filling the contact hole using a solid state epitaxy (SPE) process; Implanting a dopant to penetrate the interface between the contact layer and the substrate; And regrowing a part of the contact layer through heat treatment, wherein the ion implantation is ion implantation using ion implantation energy penetrating the interface between the contact layer and the substrate. In the ion implantation, the ion implantation energy is 10 to 50 keV and the dose is 5E14 to 1E16 atoms / cm ² , and the contact layer is formed to be thin with a thickness of 50 to 400 kV. Si silicon, phosphorous (P), argon (Ar) or nitrogen (Nitrogen, N) is used.

Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

2A through 2D are cross-sectional views illustrating a method for forming a contact in a semiconductor device according to an embodiment of the present invention.

As shown in FIG. 2A, after forming an isolation layer 22 by performing an isolation process for isolation between devices on the semiconductor substrate 21, the gate insulating layer 23 is formed on the semiconductor substrate 21. The gate patterns stacked in the order of the gate electrode 24 and the gate hard mask 25 are formed.

Subsequently, an insulating film is deposited on the semiconductor substrate 21 including the gate pattern and then etched to form a gate spacer 26 in contact with both sidewalls of the gate pattern. In this case, the gate hard mask 25 and the gate spacer 26 may be formed of a material having an etching selectivity with a subsequent interlayer dielectric layer, and may be silicon nitride when the interlayer dielectric layer is a silicon oxide layer.

Next, a junction layer 27 serving as a source / drain of the transistor is formed using a known ion implantation method on the semiconductor substrate 21 exposed between the gate patterns. Here, the bonding layer 27 may be a lightly doped drain (LDD) structure, and an n-type dopant such as arsenic (As) or a p-type dopant such as boron is implanted.

Next, an interlayer dielectric (ILD) 28 is deposited on the semiconductor substrate 21 including the gate pattern. In this case, the interlayer insulating layer 28 uses an oxide, and includes boron phosphorous silicate glass (BPSG), undoped silicate glass (USG), tetra-ethyl-ortho-silicate (TEOS), phosphorous silicate glass (PSG), or boron silicalicate (SGS). Galss) using a silicon oxide film material selected from.

Next, the interlayer insulating film 28 is planarized through a chemical mechanical polishing (CMP) process until the top of the gate pattern is exposed. Subsequently, after forming a contact mask through a photo / etch process, that is, photoresist coating, exposure, and development, the interlayer insulating layer 28 is etched using a contact mask (not shown) as an etching mask to form a contact hole 29 for a cell plug plug contact. ).

In this case, since the photo / etch process margin with the lower layer is insufficient in the ultra-high integrated device, the interlayer insulating layer 28 may be self aligned with the gate hard mask 25 and the gate spacer 26 under a good etching selectivity. ; SAC). Accordingly, the silicon oxide based material, which is the interlayer insulating film 28 exposed by the photo process, is etched at a high speed, but the etching speed of the silicon nitride film, which is the gate hard mask 25 and the gate spacer 26, is slow, so that the upper portion of the gate pattern is etched. Alternatively, the silicon nitride film on the sidewall is protected to some extent to expose the bonding layer 27 of the semiconductor substrate 21.

Meanwhile, since organic contaminants (not shown) remain on the sidewalls and the bottom of the contact hole 29 formed by etching the interlayer insulating layer 28, a pretreatment process is performed to remove them. Here, the pretreatment process proceeds to Ex-situ, but uses both dry and wet processes, and wet cleaning uses the 'HF-last' process (uses hydrofluoric acid (HF) last), and dry is plasma. Thermal processes and reactive gas cleaning processes are used. In addition, the wet cleaning temperature is in the range of room temperature to 150 ° C, and the dry cleaning is performed in the range of 100 to 850 ° C.

As shown in FIG. 2B, after the exit pretreatment as described above, the amorphous silicon layer 31 is grown thinly in the contact hole 29 by a solid-phase epitaxy (SPE) process in the range of 450 to 700 ° C. At this time, in the initial deposition state (As-deposited) during the solid-phase epitaxy process, the epitaxial silicon layer 30 is formed on the bottom surface of the contact hole 29, and as the deposition proceeds, the epitaxial silicon layer 30 is formed. An amorphous silicon layer 31 is formed. Here, the total thickness of the epitaxial silicon layer 30 and the amorphous silicon layer 31 is formed to be 50 to 400 kPa thin, so that the dopant penetrates to the interfacial oxide film 32 during subsequent ion implantation.

The deposition method for the solid-phase epitaxy process is RPCVD, Low Pressure CVD (LPCVD), Very Low Pressure CVD (VLPCVD), Plasma Enhanced CVD (PECVD), Ultra High Vacuum CVD (UHVCVD), RTCVD. (Rapid Thermal CVD), APCVD (Atmosphere Pressure CVD) or MBE (Molecular Beam Epitaxy). When the solid phase epitaxy process is performed, the dopant is doped in situ, wherein the dopant is phosphorous (P), and the doping concentration is 5E19 to 1E21 atoms / cm ² .

Although the amorphous silicon layer 31 and the epitaxial silicon layer 30 used as the contact materials were formed by using the solid phase epitaxy (SPE) process, the contact materials formed by the solid phase epitaxy process include germanium (Ge) in addition to silicon. ), Silicon germanium (SiGe) is also applicable. That is, it can also be formed from epitaxial germanium / amorphous germanium and epitaxial silicon germanium / amorphous silicon germanium.

As described above, since the solid-phase epitaxy process proceeds to the pretreatment process and the excitus, an interfacial oxide film 32 is generated between the epitaxial silicon layer 30 and the semiconductor substrate 21 or the surface of the source / drain junction 27. Can not be avoided.

The present invention proceeds to the ion implantation process, as shown in Figure 2c to remove the interfacial oxide film (32).

As shown in FIG. 2C, ion implantation is performed using ion implantation energy that can penetrate the interfacial oxide film 32. In this case, ion implantation is performed by injecting argon (Ar) or nitrogen (Nitrogen, N), an inert gas, or silicon (Si) or phosphorus to penetrate the interfacial oxide film 32 to physically break the interfacial oxide film 32. (Phophorous, P) is ion implanted, and ion implantation energy is 10-50 keV. The dose during ion implantation is 5E14 to 1E16 atoms / cm ² .

Therefore, the interfacial oxide film 32 is in a physically broken state 32A.

At the same time, an amorphous layer 33 is formed under the surface of the semiconductor substrate 21 by ion implantation. Thus, the amorphous layer 33 is formed as an amorphous (Amorphization).

As shown in FIG. 2D, the amorphous layer 33 and the amorphous silicon layer 31 are regrown into the epitaxial silicon layers 31A and 33A by heat treatment at a relatively low temperature. Here, the heat treatment is carried out for 30 minutes to 10 hours at a temperature in the range of 550 ~ 650 ℃, proceeds for 10 hours at 550 ℃, 30 minutes at 650 ℃. Therefore, the heat treatment time is set shorter as the heat treatment temperature is higher and longer as the heat treatment temperature is lower.

In the solid phase epitaxy process, even if the interfacial oxide film 32 is irregular, if there is a part directly contacting the semiconductor substrate 21, the epitaxial silicon layer can be grown into an epitaxial silicon layer. Thus, the epitaxial silicon layers 31A and 33A may be formed. Regrowth is possible.

Although not shown, the surface is pretreated by wet or dry cleaning prior to filling the remaining area of the contact hole, followed by subsequent processing to fill the remaining area of the contact hole with the same silicon material. Examples thereof include a method of filling with polysilicon having a high phosphorus concentration, a method of filling the epitaxial silicon layer again by the aforementioned solid phase epitaxy method, or a method of filling a metal material. The metal material may be a stack of tungsten and a metal silicide such as titanium, cobalt, nickel, and molybdenum, and a tungsten nitride film and a titanium nitride film may be formed as a diffusion barrier between the metal silicide and tungsten. Meanwhile, the surface may be pretreated by wet or dry cleaning before filling the remaining area of the contact hole.

In this way, the contact resistance of the device can be finally lowered, the device characteristics can be improved, and the yield can be improved.

Then, chemical mechanical polishing or etch back is performed to complete the contact process. On the other hand, the above contact process is applied in both the cell region and the peripheral circuit region.

According to the above-described embodiment, since the interfacial oxide film 32 is physically broken by ion implantation, the interfacial oxide film 32 is greatly reduced, so that high quality epitaxial silicon layers 30, 31A, and 33A are formed in the contact region. In addition, it is possible to obtain a good contact interfacial property to a level similar to that of the Selective Epitaxial Growth (SEG) process as well as to maintain the phosphorus concentration in the epitaxial silicon layer.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, the present invention not only obtains the contact interface characteristics that are similar to those of the SEG process by reducing the surface oxide film by physically destroying the surface oxide film generated when the contact material is formed using the solid phase epitaxy process. By maintaining the phosphorus concentration in the epitaxial silicon layer as it is, the contact resistance is reduced, and reliability and yield can be secured.

Claims (12)

Forming a contact hole exposing a portion of the surface of the substrate; Preprocessing the contact hole; Forming a contact layer partially filling the contact hole using a solid state epitaxy (SPE) process; Implanting a dopant to penetrate the interface between the contact layer and the substrate; And Regrowing a portion of the contact layer through heat treatment Contact forming method of a semiconductor device comprising a. The method of claim 1, The ion implantation step, A method for forming a contact of a semiconductor device by ion implantation using ion implantation energy penetrating the interface between the contact layer and the substrate. The method of claim 2, The ion implantation energy is 10 to 50 keV, the contact forming method of a semiconductor device. The method of claim 3, The method of forming a contact of a semiconductor device in which the dose at the time of ion implantation is 5E14 ~ 1E16 atoms / cm ² . The method of claim 1, The contact layer is a contact forming method of a semiconductor device to form a thickness of 50 ~ 400Å. The method according to any one of claims 1 to 5, The ion implantation step, A method for forming a contact in a semiconductor device in which ion inert gas is implanted as the dopant. The method of claim 6, The inert gas is a contact forming method of a semiconductor device using argon (Ar) or nitrogen (Nitrogen, N). The method according to any one of claims 1 to 5, The ion implantation step, A method for forming a contact in a semiconductor device in which silicon (Si) or phosphorous (P) are ion implanted with the dopant. The method of claim 1, After regrowing a portion of the contact layer, And forming a contact conductive layer filling the remaining region of the contact hole on the regrown contact layer. The method of claim 9, The contact conductive layer, A method for forming a contact of a semiconductor device selected from polysilicon, an epitaxial silicon layer or a metal material by a solid phase epitaxy method. The method of claim 10, The metal material is a stack of metal silicide and tungsten (W), and a diffusion barrier is inserted between the metal silicide and tungsten. The method of claim 1, The heat treatment is, A method of forming a contact for a semiconductor device in which the temperature is in the range of 550 to 650 ° C. and in the range of 30 minutes to 10 hours, but the time is shorter as the temperature is higher.

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