KR20060091599A - Semiconductor device having a landing pad and fabrication method thereof - Google Patents

Abstract

       A semiconductor device having a landing pad and a method of manufacturing the same are provided. In the method of manufacturing a semiconductor device having the landing pad, an interlayer insulating layer is formed on a semiconductor substrate, and a storage node contact plug penetrating the interlayer insulating layer is formed. A landing pad covering the storage node contact plug is formed on the interlayer insulating layer. A storage node electrode is formed on the landing pad. A capacitor dielectric layer conformally covering at least one sidewall of the landing pad and the storage node electrode is formed.

Description

Semiconductor device having a landing pad and a method of manufacturing the same

     1 to 9 are cross-sectional views illustrating a semiconductor device having a landing pad and a method of manufacturing the same according to an embodiment of the present invention.

     The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device having a landing pad and a method for manufacturing the same.

     Since semiconductor devices such as DRAM devices exhibit higher integration levels than SRAM devices, they are widely used in computers and the like requiring large memory devices. The memory cell of the DRAM device includes one access transistor and one cell capacitor. As the degree of integration of semiconductor devices increases, the minimum design rules are becoming smaller. In order to increase the capacitance of the cell capacitor, a DRAM cell having a capacitor over bitline (COB) structure is widely adopted. In this case, the cell capacitor is located on top of the bit line. Therefore, as the integration degree of the DRAM increases, it becomes increasingly difficult to form a storage node contact plug for connecting the storage node electrode of the cell capacitor to the source region of the access transistor. In order to compensate for this, a landing pad serving as an intermediate medium for electrically connecting the storage node contact plug and the storage node electrode is widely adopted.

       Meanwhile, in order to increase the capacitance of the capacitor, one cylinder type storage node electrode (OCS) is widely used. However, as the design rule decreases, the cylinder-type storage node electrode is evaluated to have a high possibility of causing a side fall failure, for example, a two bit failure. This is due to not only the width of the wiring on the semiconductor substrate but also the distance between the wiring and the wiring as the design rule decreases in the planar arrangement of the storage node electrodes. Capacitors manufactured by the prior art are increased in height to meet the fixed capacitance, and due to the narrow spacing between the wirings, the capacitors are inclined or fall down when the molding film is removed by the dip-out process, resulting in a bridge between capacitors Will cause.

       Conventional landing pads occupy a large area in a cell, but do not play any role other than simply connecting layers. There is a need for a semiconductor device having an improved landing pad that can compensate for the above-described problems caused by the reduction of design rules. .

       An object of the present invention is to provide a semiconductor device having a landing pad capable of increasing the capacitance by using the landing pad as part of a capacitor and preventing the storage node electrode from falling down, and a method of manufacturing the same.

       According to an aspect of the present invention, a method of manufacturing a semiconductor device having a landing pad is provided. This method includes forming an interlayer insulating film on a semiconductor substrate. A storage node contact plug penetrating the interlayer insulating layer is formed. A landing pad covering the storage node contact plug is formed on the interlayer insulating layer. A storage node electrode is formed on the landing pad, and a capacitor dielectric layer conformally covering at least one sidewall of the landing pad and the storage node electrode is formed.

       In some embodiments of the present disclosure, the method may further include forming a first etch stop layer on the interlayer insulating layer after forming the interlayer insulating layer. In this case, the storage node contact plug may be formed to pass through the first etch stop layer.

       In other embodiments, the landing pad may be formed by forming a conductive layer on the interlayer insulating layer having the storage node contact plug and patterning the conductive layer.

       In example embodiments, a second etch stop layer may be formed on the conductive layer, and the second etch stop layer may be patterned together with the conductive layer.

       In example embodiments, the first etch stop layer and the second etch stop layer may be formed of silicon nitride.

       According to another aspect of the present invention for achieving the above technical problem, a semiconductor device having a landing pad is provided. The semiconductor device includes a semiconductor substrate and an interlayer insulating layer disposed on the semiconductor substrate. The storage node contact plug penetrates the interlayer insulating layer. Landing pads are disposed on the storage node contact plugs. Storage node electrodes are disposed on the landing pads. A capacitor dielectric film is provided to conformally cover at least one sidewall of the landing pad and the storage node electrode.

       In some embodiments of the present disclosure, a first etch stop layer may be further disposed on the interlayer insulating layer and disposed to pass through the storage node contact plug. In other embodiments, a second etch stop layer may be further provided on the landing pad.

       Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided to ensure that the disclosed subject matter is thorough and complete, and that the scope of the invention to those skilled in the art will fully convey. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Like numbers refer to like elements throughout.

       1 to 9 are cross-sectional views illustrating a method of manufacturing a semiconductor device having a landing pad according to an embodiment of the present invention.

       Referring to FIG. 1, an isolation layer 103 is formed in a predetermined region of the semiconductor substrate 100 to define an active region 101. A gate oxide film is formed on the surface of the active region 101, and a gate conductive film and a gate capping film are sequentially formed on the entire surface of the semiconductor substrate 100 having the gate oxide film. The gate conductive layer may deposit a doped polysilicon layer and deposit a metal silicide layer thereon to improve conductivity of the gate. The metal silicide layer may be formed of a tungsten silicide layer. The gate capping layer may be formed of silicon nitride on the metal silicide layer to protect the gate from an etching process and the like. The photo process and the etching process are performed to form a gate pattern including the gate capping layer pattern 113, the gate conductive layer pattern 111, and the gate oxide layer pattern 105. Impurity ions are implanted into the active region 101 using the gate pattern and the device isolation layer 103 as ion implantation masks to form source and drain regions (not shown) of the transistor. The gate spacer 115 is formed by performing a spacer forming process of depositing and etching an insulating layer covering the gate pattern. The gate spacer 115 may be formed of a silicon oxide film or a silicon nitride film.

       Referring to FIG. 2, direct contact pads 119 prepared for electrical connection with a bit line and buried contact pads 121 prepared for electrical connection with a storage node electrode are formed. For example, the first interlayer insulating layer may be formed on the entire surface of the semiconductor substrate 100 having the gate patterns. The active region 101 may be removed by selectively removing the first interlayer insulating layer on which the direct contact pads 119 and the buried contact pads 121 are to be formed using a photolithography process and an optional etching process. A first interlayer insulating film pattern 117 having exposed contact holes is formed. Thereafter, an ion implantation process is performed on the exposed active region 101 to induce contact resistance between the active region 101 and contact pads to be formed later. Thereafter, a conductive film such as doped polysilicon is deposited to fill the contact holes. Subsequently, the direct contact pad 119 and the direct contact pad 119 may be exposed by dry etching, for example, by etching back or exposing an upper surface of the first interlayer insulating layer pattern 117 using a chemical mechanical polishing (CMP) method. Buried contact pads 121 may be formed.

       Referring to FIG. 3, a second interlayer insulating layer 123 is formed on the entire surface of the semiconductor substrate 100 having the direct contact pads 119 and the buried contact pads 121. The second interlayer insulating layer 123 is introduced to insulate the bit line 127 from the buried contact pads 121 and may be formed of silicon oxide. The second interlayer insulating layer 123 is patterned to form a bit line contact hole 125 exposing the direct contact pad 119. The bit line 127 is formed on the entire surface of the semiconductor substrate 100 having the bit line contact hole 125. The bit line 127 may be formed of a conductive polysilicon layer or a metal conductive layer such as tungsten. Accordingly, the bit line 127 is electrically connected to the direct contact pad 119 through the bit line contact hole 125. A third interlayer insulating film 129 is formed on the entire surface of the semiconductor substrate 100 having the bit line 127. The third interlayer insulating film 129 may be formed of a silicon oxide film.

       Referring to FIG. 4, a first etch stop layer 131 is formed on the entire surface of the semiconductor substrate 100 having the third interlayer insulating layer 129. The first etch stop layer 131 may be formed of an insulating layer having an etch selectivity with respect to the third interlayer insulating layer 129. For example, the first etch stop layer 131 may be formed of a silicon nitride layer.

       Referring to FIG. 5, the first etching stop layer 131, the third interlayer insulating layer 129, and the second interlayer insulating layer 123 are successively patterned to expose the buried contact pads 121. Node contact holes are formed. Subsequently, storage node contact plugs 133 are formed in the storage node contact holes using a conventional method. The storage node contact plugs 133 may be formed of doped polysilicon.

       Referring to FIG. 6, a conductive doped polysilicon layer 135 is formed on an entire surface of the semiconductor substrate 100 having the storage node contact plug 133. A second etch stop layer 137 may be formed on the polysilicon layer 135. The second etch stop layer 137 may be formed of a silicon nitride layer.

       Referring to FIG. 7, the second etch stop layer 137 and the polysilicon layer 135 are sequentially patterned to form landing pads 135a covered by the second etch stop layer patterns 137a. . The landing pads 135a may be patterned in an extended form in the direction of the bit line 127 to be advantageous to the arrangement of the storage node electrodes, which are subsequent processes. As the design rule of the semiconductor device decreases, it is an important problem to arrange the array to have the maximum capacitance while maintaining the separation distance between the storage node electrodes. Can be increased.

       Referring to FIG. 8, a molding layer is formed on the entire surface of the semiconductor substrate 100 having the second etch stop layer patterns 137a. The molding layer may be formed of an insulating layer having an etch selectivity with respect to the second etch stop layer patterns 137a. For example, when the second etch stop layer patterns 137a are formed of a silicon nitride layer, the molding layer may be formed of a silicon oxide layer. The molding layer is patterned to expose the second etch stop layer patterns 137a, and the second etch stop layer patterns 137a are selectively etched sequentially to expose the landing pads 135a. A conductive film is conformally formed on the entire surface of the semiconductor substrate 100 having the molding film pattern. The conductive film may be formed of a conductive polysilicon film. A sacrificial film may be formed of silicon oxide on the conductive film. Thereafter, the upper surface of the molding layer patterns is exposed using a chemical mechanical polishing (CMP) method, and the like, and thus, the conductive layer is separated into respective storage node electrodes 139. The outer and inner surfaces of the storage node electrodes 139 may be exposed by selectively removing the molding layer pattern and the sacrificial layer. When the molding layer pattern and the sacrificial layer are removed, the etching is terminated by the first etch stop layer 131. The storage node electrodes 139 may be formed on the side surface of the selectively etched second etch stop layer pattern 137a. Accordingly, the storage node electrodes 139 may be supported by the second etch stop layer patterns 137a while being in contact with the landing pads 135a. The thickness of the second etch stop layer patterns 137a may be controlled to effectively prevent the storage node electrodes 139 from falling down due to the integration of semiconductor devices.

       Referring to FIG. 9, a capacitor dielectric layer 141 conformally covering the semiconductor substrate 100 having the storage node electrodes 139 is formed. The capacitor dielectric layer 141 may be formed to cover sidewalls of the landing pads 135a, so that the sidewalls of the landing pads 135a may also be used as lower electrodes of the capacitor, thereby increasing capacitance of the capacitor. In the formation of the storage node electrodes 139, the positions of the storage node electrodes 139 are determined according to the molding layer pattern, and thus the capacitor dielectric layer 141 forms one sidewall of the landing pads 135a. It may be covered, or may be formed to cover one or more sidewalls.

       Referring to FIG. 9 again, a semiconductor device having a landing pad according to an embodiment of the present invention will be described.

       9, an active region 101 defined by an isolation layer 103 is provided in a predetermined region of the semiconductor substrate 100. Gate patterns are provided on the semiconductor substrate 100 having the active region 101. The gate patterns may include a gate oxide layer pattern 105, a gate conductive layer pattern 111, and a gate capping layer pattern 113. The gate conductive layer pattern 111 may include a metal silicide layer pattern 109 stacked on the polysilicon layer pattern 107 together with the polysilicon layer pattern 107. The metal silicide layer pattern 109 may be a tungsten silicide layer pattern. The gate capping layer pattern 113 may be a silicon nitride layer. Sidewalls of the gate pattern may be covered by the gate spacer 115.

       A first interlayer insulating layer pattern 117 is disposed between the gate patterns crossing the device isolation layer 103, and a direct contact pad 119 and a berry are disposed between the gate patterns crossing the active region 101. Buried contact pads 121 are disposed. The direct contact pads 119 and buried contact pads 121 may be doped polysilicon layers.

       A second interlayer insulating layer 123 having a bit line contact hole 125 is disposed on the semiconductor substrate 100 having the gate patterns. The bit line 127 is disposed on the second interlayer insulating layer 123 while filling the bit line contact hole 125. A third interlayer insulating layer 129 is disposed on the bit line 127. The second interlayer insulating layer 123 and the third interlayer insulating layer 129 may be silicon oxide layers. A first etch stop layer 131 may be provided on the third interlayer insulating layer 129. Storage node contact plugs 133 are provided to pass through the first etch stop layer 131, the third interlayer insulating layer 129, and the second interlayer insulating layer 123. The storage node contact plugs 133 may be doped polysilicon layers.

       Landing pads 135a are disposed on the storage node contact plugs 133. Second etch stop layer patterns 137a may be further provided on the landing pads 135a. Storage node electrodes 139 may be disposed on side surfaces of the second etch stop layer patterns 137a on the landing pads 135a. The landing pads 135a may have an extended shape in the direction of the bit line 127 for the process margin of the storage node electrodes 139. The storage node electrodes 139 may be conductive polysilicon layers. The first etch stop layer 131 and the second etch stop layer pattern 137a may be silicon nitride layers. The capacitor dielectric layer 141 is conformally disposed to cover at least one sidewall of the storage node electrodes 139 and the landing pads 135a.

       According to the present invention made as described above, it is possible to increase the capacitance by using the landing pad side as part of the capacitor lower electrode. In addition, since the thickness of the second etch stop layer may be adjusted to support the storage node electrode, the bridge may be prevented from being caused by falling of the storage node electrode, thereby improving reliability of the semiconductor device.

Claims (8)

       An interlayer insulating film is formed on the semiconductor substrate,        Forming a storage node contact plug penetrating the interlayer insulating layer;        Forming a landing pad covering the storage node contact plug on the interlayer insulating layer;        Forming a storage node electrode on the landing pad,        And forming a capacitor dielectric film conformally covering at least one sidewall of the landing pad and the storage node electrode.        The method of claim 1,        And forming a first etch stop layer on the interlayer insulating layer after forming the interlayer insulating layer, wherein the storage node contact plug is formed to pass through the first etch stop layer.        The method of claim 1,        Forming the landing pad        A conductive film is formed on the interlayer insulating film having the storage node contact plug,        The method of manufacturing a semiconductor device comprising the step of patterning the conductive film.        The method of claim 3, wherein        And forming a second etch stop layer on the conductive layer, wherein the second etch stop layer is patterned together with the conductive layer.        The method of claim 4, wherein        And the first etch stop layer and the second etch stop layer are formed of a silicon nitride film.        Semiconductor substrates;        An interlayer insulating film disposed on the semiconductor substrate;        A storage node contact plug penetrating the interlayer insulating layer;        A landing pad disposed on the storage node contact plug;        A storage node electrode disposed on the landing pad; And        And a capacitor dielectric layer conformally covering at least one sidewall of the landing pad and the storage node electrode.        The method of claim 6,        And a first etch stop layer disposed on the interlayer insulating layer and disposed to pass through the storage node contact plug.        The method of claim 7, wherein        And a second etch stop layer pattern disposed on the landing pad.

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