KR20060088765A - Apparatus for driving plasma display panel - Google Patents

Abstract

The present invention relates to a driving apparatus of a plasma display panel in which a plurality of subfields for time division gray scale display exist for each frame as a display period, and a reset period, an address period, and a sustain discharge period exist for each subfield. . A plasma display panel driving apparatus according to the present invention is directed to a plasma display panel in which discharge cells are formed in regions where address electrode lines cross with respect to sustain electrode line pairs in which X electrode lines and Y electrode lines are alternately arranged side by side, A plasma display panel driving apparatus in which a plurality of sub-fields for time division gray scale display exist for each frame as a display period, and a reset cycle, an address cycle, and a sustain discharge cycle exist for each sub-field. A temperature sensor detecting a detected temperature of the display panel; And a logic control section for controlling to reduce the intensity of discharge occurring in the address period when the detection temperature is higher than the reference temperature. According to the present invention, when the temperature is higher than the reference temperature, the address pulse and the scan pulse are asynchronous to suppress the address discharge, thereby preventing overdischarge at a high temperature.

Description

Apparatus for driving plasma display panel

1 is an internal perspective view showing the structure of a three-electrode surface discharge plasma display panel according to an embodiment to which the present invention is applied.

2 is a block diagram illustrating a driving apparatus of a plasma display panel as a preferred embodiment of the present invention.

3 is a timing diagram illustrating a method of driving a plasma display panel in which a unit frame is configured by driving a plurality of subfields in the apparatus for driving a plasma display panel of FIG. 2.

4 and 5 are timing diagrams showing driving signals applied to electrode lines of the plasma display panel in unit sub-fields as other embodiments of driving signals by the driving apparatus of the plasma display panel of FIG. 2. .

6 is a block diagram showing a driving apparatus of a plasma display panel as another preferred embodiment of the present invention.

7 and 8 are block diagrams schematically showing logic controllers in the driving apparatus of the plasma display panel of FIG. 6, according to another preferred embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

X _{1 to} X _n : X electrode line, Y ₁ -Y _n : Y electrode line,

A ₁ ~A _m: address electrode lines, PR: a reset period,

PA: address cycle, PS: sustain discharge cycle,

27: temperature sensing unit, 28: timing control unit,

77, 87: load rate detection unit, 78: scan timing adjustment unit,

88: address timing adjusting unit.

The present invention relates to an apparatus for driving a plasma display panel, and more particularly, there are a plurality of subfields for time division gray scale display for each frame as a display period, and a reset period, an address period, and a sustain discharge period for each subfield. The present invention relates to a driving apparatus of a plasma display panel which is present and driven.

As flat panel display devices, plasma display panels (PDPs), which are easy to manufacture large panels, have attracted attention. A plasma display panel is a display device that displays an image by using a discharge phenomenon. In general, a plasma display panel can be classified into a direct current type and an alternating current type according to the type of driving voltage. Due to the long disadvantage, the development of the AC plasma display panel has been made a lot.

An AC plasma display panel includes a three-electrode AC surface discharge type plasma display panel having three electrodes and driven by an AC voltage. A typical three-electrode surface discharge type plasma display panel is composed of a multi-layered plate, which is spatially advantageous because it can provide a thinner, lighter, and wider screen than a conventional cathode ray tube (CRT).

As an example of a conventional plasma display panel, a three-electrode surface discharge plasma display panel, a driving apparatus thereof, and a driving method thereof are disclosed in US Patent No. 6,744,218 (name: Method of driving a plasma display panel in which the). width of display sustain pulse varies). Matters related to the plasma display panel, the driving apparatus, and the driving method disclosed in the above-mentioned US patent are included in the present specification, and a detailed description thereof will be omitted.

The plasma display panel includes a plurality of display cells, and one display cell includes three discharge cells (red, green, and blue), and expresses the gray level of an image by adjusting the discharge state of the discharge cells. .

In order to express the gray scale of the plasma display panel, one frame applied to the plasma display panel may be configured with eight subfields having different emission counts to express 256 gray scales. That is, in the case where the image is to be displayed with 256 gray levels, the frame period (16.67 ms) corresponding to 1/60 second is divided into eight subfields.

Each of the subfields is divided into a reset period for uniformly generating a discharge, an address period for selecting a display cell, and a sustain discharge period for expressing gray scale according to the number of discharges. The length of the period in which the reset period and the address period are combined is the same in all the subfields, and the sustain discharge period is different in length for each subfield. The number of discharge pulses occurring in the sustain discharge cycle of the subfields increases in the order of 1,2,4,8,16,32,128. The number of discharges of the discharge cells is determined according to the number of discharge pulses. In this way, 256 levels of gray scale can be expressed by adjusting the number of discharges in the sustain discharge period in the subfields.

In the reset period, all the discharge cells in the display panel are initialized, in the address period, the discharge cells to emit light by generating an address discharge only in the discharge cells to emit light are selected, and in the sustain discharge period, to emit light. Only the selected discharge cells cause sustain discharge to emit light.

In a typical plasma display panel driving apparatus, a scan pulse is sequentially applied to Y electrode lines in an address period, and an address pulse is applied only to address electrode lines corresponding to discharge cells to emit light for each scan pulse. Allow address discharge to occur between the pulse and the address pulse.

At this time, for effective address discharge, the timing at which the address pulse and the scan pulse are applied is synchronized, so that the address discharge is caused by the voltage difference between the address pulse and the scan pulse, so that the wall charges necessary for the sustain discharge are formed only in the desired discharge cells. To help.

However, depending on the temperature characteristics of the plasma display panel, when the temperature rises, secondary electron emission of MgO may increase, thereby causing overdischarge, and thus, wall charges may be excessively formed than in a normal case. Therefore, there may be a problem that overdischarge may occur in the subsequent sustain discharge, whereby the displayed luminance may be too bright than the luminance to be displayed. In particular, as in the case of expressing full white, the temperature may increase when the ratio of discharge cells to emit light among all the discharge cells is large or when sustain discharge is performed in all subfields, and over discharge may occur at such a high temperature. There is a problem.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems. When the temperature of the plasma display panel is detected and the temperature is higher than the reference temperature, the address pulse and the scan pulse are asynchronous to suppress the address discharge, thereby preventing over discharge at high temperature. It is an object of the present invention to provide a plasma display panel drive device.

In the plasma display panel driving apparatus according to the present invention for achieving the above object, the discharge cells in the region where the address electrode lines intersect with respect to the pair of sustain electrode line in which X electrode lines and Y electrode lines are alternately arranged side by side. For the plasma display panel to be formed, there are a plurality of sub-fields for time division gray scale display for each frame as the display period, and a reset period, an address period, and a sustain discharge period are present for each sub-field and driven. An apparatus for driving a splay panel, comprising: a temperature sensing unit for detecting a detected temperature of a plasma display panel; And a logic control section for controlling to reduce the intensity of discharge occurring in the address period when the detection temperature is higher than the reference temperature.

According to another aspect of the present invention, a plasma display panel driving apparatus includes a plasma display panel in which discharge cells are formed in regions where address electrode lines cross with respect to sustain electrode line pairs in which X electrode lines and Y electrode lines are alternately arranged side by side. For a frame display panel driving apparatus, there are a plurality of sub-fields for time division gray scale display for each frame as a display period, and a reset cycle, an address cycle, and a sustain discharge cycle exist for each sub-field. A load rate sensing unit for sensing a load ratio which is a ratio of the number of discharge cells to be displayed with respect to all discharge cells in a sub-field; And a logic control section for controlling to reduce the intensity of discharge occurring in the address period when the load rate is higher than the reference load rate.

According to the present invention, when the temperature is higher than the reference temperature, the address pulse and the scan pulse are asynchronous to suppress the address discharge, thereby preventing overdischarge at a high temperature.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is an internal perspective view showing the structure of a three-electrode surface discharge plasma display panel according to an embodiment to which the present invention is applied.

Referring to the drawings, between the front and rear glass substrates 10 and 13 of the surface discharge plasma display panel 1, the address electrode lines A _{R1 to} A _Bm , the dielectric layers 11 and 15, and the Y electrode Lines Y ₁ to Y _n , X electrode lines X ₁ to X _n , a fluorescent layer 16, a partition 17, and a magnesium monoxide (MgO) layer 12 as a protective layer are provided.

The address electrode lines A _{R1 to} A _Bm are formed in a predetermined pattern on the front side of the rear glass substrate 13. The lower dielectric layer 15 is applied to the entire surface in front of the address electrode lines A _{R1 to} A _Bm . In front of the lower dielectric layer 15, barrier ribs 17 are formed in a direction parallel to the address electrode lines A _{R1 to} A _Bm . The partition walls 17 function to partition the discharge area of each discharge cell 14 and to prevent optical cross talk between the discharge cells 14. The fluorescent layer 16 is formed on the inner surface of the space formed between the lower dielectric layer 15 and the partition walls 17 formed on the rear glass substrate 13.

The X electrode lines X ₁ to X _n and the Y electrode lines Y ₁ to Y _n have a constant pattern on the rear side of the front glass substrate 10 to be orthogonal to the address electrode lines A _{R1 to} A _Bm . Is formed. Each intersection sets a corresponding discharge cell 14. Each X electrode line (X _{1 to} X _n ) and each Y electrode line (Y _{1 to} Y _n ) are combined with a transparent electrode line made of a transparent conductive material such as indium tin oxide (ITO) and a metal electrode line for increasing conductivity. Is formed. Here, the X electrode lines X ₁ to X _n become sustain electrodes in the respective discharge cells 14, and the Y electrode lines Y ₁ to Y _n correspond to scan electrodes in the respective discharge cells 14. And become an address electrode in each discharge cell 14 of each of the address electrode lines A _{R1 to} A _Bm .

2 is a block diagram illustrating a driving apparatus of a plasma display panel as a preferred embodiment of the present invention.

Referring to the drawing, the driving device 2 of the plasma display panel 1 includes an image processor 26, a logic controller 22, an address driver 23, an X driver 24, and a Y driver 25. . The image processing unit 26 converts an external analog image signal into a digital signal, for example, an internal image signal, for example, 8-bit red (R), green (G), and blue (B) image data, a clock signal, vertical and horizontal, respectively. Generate sync signals. The logic controller 22 generates driving control signals S _A , S _Y , and S _X according to an internal image signal from the image processor 26.

In this case, the driving unit such as the address driver 23, the X driver 24, and the Y driver 25 receives input from the driving control signals S _A , S _Y , and S _X , and generates respective driving signals. The applied driving signal to each of the electrode lines.

That is, the address driver 23 processes the address signal S _A among the drive control signals S _A , S _Y , and S _X from the logic controller 22 to generate a display data signal, and generates the displayed display. The data signal is applied to the address electrode lines. The X driver 24 processes the X driving control signal S _X from the driving control signals S _A , S _Y , and S _X from the logic controller 22 and applies the X driving control signal S _X to the X electrode lines. The Y driver 25 processes the Y driving control signal S _Y from the driving control signals S _A , S _Y , and S _X from the logic controller 22 and applies the Y driving control signal S _Y to the Y electrode lines.

The driving apparatus of the plasma display panel according to the present invention includes a temperature sensing unit 27; And a logic controller 22 is preferable. The temperature detector 27 detects a detection temperature of the plasma display panel. When the detection temperature is higher than the reference temperature, the logic controller 22 controls to reduce the intensity of discharge generated in the address period.

The temperature detector 27 detects a detected temperature of the plasma display panel. The temperature detector 27 measures whether the temperature of the panel is enough to affect the address discharge. It is desirable to. To this end, a temperature sensing unit 27 may be installed to directly contact the rear surface of the panel, and as the temperature sensing unit 27, conventional temperature measuring apparatuses using a thermocouple principle may be used. In another embodiment, a bimetal that may generate a signal when the temperature is higher than the reference temperature may be used.

 When the detection temperature is higher than the reference temperature, the logic control unit 28 controls to reduce the intensity of discharge generated in the address period. The logic control unit 22 applies the address pulse when the detection temperature is higher than the reference temperature. It is preferable to have a timing controller 28 for controlling the time and the time for applying the scan pulse to be asynchronous.

That is, when the temperature rises, secondary electron emission of MgO may increase, thereby causing overdischarge, and thus, wall charges may be excessively formed than in the usual case, as shown in the timing diagram shown in FIG. 4 or 5. The timing of the scan pulse and the address pulse can be controlled to suppress overdischarge at high temperatures.

In this case, the scan pulse and the address pulse may have the same pulse width, and when the detection temperature is higher than the reference temperature, the timing controller 28 controls the address pulse to advance or lag behind the scan pulse by a predetermined time interval, The time to apply the pulse and the time to apply the scan pulse can be controlled to be asynchronous. Therefore, the intensity of the discharge during the address discharge can be weakened by that much.

In addition, according to the exemplary embodiment, as illustrated in FIG. 2, the timing controller 28 may be configured to be included in the logic controller 22.

3 is a timing diagram illustrating a method of driving a plasma display panel in which a unit frame is configured by driving a plurality of subfields in the apparatus for driving a plasma display panel of FIG. 2.

Referring to the drawing, the unit frame FR is divided into eight subfields SF1 to SF8 to realize time division gray scale display. Each subfield SF1 to SF8 is divided into reset periods R1 to R8, address periods A1 to A8, and sustain discharge periods S1 to S8.

The luminance of the plasma display panel is proportional to the length of the sustain discharge periods S1 to S8 occupied in the unit frame. The length of the sustain discharge cycles S1 to S8 occupied in the unit frame is 255T (T is the unit time). At this time, a time corresponding to 2 ⁿ is set in the sustain discharge period Sn of the nth subfield SFn. Accordingly, if the subfield to be displayed among the eight subfields is appropriately selected, 256 gray levels may be displayed including all zero (zero) grays not displayed in any of the subfields.

4 and 5 are timing diagrams showing driving signals applied to electrode lines of the plasma display panel in unit sub-fields as other embodiments of driving signals by the driving apparatus of the plasma display panel of FIG. 2. .

4 and 5, reference numeral S _AR1..ABm denotes a drive signal applied to each address electrode line (A _R1 to A _{Bm in} FIG. 1), and S _X1..Xn denotes X electrode lines (X in FIG. ₁ to X _n ), and S _Y1 to S _Yn indicate a driving signal to each Y electrode line (Y ₁ to Y _{n in} FIG. 1).

Referring to the drawings, in the reset period PR of the unit sub-field SF, first, the voltage applied to the X electrode lines X ₁ to X _n is converted from the ground voltage V _G to the second voltage V _S. For example, it continuously increases to 155 volts (V). Here, the ground voltage V _G is applied to the Y electrode lines Y ₁ to Y _n and the address electrode lines A _R1 to A _Bm . Accordingly, between the X electrode lines X ₁ to X _n and the Y electrode lines Y ₁ to Y _n , and the X electrode lines X ₁ to X _n and the address electrode lines A ₁ to A _A weak discharge occurs between _m ) and negative wall charges are formed around the X electrode lines X ₁ to X _n .

The Next, Y electrode lines (Y ₁ ~ Y _n) voltage to the second voltage applied to the (V _S), for example, the third voltage (V _SET than the second voltage (V _S) from 155 volt (V) The maximum voltage (V _SET + V _S ), which is as high as), continues to rise to, for example, 355 volts (V). Here, the ground voltage V _G is applied to the X electrode lines X ₁ to X _n and the address electrode lines A _R1 to A _Bm . Accordingly, a weak discharge occurs between the Y electrode lines Y ₁ to Y _n and the X electrode lines X ₁ to X _n , while the Y electrode lines Y ₁ to Y _n and the address electrode lines are formed. Weak discharge occurs between (A _R1 and A _Bm ).

Next, while the voltage applied to the X electrode lines X ₁ to X _n is maintained at the second voltage V _S , the voltage applied to the Y electrode lines Y ₁ to Y _n is second. It continues to fall from voltage V _S to ground voltage V _G. Here, the ground voltage V _G is applied to the address electrode lines A _R1 to A _Bm .

Leads in the address period (PA), the address is applied to a display data signal of the address pulse to the electrode line, the second voltage (V _S) lower fourth voltage (V _SCAN) to bias the Y-electrode line than the (Y ₁ As the scan signals of the scan pulses of the ground voltage V _G are sequentially applied to ˜Y _n ), smooth addressing may be performed.

At this time, the display data signal applied to each of the address electrode lines A _R1 to A _{Bm is} supplied with the positive address voltage V _A when the discharge cell is selected and the ground voltage V _G when the discharge cell is not selected. Accordingly, when the display data signal of the positive address voltage V _A is applied while the scan pulse of the ground voltage V _G is applied, wall charges are formed by the address discharge in the corresponding discharge cell. Wall charges do not form. In addition, the second voltage V _S is applied to the X electrode lines X ₁ to X _{n for} more accurate and efficient address discharge.

In this case, it is preferable that the scan pulse and the address pulse have the same pulse width. When the detection temperature is lower than the reference temperature, the scan pulse and the address pulse are synchronized so that a sufficient positive wall charge is provided to the Y electrode after the address discharge. It is desirable to allow accumulation so that subsequent sustain discharges can be stabilized.

However, in the case of high temperature, as shown in FIGS. 4 and 5, the over-discharge according to the temperature characteristics can be suppressed by making the scan pulse and the address pulse asynchronous. That is, so as to advance as a as an address pulse a predetermined time period than the scan pulse (t _AS) at predetermined time intervals (t _AS) than or so earlier, the scan pulse, as illustrated in Figure 5, the address pulse as shown in Figure 4 You can do it. At this time, the asynchronous time interval t _AS may be tens of ns to hundreds of ns.

At this time, the asynchronous time t _AS may vary according to the setting of the reference temperature, and when the reference temperature rises, the asynchronous time t _AS may increase by that much. In other words, it is desirable to find a temperature over-discharge is worse find points to obtain the proper discharge its temperature to the reference temperature, while adjustment asynchronous time (t _AS) accordingly, setting an asynchronous time (t _AS) .

In the sustain discharge period PS, the display sustain pulse of the second voltage V _S is alternately applied to all the Y electrode lines Y ₁ to Y _n and the X electrode lines X ₁ to X _n . In the corresponding address period PA, a discharge for maintaining the display occurs in discharge cells in which wall charges are formed. That is, when the detection temperature is lower than the reference temperature, the sustain discharge occurs with the help of the wall charge accumulated by the discharge between the synchronized address pulse and the scan pulse, and when the detection temperature is higher than the reference temperature, the asynchronous address pulse and By the discharge between the scan pulses, a constant sustain discharge can be obtained regardless of the temperature effect due to the temperature change.

As described above, according to the present invention, only the timing of the address pulse and the scan pulse is adjusted according to the temperature, so that the discharge is more easily controlled. In addition, by the driving apparatus capable of controlling the timing of the address pulse and the scan pulse according to the present invention, the plasma display panel having stable discharge characteristics can be obtained regardless of the temperature change only by timing control in the logic controller.

6 is a block diagram showing a driving apparatus of a plasma display panel as another preferred embodiment of the present invention. 7 and 8 are block diagrams schematically showing logic controllers in the driving apparatus of the plasma display panel of FIG. 6, according to another preferred embodiment of the present invention.

Referring to the drawings, the plasma display panel driving apparatus includes an address electrode line for sustain electrode line pairs in which X electrode lines X ₁ to X _n and Y electrode lines Y ₁ to Y _n are alternately arranged side by side. For a plasma display panel in which discharge cells are formed in a region where the fields A _{R1 to} A _Bm intersect, a plurality of sub-fields for time division gray scale display exist for each frame as a display period, and for each of the sub-fields. The reset period PR, the address period PA, and the sustain discharge period PS exist and are driven. At this time, the driving device of the plasma display panel includes a load rate sensing unit (77, 87 of Figs. 7 and 8); And a logic controller 32.

The load rate detectors 77 and 87 of FIGS. 7 and 8 detect a load rate which is a ratio of the number of discharge cells to be displayed to all discharge cells in the sub-field. When the load ratio is higher than the reference load ratio, the logic controller 32 controls to reduce the intensity of the address discharge occurring in the address period. The adjustment of the address discharge according to the present invention may be performed by the timing controllers 78 and 88. The scan timing controller 78 or the address timing controller 88 may be adjusted depending on whether to adjust the scan pulse timing or the address pulse timing. )

That is, the timing of the scan pulse applied to the Y electrode line by the scan timing adjusting unit 78 or the timing of the address pulse applied to the address electrode line by the address timing adjusting unit 88 is adjusted. Adjust the scan pulse and address pulse asynchronously. In particular, the degree of discharge may be controlled by adjusting the asynchronous time (t _{AS in} FIGS. 4 and 5) of the scan pulse and the address pulse. In addition, the asynchronous time (t _AS of FIGS. 4 and 5) may be adjusted according to the setting of the reference temperature.

The load rate detectors 77 and 87 may be configured to be included in the logic controller 32 as illustrated in FIGS. 7 and 8. For details of the components of the driving apparatus of the plasma display panel of FIG. 6, the description of FIG. 2 is referred to.

Referring to the drawings, the present embodiment is configured such that the load factor detection units 77 and 87 are included in the logic control unit 32 as shown in FIGS. 7 and 8. Hereinafter, the description of the present invention is mainly made with reference to FIG. 7, and the same reference numerals as those of FIG. 7 are used for the same components that perform the same functions as those of FIG. 7.

The logic controller according to the present invention includes a clock buffer 55, a synchronization controller 526, a gamma correction unit 51, an error diffusion unit 512, a first-in first-out memory 511, and a subfield. Generator 521, subfield matrix 522, matrix buffer 523, memory controller 524, frame-memory (RFM1, ..., BFM3), rearrangement 525, average signal level Detector 53a, power controller 53, EEPROM 54a, I2C serial communication interface 54b, timing-signal generator 54c, XY controller 54, load factor detector 77, and scan A timing adjusting unit 78 or an address timing adjusting unit 88.

The clock buffer 55 converts the 26-megahertz (MHz) clock signal CLK26 from the image processor (36 in FIG. 8) into a 40-megahertz (MHz) clock signal CLK40 and outputs the converted signal. The synchronization adjustment unit 526 includes a 40-megahertz (MHz) clock signal CLK40 from the clock buffer 55, an initialization signal RS from the outside, and a horizontal synchronization signal from the image processing unit (36 in FIG. 8). (HSYNC) and the vertical sync signal VSYNC are input. The synchronization adjusting unit 526 outputs the horizontal synchronization signals HSYNC1, HSYNC2, and HSYNC3 in which the input horizontal synchronization signal HSYNC is delayed by a predetermined number of clocks, respectively, while the input vertical synchronization signal VSYNC is predetermined. The vertical synchronization signals VSYNC2 and VSYNC3 are respectively delayed by the number of clocks.

The image data R, G, and B input to the gamma correction unit 51 has a reverse nonlinear input / output characteristic in order to correct the nonlinear input / output characteristics of the cathode ray tube. Therefore, the gamma correction unit 51 processes the image data R, G, and B of the reverse nonlinear input and output characteristics to have the linear input and output characteristics. The error diffusion unit 512 reduces the data transmission error by using the first-in first-out memory 511 to move the position of the maximum sign bit that is the boundary bit of the image data R, G, and B.

The subfield generator 521 converts 8-bit image data R, G, and B into 8-bit image data R, G, and B, respectively, corresponding to the number of subfields. For example, when grayscale driving is performed with 14 subfields in a unit frame, after converting 8-bit image data R, G, and B into 14-bit image data R, G and B, respectively, In order to reduce a data transmission error, 16 bits of image data R, G, and B are output by adding invalid data '0' of a maximum value bit (MSB) and a minimum value bit (Least Significant Bit).

The subfield matrix unit 522 rearranges 16-bit video data R, G, and B into which data of different subfields is simultaneously input, so that data of the same subfield is simultaneously output. The matrix buffer unit 523 processes the 16-bit image data R, G, and B from the subfield matrix unit 522 and outputs the 32-bit image data (R, G, B).

The memory control unit 524 may include a red memory control unit for controlling three red frame R memories (RFM1, RFM2, and RFM3), and three green (G) frame memory memories (GFM1, GFM2, A green memory control unit for controlling GFM3) and a blue memory control unit for controlling the three blue frame B memories (BFM1, BFM2, BFM3). Frame data from the memory controller 524 is continuously output in units of frames and input to the rearrangement unit 525.

In the drawing, reference numeral EN denotes an enable signal generated from the XY controller 54 and input to the memory controller 524 to control the data output of the memory controller 524. In addition, the reference numeral S _SYNC is generated from the XY control unit 54 to control data input / output in units of 32-bit slots in the memory control unit 524 and the rearrangement unit 525, and thus the memory control unit 524 and the rearrangement unit. The slot synchronization signal input to 525 is indicated. The rearrangement unit 525 rearranges and outputs 32-bit image data R, G, and B from the memory control unit 524 to match the input format of the address driver 33 (FIG. 6).

Meanwhile, the average signal level detection unit 53a detects the average signal level ASL in units of frames from the 8-bit image data R, G, and B from the error diffusion unit 512, respectively, and transmits the average signal level ASL to the power control unit 53. Enter it. The power control unit 53 generates the number of discharge control data APC corresponding to the average signal-level ASL input from the average signal level detection unit 53a, thereby making automatic power consumption constant in each frame. Perform the function of control. In the present embodiment, the power control unit 53 performs the automatic power control function when the load rate of the frame exceeds 30%. In the YEPROM 54a, timing control data according to a driving sequence of the X electrode lines (X1 to Xn in FIG. 1) and the Y electrode lines (Y1 to Yn in FIG. 1) are stored. The discharge recovery control data APC from the power control unit 53 and the timing control data from EPIROM 54a are input to the timing-signal generator 54c via the I ² C serial communication interface 54b. The timing-signal generator 54c operates according to the input discharge count control data APC and the timing control data to generate the timing-signal. The XY control unit 54 operates in accordance with the timing-signal from the timing-signal generator 54c to output the X drive control signal S _X and the Y drive control signal S _Y.

The load rate detection unit 77 detects the load rate and inputs it to the scan timing adjusting unit 78 to adjust the timing of the scan pulse applied to the Y electrode according to the load rate. In this case, the load ratio may be a ratio of the number of discharge cells to be displayed with respect to all the discharge cells in the sub-field. The load ratio may be used when the average signal level detector 53a detects the average signal level. According to an embodiment, the load ratio may mean an average load ratio of load rates of each subfield of a corresponding frame, and the load ratio of each subfield is plasma. It may mean a ratio of the number of cells to be displayed to the number of all cells of the display panel. In this case, the load ratio may be directly obtained from data output from the error diffusion unit 512.

In the case where over discharge can occur due to a large number of discharge cells in which all discharge cells are discharged and the panel temperature rises, that is, when the load ratio is greater than the reference load ratio, the scan pulse and the address pulse are asynchronous to suppress over discharge at high temperature. In addition, by controlling the asynchronous time (t _AS ) according to the reference load rate, it can be found that the proper discharge can be made at a high temperature. Based on these criteria, the reference load factor can be set.

In this case, when the load ratio is higher than the reference load ratio, the scan timing adjusting unit 78 controls the scan pulse to advance or fall behind the address pulse by a predetermined time interval t _AS to suppress over discharge at high temperature. have.

That is, when the load rate detected by the load rate detection unit 77 is higher than the reference load rate, the scan timing applied to the Y electrode line by the scan timing adjusting unit 78 may advance or fall behind the address pulse by an asynchronous time t _AS . A signal can be generated and input to the timing control signal generator 54c or the XY control unit 54 so that the scan pulse is asynchronous with the address pulse asynchronous time t _AS .

In addition, when the load rate is higher than the reference load rate, the address timing adjusting unit 88 may control the address pulse to advance or fall behind the scan pulse by a predetermined time interval t _AS to suppress overdischarge at high temperature.

That is, when the load rate detected by the load rate detection unit 87 is higher than the reference load rate, the address pulse applied to the address electrode line by the address timing adjusting unit 88 may precede or fall behind the scan pulse by an asynchronous time t _AS . A signal may be generated and input to the memory controller 524 or the rearranger 525 so that the scan pulse is asynchronous with the address pulse asynchronous time t _AS . In this case, the address timing controller 88 may receive the enable signal EN and the slot synchronization signal S _SYNC output from the XY controller 54 to generate an asynchronous signal.

In addition, according to the exemplary embodiment, the asynchronous signal output from the address timing adjusting unit 88 is input to the address drive of the address driving unit 33 so that the address pulse precedes the scan pulse by the asynchronous time t _AS in the address drive. You may be able to fall behind.

Accordingly, the address discharge can be more easily controlled by adjusting only the timing at which the address pulse and the scan pulse are applied.

1 to 3, the plasma display panel, a driving device, and a driving method thereof are just one embodiment to which the driving device of the plasma display panel according to the present invention can be applied, and various other plasma display panels and driving thereof are shown. Applicable to the device and the driving method.

According to the plasma display panel driving apparatus according to the present invention, when the temperature of the plasma display panel is detected and the temperature is higher than the reference temperature, the address pulse and the scan pulse are asynchronous to suppress the address discharge and to prevent over discharge at high temperature. Can be.

In addition, the size of the address discharge can be controlled by adjusting the asynchronous time widths of the address pulse and the scan pulse, and the amount of wall charge accumulated by the address discharge can be adjusted.

In addition, it is possible to prevent the luminance at a specific gradation from becoming too large due to overdischarge at high temperature.

Although the present invention has been described with reference to one embodiment shown in the accompanying drawings, it is merely an example, and those skilled in the art may realize various modifications and equivalent other embodiments therefrom. I can understand. Accordingly, the true scope of protection of the invention should be defined only by the appended claims.

Claims (10)

For plasma display panels in which discharge cells are formed in regions where address electrode lines cross with respect to sustain electrode line pairs in which X electrode lines and Y electrode lines are alternately arranged side by side, a plurality of time division gray scale displays for each frame as a display period In the driving apparatus of the plasma display panel in which there are sub-fields of, and each of the sub-fields has a reset period, an address period, and a sustain discharge period. A temperature sensor detecting a detection temperature of the plasma display panel; And And a logic controller for controlling the intensity of discharge generated in the address period when the detection temperature is higher than the reference temperature. The method of claim 1, In the discharge cell to emit light by applying an address pulse to the address electrode lines corresponding to the discharge cells to emit light for each of the scan pulse, while sequentially applying the scan pulse to the Y electrode lines in the address period To cause an address discharge, And a timing control unit configured to control the logic control unit to synchronize the time for applying the address pulse and the time for applying the scan pulse when the detection temperature is higher than a reference temperature. The method of claim 2, And the scan pulse and the address pulse have the same pulse width. The method of claim 2, And the timing controller controls the address pulse to precede the scan pulse by a predetermined time interval when the detection temperature is higher than the reference temperature. The method of claim 2, And the timing controller controls the scan pulse to advance the address pulse by a predetermined time interval when the detection temperature is higher than the reference temperature. For plasma display panels in which discharge cells are formed in regions where address electrode lines cross with respect to sustain electrode line pairs in which X electrode lines and Y electrode lines are alternately arranged side by side, a plurality of time division gray scale displays for each frame as a display period In the driving apparatus of the plasma display panel in which there are sub-fields of, and each of the sub-fields has a reset period, an address period, and a sustain discharge period. A load ratio detector for detecting a load ratio which is a ratio of the number of discharge cells to be displayed with respect to all discharge cells in the sub-field; And And a logic controller for controlling the intensity of discharge generated in the address period when the load ratio is higher than a reference load ratio. The method of claim 6, In the discharge cell to emit light by applying an address pulse to the address electrode lines corresponding to the discharge cells to emit light for each of the scan pulse, while sequentially applying the scan pulse to the Y electrode lines in the address period To cause an address discharge, And a timing control unit configured to control the logic control unit to synchronize the time for applying the address pulse and the time for applying the scan pulse when the load ratio is higher than a reference load ratio. The method of claim 7, wherein And the scan pulse and the address pulse have the same pulse width. The method of claim 7, wherein And the timing controller is an address timing adjuster that controls the address pulse to advance or fall behind the scan pulse by a predetermined time interval when the load ratio is higher than a reference load ratio. The method of claim 7, wherein And a timing control unit configured to control the scan pulse to advance or lag behind the address pulse by a predetermined time interval when the load ratio is higher than a reference load ratio.

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