KR100637247B1 - Method for driving display panel - Google Patents

Abstract

A driving method of a display panel is provided to restrict low discharge caused due to the time delay of address discharge, and to improve discharge uniformity by gradually increasing pre-scan pulse level from a discharge cell executing the address discharge for the first time to a discharge cell generating the address discharge later. A method for driving a display panel having discharge cells formed by a sustain electrode and an address electrode, by forming plural sub-fields(SF) according to each weighted value of gray scales to time-division display the gray scales for every frame that is a display period, and a reset period(PR), an address period(PA), and a sustain discharge period(PS) for each sub-field: applies scan pulse in sequence to the sustain electrode from one end of the display panel to the other end thereof during the address period, and selects the discharge cell to be displayed by applying data pulse to the address electrode of the selected discharge cell. Pre-scan pulse(Vpre1~Vpre3) executing discharge between the sustain electrode and the address electrode is applied to the sustain electrode before the scan pulse is applied. The level of the pre-scan pulse is gradually increased according to an order of the sustain electrodes to which the scan pulse is applied.

Description

Method for driving display panel {Method for driving display panel}

1 is a perspective view illustrating a structure of a three-electrode surface discharge type plasma display panel according to an embodiment to which a plasma display panel driving method according to the present invention is applied.

2 is a block diagram illustrating a driving apparatus of a plasma display panel as an embodiment to which a plasma display panel driving method according to the present invention is applied.

3 is a timing diagram illustrating a driving method of driving a unit frame composed of a plurality of sub-fields in the method of driving a plasma display panel according to the present invention.

4 is a timing diagram illustrating an embodiment of driving signals applied to electrode lines of the plasma display panel in successive sub-fields according to the present invention.

<Explanation of symbols for the main parts of the drawings>

1: plasma display panel, 10: front glass substrate,

11, 15: dielectric layer, 12: protective layer,

13: rear glass substrate, 14: discharge space,

16: fluorescent layer, 17: bulkhead,

22: logic controller, 23: address driver,

24: X drive unit, 25: Y drive unit,

X _{1 to} X _n : X electrode line, Y ₁ -Y _n : Y electrode line,

A ₁ ~A _m: address electrode lines, SF1~SF8: sub-field.

The present invention relates to a method of driving a display panel, and more particularly, there are a plurality of subfields for time division gray scale display for each frame as a display period, and a reset period, an address period, and a sustain discharge period for each subfield. The present invention relates to a driving method of a display panel which is driven.

As flat panel display devices, plasma display panels (PDPs), which are easy to manufacture large panels, have attracted attention. A plasma display panel is a display device that displays an image by using a discharge phenomenon. In general, a plasma display panel can be classified into a direct current type and an alternating current type according to the type of driving voltage. Due to the disadvantages, the development of the AC plasma display panel has been made a lot.

An AC plasma display panel includes a three-electrode AC surface discharge type plasma display panel having three electrodes and driven by an AC voltage. The conventional three-electrode surface discharge plasma display panel is composed of a multi-layered plate, and is thinner, lighter, and wider than a conventional cathode ray tube (CRT), which is spatially advantageous.

As an example of a conventional plasma display panel, a three-electrode surface discharge plasma display panel, a driving apparatus thereof, and a driving method thereof are disclosed in US Patent No. 6,744,218 (name: Method of driving a plasma display panel in which the). width of display sustain pulse varies).

The plasma display panel includes a plurality of display cells, and one display cell includes three discharge cells (red, green, and blue), and expresses the gray level of an image by adjusting the discharge state of the discharge cells. .

In the plasma display panel, discharge cells are formed in regions in which X and Y electrodes and alternately arranged address electrodes are alternately arranged side by side. A plurality of sub-fields according to gray scale weights exist for each time frame grayscale display, and a reset cycle, an address cycle, and a sustain discharge cycle exist for each sub-field, thereby driving the plasma display panel. do.

At this time, all the discharge cells are initialized in the reset cycle. In the next address period, scan pulses are sequentially applied to each of the Y electrodes, and data pulses synchronized with the scan pulses are applied to the address electrodes corresponding to the discharge cells to be displayed among the discharge cells, thereby displaying the discharges. Select the cell. In the subsequent sustain discharge cycle, sustain pulses are applied to the X electrode and the Y electrode so that the sustain discharge can occur only in the discharge cells to be displayed, thereby expressing the image.

After a wall charge condition suitable for generating an address discharge is initialized in a reset period, address discharge is sequentially generated from one end of the panel to the other end in the address period, and then the discharge cell that performs the first address discharge and the address discharge last. There is a time delay between the discharge cells by the time required for the address period.

At this time, as time passes after the reset discharge, wall charges due to the reset discharge are disturbed, and low discharge of the address discharge due to the wall charge loss occurs. In addition, the intensity of the discharge may vary between the address discharge immediately after the reset discharge and subsequent address discharges. In particular, the difference between the address discharge immediately after the reset discharge and the address discharge at the end can have a significant effect on the discharge, resulting in a nonuniform discharge between the discharge cells on the panel.

The present invention is to solve the above problems, to provide a method of driving a display panel that can prevent low discharge according to the time delay of the address discharge in each discharge cell in the panel, and improve the discharge uniformity. The purpose.

The display panel driving method according to the present invention for achieving the above object, for each display frame as a display period for the display panel in which the discharge cells are formed by the sustain electrode and the address electrode, each gray scale weight There are a plurality of sub-fields, and each of the sub-fields has a reset period, an address period, and a sustain discharge period.

In the address period, scan pulses are sequentially applied to the sustain electrodes from one end of the panel to the other end, and data pulses are applied to the address electrodes of the discharge cells to be displayed among the discharge cells. Select the discharge cell to be.

Before the scan pulse is applied, a pre-scan pulse causing discharge between the address electrode is applied to the sustain electrode, and the level of the pre-scan pulse is sequentially increased according to the order of the sustain electrode to which the scan pulse is applied. .

Discharge cells are formed in an area where the address electrode lines intersect with respect to the sustain electrode pairs in which the X and Y electrodes are alternately arranged side by side, and the display panel biases the X electrode to a first level In the state where the Y electrode is biased to the second level, scan pulses of the third level are sequentially applied.

Preferably, the prescan pulse is applied to the Y electrode.

Preferably, the level of the prescan pulse is higher than the second level.

While the pre-scan pulse is applied, it is preferable that the address electrode is maintained at the fourth level and the X electrode is maintained at the second level.

According to the present invention, low discharge due to time delay of address discharge in each discharge cell in the panel can be prevented, and discharge uniformity can be improved.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a perspective view illustrating a structure of a three-electrode surface discharge type plasma display panel according to an embodiment to which a plasma display panel driving method according to the present invention is applied.

Referring to the drawings, between the front and rear glass substrates 10 and 13 of the surface discharge plasma display panel 1, the address electrode lines A _{R1 to} A _Bm , the dielectric layers 11 and 15, and the Y electrode line (Y ₁ to Y _n ), X electrode lines (X ₁ to X _n ), fluorescent layer 16, partition wall 17, and magnesium monoxide (MgO) layer 12 as a protective layer are provided.

The address electrode lines A _{R1 to} A _Bm are formed in a predetermined pattern on the front side of the rear glass substrate 13. The lower dielectric layer 15 is applied to the entire surface in front of the address electrode lines A _{R1 to} A _Bm . In front of the lower dielectric layer 15, barrier ribs 17 are formed in a direction parallel to the address electrode lines A _{R1 to} A _Bm . The partition walls 17 function to partition the discharge area of each discharge cell 14 and to prevent optical cross talk between the discharge cells 14. The fluorescent layer 16 is formed on the inner surface of the space formed between the lower dielectric layer 15 and the partition walls 17 formed on the rear glass substrate 13.

The X electrode lines X ₁ to X _n and the Y electrode lines Y ₁ to Y _n have a constant pattern on the rear side of the front glass substrate 10 to be orthogonal to the address electrode lines A _{R1 to} A _Bm . Is formed. Each intersection sets a corresponding discharge cell 14. Each X electrode line (X _{1 to} X _n ) and each Y electrode line (Y _{1 to} Y _n ) are combined with a transparent electrode line made of a transparent conductive material such as indium tin oxide (ITO) and a metal electrode line for increasing conductivity. Is formed. Here, the X electrode lines X ₁ to X _n become sustain electrodes in the respective discharge cells 14, and the Y electrode lines Y ₁ to Y _n correspond to scan electrodes in the respective discharge cells 14. And become an address electrode in the discharge cell 14 of each of the address electrode lines A _{R1 to} A _Bm .

2 is a block diagram illustrating a driving apparatus of a plasma display panel as an embodiment to which a plasma display panel driving method according to the present invention is applied.

Referring to the drawing, the driving device 2 of the plasma display panel 1 includes an image processor 26, a logic controller 22, an address driver 23, an X driver 24, and a Y driver 25. . The image processing unit 26 converts an external analog image signal into a digital signal, for example, an internal image signal, for example, 8-bit red (R), green (G), and blue (B) image data, a clock signal, vertical and horizontal, respectively. Generate sync signals. The logic controller 22 generates driving control signals S _A , S _Y , and S _X according to an internal image signal from the image processor 26.

In this case, the driving unit such as the address driver 23, the X driver 24, and the Y driver 25 receives input from the driving control signals S _A , S _Y , and S _X , and generates respective driving signals. The applied driving signal to each of the electrode lines.

That is, the address driver 23 processes the address signal S _A among the drive control signals S _A , S _Y , and S _X from the logic controller 22 to generate a display data signal, and generates the displayed display. The data signal is applied to the address electrode lines. The X driver 24 processes the X driving control signal S _X from the driving control signals S _A , S _Y , and S _X from the logic controller 22 and applies the X driving control signal S _X to the X electrode lines. The Y driver 25 processes the Y driving control signal S _Y among the driving control signals S _A , S _Y , and S _X from the logic controller 22 and applies the Y driving control signal S _Y to the Y electrode lines.

3 is a timing diagram illustrating a driving method of driving a unit frame composed of a plurality of sub-fields in the method of driving a plasma display panel according to the present invention.

Referring to the drawing, the unit frame FR is divided into eight subfields SF1 to SF8 to realize time division gray scale display. Each subfield SF1 to SF8 is divided into reset periods R1 to R8, address periods A1 to A8, and sustain discharge periods S1 to S8.

The luminance of the plasma display panel is proportional to the length of the sustain discharge periods S1 to S8 occupied in the unit frame. The length of the sustain discharge cycles S1 to S8 occupied in the unit frame is 255T (T is the unit time). At this time, a time corresponding to 2 ⁿ is set in the sustain discharge period Sn of the nth subfield SFn. Accordingly, if the subfield to be displayed among the eight subfields is appropriately selected, 256 gray levels may be displayed including all zero (zero) grays not displayed in any of the subfields.

4 is a timing diagram illustrating an embodiment of driving signals applied to electrode lines of the plasma display panel in successive sub-fields according to the present invention.

In FIG. 4, reference numeral S _{AR1 ..ABm} denotes a driving signal applied to each address electrode line (A _R1 to A _Bm of FIG. 1), and S _{X1 ..Xn} denotes X electrode lines (X ₁ to X of FIG. 1). _n ), and S _Y1 to S _Yn indicate a drive signal applied to each Y electrode line (Y ₁ to Y _{n in} FIG. 1).

Referring to the drawings, in the reset period PR of the unit sub-field SF, first, the voltage applied to the X electrode lines X ₁ to X _n is converted from the ground voltage V _G to the second voltage V _S. For example, it continuously increases to 155 volts (V). Here, the ground voltage V _G is applied to the Y electrode lines Y ₁ to Y _n and the address electrode lines A _R1 to A _Bm . Accordingly, between the X electrode lines X ₁ to X _n and the Y electrode lines Y ₁ to Y _n , and the X electrode lines X ₁ to X _n and the address electrode lines A ₁ to A _A weak discharge occurs between _m ) and negative wall charges are formed around the X electrode lines X ₁ to X _n .

The Next, Y electrode lines (Y ₁ ~ Y _n) voltage to the second voltage applied to the (V _S), for example, the third voltage (V _SET than the second voltage (V _S) from 155 volt (V) The maximum voltage (V _SET + V _S ), which is as high as), continues to rise to, for example, 355 volts (V). Here, the ground voltage V _G is applied to the X electrode lines X ₁ to X _n and the address electrode lines A _R1 to A _Bm . Accordingly, a weak discharge occurs between the Y electrode lines Y ₁ to Y _n and the X electrode lines X ₁ to X _n , while the Y electrode lines Y ₁ to Y _n and the address electrode lines are formed. Weak discharge occurs between (A _R1 and A _Bm ).

Next, while the voltage applied to the X electrode lines X ₁ to X _n is maintained at the second voltage V _S , the voltage applied to the Y electrode lines Y ₁ to Y _n is second. It continues to fall from voltage V _S to ground voltage V _G. Here, the ground voltage V _G is applied to the address electrode lines A _R1 to A _Bm .

Leads in the address period (PA), the address is applied to a display data signal of the address pulse to the electrode line, the second voltage (V _S) lower fourth voltage (V _SCAN) to bias the Y-electrode line than the (Y ₁ As the scan signals of the scan pulses of the ground voltage V _G are sequentially applied to ˜Y _n ), smooth addressing may be performed.

At this time, the display data signal applied to each of the address electrode lines A _R1 to A _{Bm is} supplied with the positive address voltage V _A when the discharge cell is selected and the ground voltage V _G when the discharge cell is not selected. Accordingly, when the display data signal of the positive address voltage V _A is applied while the scan pulse of the ground voltage V _G is applied, wall charges are formed by the address discharge in the corresponding discharge cell. Wall charges do not form. In addition, the second voltage V _S is applied to the X electrode lines X ₁ to X _{n for} more accurate and efficient address discharge.

In this case, it is preferable that the scan pulse and the address pulse have the same pulse width, and the scan pulse and the address pulse are synchronized so that a sufficient amount of positive wall charges can be accumulated on the Y electrode after the address discharge so that subsequent sustain discharge is stabilized. It is desirable to be able to.

In this way, after the wall charge state suitable for the address discharge is formed for all the discharge cells in the reset period PR, in the direction from one end of the panel to the other end, that is, the Y electrode at the other end from one end of the Y electrode Y ₁ . (Y _n ), the scan pulses are sequentially applied in the order of Y ₁ , Y ₂ ,..., Y _n , and to the Y electrodes Y ₁ ,..., Y _{n to} which respective scan pulses are applied. for the address electrodes that form discharge cells to be displayed it is applied to the data pulse through the _{(a 1, ..., a m} ).

Therefore, in the discharge cells corresponding to the Y ₁ electrode, address discharge may occur while the wall charge state formed in the reset period PR is maintained as it is. However, as time passes after the reset discharge, the wall charge state due to the reset discharge may be disturbed. Therefore, the wall charge state due to the reset discharge may be disturbed in the address discharge in the second half of the address period, so that the problem of low discharge may occur in the second half of the address period.

Therefore, in the present invention, before the scan pulse for address discharge is applied, the prescan pulses V _pre1 , V _pre2 ,..., And V _pre3 that cause discharge between the address electrodes are applied to the sustain electrode. The level of the prescan pulse is sequentially increased according to the order of the sustain electrodes to which the scan pulse is applied.

That is, the level of the prescan pulse applied to the Y ₁ electrode is set to V _pre1 , the level of the prescan pulse applied to the Y ₂ electrode is set to V _pre2 , and the level of the prescan pulse applied to the Y _n electrode is set to V _pren. You can do At this time, it is preferable that V _pre1 <V _pre2 <... <V _pren so that the level of the prescan pulse becomes higher toward the second half of the address period PA.

Accordingly, as the latter half of the address period in which the wall charge effect due to the reset discharge may be disturbed, the precharge of the wall charge which may be disturbed over time by the larger pre-address discharge is compensated in advance. Therefore, the wall charge state necessary for the address discharge is formed more strongly in the discharge cells which cause the address discharge later, so that the address discharge can be stably generated even if the wall charge state is disturbed according to the time delay. Discharge can be prevented and discharge unevenness can be prevented thereby.

In addition, since the address discharge can be stabilized and the address pulse width can be reduced, a high speed address can be realized.

In the sustain discharge period PS, the display sustain pulse of the second voltage V _S is alternately applied to all the Y electrode lines Y ₁ to Y _n and the X electrode lines X ₁ to X _n . In the corresponding address period PA, a discharge for maintaining the display occurs in discharge cells in which wall charges are formed.

According to the driving method of the display panel according to the present invention, the pre-scan pulse in the discharge cell which causes the pre-address discharge by the pre-scan pulse in all the discharge cells before the address discharge and causes the address discharge later from the discharge cell which causes the first address discharge. By gradually increasing the level of, the low discharge due to the time delay of the address discharge in each discharge cell in the panel can be prevented, and the discharge uniformity can be improved.

Although the present invention has been described with reference to one embodiment shown in the accompanying drawings, it is merely an example, and those skilled in the art may realize various modifications and equivalent other embodiments therefrom. I can understand. Accordingly, the true scope of protection of the invention should be defined only by the appended claims.

Claims (5)

For the display panel in which discharge cells are formed by the sustain electrode and the address electrode, there are a plurality of sub-fields according to respective gray weights for time-division gray scale display for each frame as a display period, and reset for each sub-field. In the driving method of a display panel in which a period, an address period, and a sustain discharge period are present and driven, In the address period, scan pulses are sequentially applied to the sustain electrodes from one end of the panel to the other end, and data pulses are applied to the address electrodes of the discharge cells to be displayed among the discharge cells. Select the discharge cell to Before the scan pulse is applied, a pre-scan pulse causing a discharge between the sustain electrode and the address electrode is applied, And the level of the pre-scan pulse is sequentially increased according to the order of the sustain electrodes to which the scan pulse is applied. The method of claim 1, Discharge cells are formed in an area where the address electrode lines intersect with respect to the sustain electrode pairs in which the X and Y electrodes are alternately arranged side by side in the display panel, In the address period, the X electrode is biased to a first level, And a scan pulse of a third level is sequentially applied while the Y electrode is biased to the second level. The method of claim 2, And the pre-scan pulse is applied to the Y electrode. The method of claim 2, And the level of the prescan pulse is higher than the second level. The method of claim 2, The address electrode is maintained at the fourth level while the pre-scan pulse is applied, and the X electrode is maintained at the second level.

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