KR20060087108A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

The present invention is to provide a semiconductor device and a method of manufacturing the same that can prevent the current reverse phenomenon and the threshold voltage to increase significantly in the high-voltage BiMOS transistor having a long channel, in the present invention is formed on a substrate A semiconductor device comprising a gate electrode, a junction region formed on the substrate exposed to both sides of the gate electrode, and a first drift region formed by implanting impurity ions of a type opposite to the junction region below the gate electrode; It provides a manufacturing method.

BiMOS, High Voltage Transistor, Cross, Drift Region, Long Channel, Short Channel

Description

Semiconductor device and its manufacturing method {SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME}             

1 is a plan view showing a semiconductor device according to a preferred embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along the line 'A-A' shown in FIG. 1; FIG.

3 to 6 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a preferred embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

10: Well

11: N ^- drift

12a, 12b: P ^- drift

13: field oxide film

14: gate insulating film

15: polysilicon film

16: gate electrode                 

17: N ⁺ junction area

18: P ⁺ junction area

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly, to a bipolar transistor having a directional structure having a breakdown voltage (BV) of 40V or more, and a method of manufacturing the same.

In general, in order to have a breakdown voltage of 40 V or more in the 0.18 μm class, the high voltage BiMOS transistor has a long channel of 2 μm or more. However, in such a high voltage BiMOS transistor, when the threshold voltage is set high and the channel length becomes longer than a certain length based on the effective channel length, the drain region and the source are increased. A current reverse phenomenon occurs in which the amount of current flowing through the region is smaller than that of a short channel. As a result, designers cannot accurately identify and set the spice and electrical parameters when designing a circuit.

Accordingly, the present invention has been proposed to solve the above-mentioned problems of the prior art, and the semiconductor device and its fabrication which can prevent a large increase in the current reverse phenomenon and the threshold voltage occurring in a high voltage BiMOS transistor having a long channel. The purpose is to provide a method.

Another object of the present invention is to provide a semiconductor device and a method of manufacturing the same, which can improve current performance per unit area by selectively adjusting the amount of current flowing through the channel region.

According to an aspect of the present invention, there is provided a semiconductor device including a gate electrode formed crosswise on a substrate, and a junction region formed on each of the substrates exposed to each corner of the gate electrode. do.

According to another aspect of the present invention, there is provided a gate electrode formed on a substrate, a junction region formed on the substrate exposed to both sides of the gate electrode, and a junction region below the gate electrode. Provided is a semiconductor device including a first drift region formed by implanting impurity ions of a type opposite to the above.

In addition, the present invention according to another aspect for achieving the above object, forming a well in a substrate, forming a first drift region in a predetermined region in the well, and between the first drift region Implanting impurity ions of a type opposite to the first drift region to form a second drift region, forming a gate electrode on the substrate to cover the second drift region, and in the first drift region It provides a method for manufacturing a semiconductor device comprising forming a junction region.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.

Example

1 is a plan view of a high voltage BiMOS transistor shown in order to explain a semiconductor device according to an exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along the line 'A-A' of FIG. 1. Here, an NMOS transistor is shown as an example for convenience of description.

1 and 2, a semiconductor device according to a preferred embodiment of the present invention includes a gate electrode 16 formed on a semiconductor substrate (not shown) to have a cross (+), and a lower portion of the gate electrode 16. A plurality of P ⁻ drift regions 12b spaced apart from each other in a direction parallel to each other along the shape of the gate electrode 16 in the substrate and one at each of upper and lower left and right corners of the gate electrode 16 are formed. N ⁺ junction region 17.

The P ⁻ drift region 12b (hereinafter, referred to as a first drift region) is formed to be spaced apart from the N ⁻ drift region 11 (hereinafter, referred to as a second drift region) formed at a predetermined interval L from each other. do. Second drift region 11 by spreading the electric field applied to the N ⁺ junction region 17 to deepen the depth of the bonding zone N ⁺ junction region 17 to increase the junction breakdown voltage (breakdown voltage) due to electric field concentration It is formed to surround.

A first drift region (12b) is N ⁺ junction region (17) bias (bias), if applied to N ⁺ junction region of the ion, for example a (Phosphorus doped in the 17 and the second drift region (11), P in ), Arsenic (As) ions diffuse into the channel region to prevent the channel length from decreasing below the effective channel length. That is, the channel length is fixed so that the effective channel length is maintained. As a result, the current reverse phenomenon occurring in the long channel can be prevented.

In addition, by preventing diffusion of the N ⁺ junction region 17 and the second drift region 11 through the first drift region 12b into the channel region, the channel length is reduced in consideration of the case where the channel length is reduced by diffusion. In order to increase the threshold voltage decreased by the decrease, it is possible to prevent the well 10 concentration from being increased during the ion implantation process for adjusting the threshold voltage. As a result, the threshold voltage may be prevented from increasing by maintaining a constant concentration of the well 10 in the center portion of the channel region located between the first drift regions 12b.

On the other hand, the gate electrode 16 is cross-shaped as described above, a total of four N ⁺ junction region 17 is formed on each of the upper left and right sides. Then, a metal wiring process is selectively performed to appropriately select a junction region to be used as a source region or a drain region among the N ⁺ junction regions 17. Thus, the amount of current flowing from the drain region to the source region can be selectively controlled. For example, in order to reduce the amount of current flowing from the drain region to the source region, the N ⁺ junction region formed on the left side of the upper portion through the metal wiring process may be used as the source region, and the remaining N ⁺ junction region may be used as the drain region. .

In addition, in the case of using the preferred embodiment of the present invention as a directional BiMOS transistor, a metal wiring process is performed to use any two N ⁺ junction regions of four N ⁺ junction regions as a source region, and any two The N ⁺ junction region of may be used as the drain region.

Hereinafter, a method of manufacturing a semiconductor device according to an exemplary embodiment of the present invention illustrated in FIG. 2 will be described with reference to FIGS. 3 to 6. Although only NMOS transistors are shown in FIGS. 3 to 6, the following description will be made as a method of manufacturing a CMOS transistor for better understanding.

First, as shown in FIG. 3, a high voltage N-well (HNWELL, not shown) is formed in an NMOS region by performing a diffusion process or an ion implantation process in a substrate (not shown). A high voltage P-well (HPWELL) 10 is formed in the PMOS region. In this case, the diffusion process is composed of a pre-deposition step and a drive-in step, and the pre-deposition is a step of injecting a predetermined amount of N-type or P-type impurities into the surface of the substrate. The amount of impurities pre-deposited on the surface of the substrate is controlled to obtain a final junction depth and concentration distribution by controlling the temperature and the processing time. On the other hand, the ion implantation process is a method in which the impurity atoms are accelerated to the ion state and injected directly to the substrate. Of course, in the ion implantation process, the drive-in step using the heat treatment process may be performed as in the diffusion process.

Subsequently, a diffusion process or an ion implantation process using N-type or P-type impurity ions is performed, and the N ^- drift region 11 and the P-drift region 12a, respectively, in predetermined regions in the N-well and P-well 10, respectively. 12b). At this time, the P ⁻ drift region 12b formed in the P-well is formed in the channel region so as to cross the N ⁻ drift region 11 at a predetermined interval L in a cross shape. In addition, the N ⁻ drift region formed in the N ^- well is formed in the same shape as the P ⁻ drift region 12b formed crosswise under the gate electrode 16 in the NMOS region.

On the other hand, the P ⁻ drift region 12a also functions for device isolation for electrically separating the PMOS region and the NMOS region.

Next, as shown in FIG. 4, a LOCOS (LOCal Oxidation of Silicon) process is performed to form a field oxide layer 13 defining an active region and a field region in a predetermined region of the substrate. do. Alternatively, a device isolation layer defining an active region and a field region may be formed by performing a shallow trench isolation (STI) process or a deep trench isolation (DTI) process instead of the LOCOS process. In this case, the P- drift region 12a which functions for element isolation may not be formed.

Subsequently, as shown in FIG. 5, the ion implantation process for adjusting the threshold voltage is performed in the channel region of the PMOS region and the NMOS region, respectively.

Subsequently, an oxidation process is performed to form the gate insulating film 14 in the PMOS region and the NMOS region. At this time, the oxidation process is performed by a wet oxidation method in which the silicon substrate is heated at a temperature of approximately 900 to 1000 ° C. in an oxidizing gas such as water vapor, or dry oxidation which is heated at a temperature of about 1200 ° C. using pure oxygen as the oxidizing gas. Do it in a way.

Next, a polysilicon film 15 is deposited on the gate insulating film 14 as a conductive film. At this time, the polysilicon film 15 is formed of a doped or undoped silicon film. For example, in the case of an undoped silicon film, it is deposited by a low pressure chemical vapor deposition (LPCVD) method using SiH ₄ . On the other hand, in the case of the doped silicon film is deposited by LPCVD method using a gas mixed with PH ₃ , PCl ₅ , BCl ₃ or B ₂ H ₆ in SiH ₄ .

Meanwhile, a tungsten layer (or a tungsten silicide layer) (not shown) may be further formed on the polysilicon film 15.

Subsequently, a photolithography process is performed to etch the polysilicon film 15 and the gate insulating film 14 to form the gate electrode 16 in the PMOS region and the NMOS region, respectively.

Next, as shown in FIG. 6, a source / drain ion implantation process is performed to form a junction region 17 in the drift region 11 exposed to each gate electrode 16 in the PMOS region and the NMOS region. As a result, a P ⁺ junction region (not shown) is formed in the P ⁻ drift region (not shown) of the PMOS region, and an N + junction region 17 is formed in the N ⁻ drift region 11 of the NMOS region. The P ⁺ or N ⁺ junction region 17 functions as a source region or a drain region, respectively.

Meanwhile, the non-described reference numeral '18' is a junction region formed at the same time as the P ⁺ junction region formed in the NMOS region, and performs a device isolation function.

Although the technical spirit of the present invention has been described in detail in the preferred embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. In addition, it will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, the following effects can be obtained.

First, in the present invention, a drift region is formed in a direction parallel to the gate electrode by implanting impurity ions of a different type from the junction region, respectively, on both sides of the lower portion of the gate electrode, so that a bias is applied to the junction region. Doped ions diffuse into the channel region to prevent the channel length from decreasing below the effective channel length. This can prevent current reverse from occurring in the long channel transistor. In addition, it is possible to keep the substrate, that is, the well concentration in the center portion of the channel region located between the drift regions, to prevent the threshold voltage from increasing in this region.

Second, in the present invention, a gate electrode formed on the substrate to have a cross (+) is formed, and a total of four junction regions are formed on the top, bottom, left, and right sides of the gate electrode, respectively, and a source region or one of the junction regions is formed through a metal wiring process. By appropriately selecting the junction region to be used as the drain region, the amount of current flowing from the drain region to the source region can be selectively controlled.

Claims (20)

A gate electrode formed crosswise on the substrate; And A junction region formed on each of the substrates exposed to each corner of the gate electrode; A semiconductor device comprising a; The method of claim 1, And a first drift region formed to surround each of the junction regions. The method of claim 2, And a second drift region formed by implanting impurity ions opposite to the first drift region in a direction parallel to each other under the gate electrode so as to be spaced apart from the first drift region at regular intervals. The method of claim 1, And a second drift region formed by implanting impurity ions opposite to the junction region in a direction parallel to each other under the gate electrode so as to be spaced apart from the junction region at a predetermined interval. The method according to claim 3 or 4, The second drift region is formed in a direction parallel to the gate electrode. The method according to claim 3 or 4, The second drift region has a cross shape. A gate electrode formed on the substrate; A junction region formed in the substrate exposed to both sides of the gate electrode; And A first drift region formed by implanting impurity ions opposite to the junction region under the gate electrode; Semiconductor device comprising a. The method of claim 7, wherein The first drift region is formed in a direction parallel to the gate electrode. The method according to claim 7 or 8, The first drift region is formed to be spaced apart from the junction region at regular intervals. The method of claim 7, wherein And a second drift region formed to surround the junction region. The method of claim 10, The second drift region is formed by implanting impurity ions of a type opposite to the first drift region. The method according to claim 10 or 11, wherein The second drift region is formed to be spaced apart from the first drift region at a predetermined interval. The method of claim 7, wherein The gate electrode is cross-shaped semiconductor device. The method of claim 13, The first drift region has a cross shape and is formed in a direction parallel to the gate electrode. The method according to claim 13 or 14, And one junction region formed at each corner of the cross-shaped gate electrode. Forming a well in the substrate; Forming a first drift region in a predetermined region in the well; Implanting impurity ions of a type opposite to the first drift region between the first drift region to form a second drift region; Forming a gate electrode on the substrate to cover the second drift region; And Forming a junction region in the first drift region; Method of manufacturing a semiconductor device comprising a. The method of claim 16, The gate electrode is formed in a cross shape manufacturing method of a semiconductor device. The method of claim 17, And forming one junction region at each corner of the cross-shaped gate electrode. The method of claim 16, The second drift region is formed to be spaced apart from the first drift region at a predetermined interval. The method of claim 16 or 19, The second drift region is formed to be spaced apart from each other at a predetermined interval.

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