KR20060086623A - Thin film transistor substrate and liquid crystal display panel comprising the same - Google Patents

Abstract

The present invention relates to a thin film transistor substrate and a liquid crystal display panel including the same, comprising: a pair of gate lines arranged in parallel with each other and adjacent to each other; A data line insulated from the pair of gate lines; A thin film transistor formed at an intersection region of a pair of gate lines and data lines; And a pair of pixel electrodes positioned between the pair of gate lines and attached to each gate line to face each other. Accordingly, a thin film transistor substrate capable of preventing variations in parasitic capacitance and a liquid crystal display panel including the same are provided.

Description

Thin film transistor substrate and liquid crystal display panel including same {THIN FILM TRANSISTOR SUBSTRATE AND LIQUID CRYSTAL DISPLAY PANEL COMPRISING THE SAME}

1 is a layout view of a thin film transistor substrate according to a first embodiment of the present invention;

2 is a cross-sectional view of the liquid crystal display panel of the present invention taken along the line II-II of FIG.

3 is an enlarged view of a thin film transistor adjacent to each other according to a first embodiment of the present invention;

4 is a view showing an embodiment in which an incision pattern is formed in a pixel electrode of a first embodiment of the present invention;

5 is a layout view of a thin film transistor substrate according to a second exemplary embodiment of the present invention.

Explanation of Signs of Major Parts of Drawings

100: thin film transistor substrate 120: gate electrode

122: gate line 123: gate pad

161: drain electrode 162: source electrode

163: data line 164: data pad

180 pixel electrode 181 contact hole

The present invention relates to a thin film transistor substrate and a liquid crystal display panel including the same, and to a thin film transistor substrate and a liquid crystal display panel including the same, which can prevent variations in parasitic capacitance.

The liquid crystal display panel displays a desired image by adjusting the light transmittance of liquid crystal cells arranged in a matrix form according to image signal information. The liquid crystal display panel includes a thin film transistor substrate, a color filter substrate attached to each other so as to face the thin film transistor substrate, and including a color filter, a black matrix, and a common electrode, and a liquid crystal injected between the thin film transistor substrate and the color filter substrate. do.

In general, a thin film transistor (TFT) is a circuit board for driving each pixel independently in a liquid crystal display (LCD) or an organic luminescence (EL) display, and is formed in a predetermined pattern. Wiring and data wiring.

Here, a method of forming a pattern includes a method of exposing the entire area using one mask or by dividing the entire area into two or more exposure areas Shot.

However, as the substrate becomes larger, it is difficult to form a precise pattern in the former case, and in the latter case, a problem of misalignment occurs due to a difference in mechanical precision of the equipment between the exposure areas. That is, distortions such as shift, rotation, and distortion of the pattern are generated, resulting in portions having different electrical characteristics in the display area.

In particular, the overlapping area of the source electrode and the gate electrode of the thin film transistor is changed, so that the parasitic capacitance is changed between the gate electrode and the source electrode, so that the electrical response characteristics of the liquid crystal display are not good. .

Accordingly, an object of the present invention is to provide a thin film transistor substrate capable of preventing variations in parasitic capacitance and a liquid crystal display panel including the same.

The object is, according to the present invention, a pair of gate lines arranged in parallel with each other and adjacent to each other; A data line insulated from the pair of gate lines; A pair of thin film transistors formed at the intersections of the pair of gate lines and data lines; And a pair of pixel electrodes positioned between the pair of gate lines and attached to each gate line so as to face each other.

Here, it is preferable for the pair of thin film transistors to have a U-shaped channel portion to prevent variation of parasitic capacitance.

In addition, it is preferable that a pixel electrode cutout pattern having a predetermined pattern is formed on the pixel electrode to improve the viewing angle.

SUMMARY OF THE INVENTION An object of the present invention includes a thin film transistor in which a pair of gate lines and a pair of pixel electrodes are alternately arranged, connected to the pixel electrodes, and attached to the pair of gate lines and disposed adjacent to each other. A thin film transistor substrate is used.

Another object of the present invention, the gate line; A pair of data lines insulated from and intersecting the gate lines; A pair of thin film transistors formed in an intersection region of the gate line and the data line and having a c-shaped channel portion; And a pair of pixel electrodes positioned between the pair of data lines and attached to each data line so as to face each other.

It is another object of the present invention to include a thin film transistor in which a pair of data lines and a pair of pixel electrodes are alternately arranged, connected to the pixel electrodes, and attached to the pair of data lines and disposed adjacent to each other. It is achieved by a thin film transistor substrate characterized in that.

Another object of the present invention, the second substrate; A pair of gate lines arranged in parallel with each other, a data line insulated from the pair of gate lines, a pair of pixel electrodes positioned between the pair of gate lines and attached to each gate line to be adjacent to each other, and A first substrate connected to the pixel electrode and having a thin film transistor formed at an intersection of a pair of gate lines and a data line; And a liquid crystal layer positioned between the first substrate and the second substrate.

Here, the thin film transistor preferably has a U-shaped channel portion.                     

Another object of the invention is a plurality of pixel electrodes arranged in a matrix form; A plurality of gate lines transferring a gate signal to a row direction pixel electrode among the plurality of pixel electrodes; A plurality of data lines transferring a data signal to column pixel electrodes of the plurality of pixel electrodes; And a plurality of thin film transistors formed near intersections of the gate lines and the data lines, and connected to the gate lines, the data lines, and the pixel electrodes, respectively, wherein at least one thin film transistor among the plurality of thin film transistors is adjacent to the first thin film. It has a shape substantially symmetrical with the first thin film transistor around the transistor and the vertical bisector, and has a shape substantially symmetrical with the second thin film transistor around the vertical bisector with the second thin film transistor adjacent in the column direction. Is achieved by a liquid crystal display panel.

Here, it is preferable that at least one thin film transistor has a horseshoe-shaped channel portion in order to prevent variation of parasitic capacitance.

In addition, it is preferable that the horseshoe-shaped channel portion be substantially symmetrical about a imaginary line passing in a predetermined column direction or row direction to minimize variation in parasitic capacitance.

Hereinafter, a thin film transistor substrate and a liquid crystal display panel including the same according to the present invention will be described in detail with reference to the accompanying drawings.

1 is a layout view of a thin film transistor substrate according to an exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view of a liquid crystal display panel manufactured according to the present invention.

The liquid crystal display panel 1 includes a thin film transistor substrate 100 (hereinafter, referred to as a “first substrate”) including a pixel electrode 180 and a common electrode 250, and is disposed on the first substrate 100. A color filter substrate 200 (hereinafter referred to as "second substrate") coupled to each other and a liquid crystal layer 300 positioned between the first substrate 100 and the second substrate 200.

The filled liquid crystal has optical anisotropy and polarization, and is driven by a change in electric field generated when a voltage is applied to two electrodes facing each other. That is, an artificial electric field is applied to the liquid crystal to control the direction of molecular arrangement of the liquid crystal, thereby forming an image through the light transmittance which varies.

First, the first substrate 100 will be described. The first substrate 100 includes a plurality of gate wires 125 and a plurality of data wires 160 and a gate wire on a first substrate material 110 made of an insulating material such as glass, quartz, ceramic, or plastic. A thin film transistor (TFT) T, which is a switching element formed at the intersection of the 125 and the data line 160, and a pixel electrode 180 connected to the thin film transistor T are included.

A signal voltage is applied to the liquid crystal layer 300 between the pixel electrode 180 and the common electrode 250 of the second substrate 200 to be described later through the thin film transistor T, and the liquid crystal layer 300 receives this signal. It is aligned with the voltage to determine the light transmittance.

The gate line 125 is connected to a plurality of gate lines 122 and gate lines 122 extending in the horizontal direction, and receives a gate signal from the outside and transmits the gate signal 123 to the gate line 122. And a gate electrode 120 that is part of the gate line 122 and is part of the thin film transistor. The gate electrode 120 is formed to branch from the gate line 122 in an increased width.                     

The gate lines 122 are formed in pairs and arranged in parallel to each other, and pixel electrodes 180 to be described later are attached to each gate line 122 in the region between the gate lines 122 and are disposed adjacent to each other. . One of the pair of gate lines 122 is arranged in parallel and adjacent to any one of the other pair of gate lines 122. The pixel electrode 180 is not formed in an area between any one of the pair of gate lines 122 and the other pair of gate lines 122. That is, the pair of pixel electrodes 180 positioned between the pair of gate lines 122 and the pair of gate lines 122 are repeatedly arranged.

The data line 160 is connected to one end of the data line 163 and the data line 163 extending in the vertical direction, and the drain is branched from the data pad 164 and the data line 163 to receive an image signal from the outside. A source electrode 162 is disposed opposite the electrode 161 and the drain electrode 161.

Here, the drain electrode 161 is branched from the data line 163 in a U shape, and the source electrode 162 is positioned inside the drain electrode 161. The drain electrode 161 and the source electrode 162 are formed on the above-described gate electrode 120 to form a thin film transistor T to be described later.

The data line 160 is insulated from and intersected with the gate line 125 described above to define the pixel area. In the pixel region, a pair of pixel electrodes are disposed to face each other. That is, a pixel region is defined by a pair of gate lines 122 arranged in parallel and two adjacent data lines 163 insulated from and intersected with the pair of gate lines 122, and a pair of pixels in the pixel region. The electrode 180 is located. The pixel electrode 180 is attached to each gate line 122 and disposed to face each other adjacently.

The thin film transistor T includes a gate electrode 120, a gate insulating layer 130, a semiconductor layer 140, ohmic contact layers 151 and 152, a source electrode 162, and a drain electrode 161.

The gate insulating layer 130 is made of an insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx), and is stacked on the entire surface of the first substrate 100 on which the gate line 122 and the gate electrode 120 are formed. On the gate insulating layer 130 where the gate electrode 120 is located, the semiconductor layer 140 made of amorphous silicon and the ohmic contact layers 151 and 152 made of n + hydrogenated amorphous silicon heavily doped with n-type impurities are sequentially formed. It is. Here, the ohmic contact layers 151 and 152 are separated on both sides of the gate electrode 120. In addition, unlike the above-described embodiment, the semiconductor layer 140 may be formed of polysilicon.

The drain electrode 161 and the source electrode 162 branched from the data line 163 and the data line 163 are formed on the ohmic contacts 151 and 152. The drain electrode 161 is branched in a U-shape from the data line 163, and a source electrode 162 is positioned inside the drain electrode 161 to form a U-shaped channel portion.

Here, each wiring including the gate line 122, the gate electrode 120, the data line 163, the source electrode 162, the drain electrode 161, and the like is formed of a single layer of a metal or an alloy. However, in order to compensate for the shortcomings of each metal or alloy and to obtain desired physical properties, they are often formed in multiple layers. For example, aluminum or an aluminum alloy is used as the lower layer, and chromium or molybdenum is used as the upper layer. The lower layer uses aluminum or aluminum alloy with low specific resistance to prevent signal resistance due to wiring resistance, and the upper layer uses chemicals to compensate for the shortcomings of aluminum or aluminum alloy where corrosion resistance by chemicals is weak and easily oxidized to cause disconnection. The upper layer is formed of chromium or molybdenum, which is highly resistant to chemicals. In recent years, molybdenum, aluminum, titanium, tungsten, and the like are spotlighted as wiring materials, and most of them are used in multiple layers.

The protective film 170 is formed of silicon nitride (SiNx), a-Si: C: O film or a-Si: C: F film (low dielectric constant CVD film) and acrylic organic film deposited by PECVD (Plasma Enhanced Chemical Vapor Deposition) method. And so on. A contact hole 181 for exposing the source electrode 162 of the thin film transistor T is formed in the passivation layer 170.

The pixel electrode 180 is formed on the passivation layer 170 and the contact hole 181. The pixel electrode 180 contacts the source electrode 162 through the contact hole 181, whereby the thin film transistor T and the pixel electrode 180 are electrically connected to each other. The pixel electrode 180 is formed of a reflective conductive film having a high reflectivity such as aluminum (Al) or silver (Ag) in the case of a reflective liquid crystal display panel, and is formed of indium tin oxide (ITO) or in the case of a transmissive liquid crystal display panel. It is formed of a transparent conductive film such as indium zinc oxide (IZO). In the case of the reflective-transmissive liquid crystal display panel, the pixel electrode 180 has a structure in which the transparent conductive film and the reflective conductive film are stacked.

As shown in FIG. 4, the pixel electrode cutting patterns 185 and 186 having a predetermined shape may be formed in the pixel electrode. The cutting pattern is divided into liquid crystal layers having different orientations, thereby realizing a wide viewing angle. Although not shown, the pixel electrode is divided into a multi-domain consisting of a main pixel region and a subpixel region, and the main pixel region is connected through a drain electrode and a contact hole, and the subpixel region has a protective film therebetween. In order to overlap the drain electrode, a capacitance may be formed in the passivation layer. This improves visibility.

In the second embodiment, as shown in Fig. 5, a pair of data lines and a pair of pixel electrodes are alternately arranged. A thin film transistor is formed to have a c-shaped channel portion at the intersection of the data line and the gate line. The thin film transistors are disposed adjacent to each data line.

That is, it is located between a pair of thin film transistors and a pair of data lines having a c-shaped channel portion formed at an intersection of the gate line, the pair of data lines that are insulated from and intersecting the gate lines, and intersected with each other. A parasitic capacitance can be prevented by fabricating a thin film transistor substrate attached to each data line and including a pair of pixel electrodes disposed to face each other. The principle of preventing the variation of the parasitic capacitance by the second embodiment will be described in detail in the following description of the principle of preventing the parasitic capacitance variation of the first embodiment.

Next, the second substrate 200 will be described. Like the first substrate 100, the second substrate 200 is made of a second substrate material including an insulating material such as glass, quartz, ceramic, or plastic. A black matrix 230 formed in an area between the color filter 220 and the color filter 220 having three primary colors of red, green and blue or cyan, magenta and yellow on the 210, a black matrix 230 and The common electrode 250 is formed on the color filter 220.

In addition, an overcoat layer 240 may be included between the black matrix 230, the color filter 220, and the common electrode 250.

The black matrix 230 distinguishes between the colors of the color filters 220 having three primary colors of red, green, and blue (RGB) or three primary colors of cyan, magenta, and yellow to prevent light leakage between adjacent pixels, and thin film transistors. Light is prevented from entering into (T) to prevent poor image quality. The black matrix 230 may be made of a single or a combination of multiple metal layers such as chromium, chromium oxide, and chromium nitride, or may be made of a photosensitive organic material to which a black pigment is added to block light. Here, carbon black, titanium oxide, or the like may be used as the black pigment.

The color filter 220 is formed by repeating red, green and blue or cyan, magenta and yellow colors with the black matrix 230 as a boundary, and is irradiated from a backlight unit (not shown) and passed through the liquid crystal layer 300. It gives a color to. The color filter 220 may also be made of a photosensitive organic material, such as a black matrix.

The overcoat layer 240 protects the color filter 220, planarizes the second substrate 200, and is mainly made of an acrylic epoxy material.

The common electrode 250 is made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). The common electrode 250 directly applies a signal voltage to the liquid crystal layer 300 together with the pixel electrode 180 of the first substrate 100.

The first substrate 100 and the second substrate 200 provided by the present invention are coupled to each other using a sealant (not shown). The liquid crystal layer 300 may be formed by injecting liquid crystal into the space between the two substrates 100 and 200 by a vacuum injection method, or the liquid crystal layer 300 may be formed through a liquid crystal dropping method.

Here, the response characteristics of the thin film transistor T according to the exemplary embodiment of the present invention will be described with reference to FIGS. 2 and 3. In general, the thin film transistor T may have different operating characteristics depending on the width and length of the U-shaped or horseshoe-shaped channel portion existing between the drain electrode 162 and the source electrode 162. In particular, as shown in FIG. 2, the response characteristics are different due to variations in the parasitic capacitance C _gs generated by the overlapping region between the source electrode 162 and the gate electrode 120. have.

The C _gs value can be calculated by the following equation (1).

C _gs = ε (A _gs / d _gs ) ------ (1)

In this case, A _gs represents an area where the gate electrode 120 and the source electrode 162 overlap, d _gs is a distance between the gate electrode 120 and the source electrode 162, and ε means a gate insulating film dielectric constant. do. Accordingly, it can be seen that the smaller the overlap area between the gate electrode 120 and the source electrode 161 is, the better the configuration.

In addition, the C _gs is related to the offset voltage (ΔV _p ) of the DC component, which is the main cause of deterioration of the liquid crystal and the afterimage, in a substrate driven by alternating current.

Said C _gs is related to (DELTA) V _p can be understood by following formula (2).

ΔV _p = (C _gs / C _LC + C _ST + C _gs ) ΔV _p [ΔV _g = ΔV _GH -ΔV _GL ] ------ (2)

In the above formula, V _GH is the highest value of the signal voltage applied to the gate wiring 125, the voltage V _GL is the lowest value of the voltage applied to the gate wiring 125, the voltage V _g is the voltage applied to the gate electrode 120, and C _LC + C _ST + C _gs can be expressed as C _T as full capacity. In this case, C _gs is a parasitic capacitance between the gate electrode 120 and the source electrode 162, C _ST is a storage capacitor auxiliary capacitance, and C _LC is a liquid crystal capacitance.

It can be seen from Equation (2) that the offset voltage value ΔV _p is proportional to the C _gs value generated between the gate electrode 120 and the source electrode 161. Therefore, the smaller the C _gs value, the more preferable the operation characteristic of the substrate. As shown in FIG. 2, since the C _gs value is always present in the configuration of the thin film transistor T, it is preferable to minimize the C _gs value or not to change it.

However, when the substrate is enlarged, the divided exposure is divided into regions, and when the pattern of the source electrode 162 is formed on the substrate, misalignment such as vertical and horizontal shifts of the pattern is generated for each region. As a result, the C _gs value is different for each region, and as a result, the distribution of the ΔV _p values is also different for each region. Thus, deterioration of image quality such as local flicker is caused. As a result, afterimages or unevenness between pixels occur on the screen.

Therefore, in the present invention, the arrangement of the thin film transistor substrate is improved to maintain the C _gs value constant. In other words, according to the arrangement of the present invention, even when the divided exposure is performed for each region to form a pattern, in the case of a thin film transistor having a U-shaped or horseshoe-shaped channel portion, even if the source electrode 162 fluctuates from side to side, the gate electrode 120 ) And the source electrode 162 overlap with each other. Therefore, it is possible to eliminate the fluctuation of the parasitic capacitance due to the fluctuation of the left and right of the pattern.

When the pattern of the source electrode 162 fluctuates upward, as shown in FIG. 3, the area where the source electrode 162 of one thin film transistor T overlaps with the gate electrode 120 is a1 and overlaps conventionally. As compared with the area, the area of the thin film transistor T and the other thin film transistor T adjacent to each other is a2, which is increased compared to the conventional overlap area, and thus the C _gs value of each pixel region is changed. However, according to the arrangement according to the present invention, the variation amounts of the C _gs values of the two adjacent thin film transistors T are compensated to each other to be zero.

By this principle it is possible to minimize the amount of change in the overall C _gs value of the substrate. In other words, when the large-sized substrate is divided into four regions and exposed, the amount of change in the overall C _gs value in each region becomes zero, and the amount of change in the C _gs value in the entire substrate also becomes zero.

And more specifically, a source electrode 162 is to move to the upper C _gs value of the 'U', but the C _gs value of the thin film transistor (T) the reduction of the shape, '∩' a thin film transistor (T) in the shape of increasing cross- Is complemented. In addition, when the source electrode 162 is moved to the lower side, but increases the C _gs value of the 'U' the thin-film transistor (T) of the contour, C _gs value of '∩' a thin film transistor (T) of a shape is complementary to decrease .

Therefore, as a whole, there is no change in the C _gs value, and the ΔV _p value becomes constant, thereby reducing defects such as afterimages and stains. In addition, the luminance difference of the entire adjacent pixel areas is mutually compensated.

In FIG. 3, when the upper thin film transistor is referred to as a first thin film transistor and the lower thin film transistor is referred to as a second thin film transistor, the second thin film transistor is symmetrical with respect to the first thin film transistor with respect to the vertical bisector. .

According to the second embodiment, in the case of the thin film transistor having a U-shaped or hoof-shaped channel portion shown in FIG. 5, the gate electrode 120 and the source electrode 162 overlap with each other even if the source electrode 162 fluctuates up and down. There is no difference in area. Therefore, it is possible to eliminate the fluctuation of the parasitic capacitance due to the fluctuation of the pattern.

Even if the pattern of the source electrode 162 fluctuates to either of the left and right sides, the variation of the overlapping area between the adjacent thin film transistors does not occur as a whole as in the above-described principle, so that the variation of the C _gs value becomes zero.

And more specifically, a source electrode 162, a Moving to the left C _gs value of "(" shape of a thin film transistor (T) thin film transistor (T) the image of the C _gs value, but reduced, "c" is increased cross- are complementary. in addition, the source electrode 162 to move to the right c _gs value of "(" shape of a thin film transistor (T) thin film transistor (T) the image of the c _gs, but the value is increased, "c" is decreased Complement each other.

In Fig. 5, the thin film transistors adjacent to each other in the column direction are symmetrical with respect to the vertical bisector.

Therefore, similarly to the first embodiment, there is no change in the C _gs value as a whole, and the ΔV _p value becomes constant, thereby reducing defects such as afterimages and stains. In addition, the luminance difference of the entire adjacent pixel areas is mutually compensated.

As described above, according to the present invention, a thin film transistor substrate and a liquid crystal display panel capable of preventing variations in parasitic capacitance can be provided.

Claims (11)

A pair of gate lines arranged parallel to each other and adjacent to each other; A data line insulated from the pair of gate lines; A pair of thin film transistors formed at the intersections of the pair of gate lines and the data lines; And And a pair of pixel electrodes positioned between the pair of gate lines and attached to each gate line to face each other. The method of claim 1, And the pair of thin film transistors have a U-shaped channel portion. The method of claim 1, The thin film transistor substrate according to claim 1, wherein a pixel electrode cutout pattern having a predetermined pattern is formed on the pixel electrode. A thin film transistor comprising a pair of gate lines and a pair of pixel electrodes disposed alternately with each other, the thin film transistors connected to the pixel electrodes and attached to the pair of gate lines, and disposed adjacent to each other; Board. A gate line; A pair of data lines insulated from and intersecting the gate lines; A pair of thin film transistors formed in an intersection region of the gate line and the data line and having a c-shaped channel portion; And And a pair of pixel electrodes positioned between the pair of data lines and attached to each data line to face each other. A thin film transistor comprising a pair of data lines and a pair of pixel electrodes disposed alternately with each other, the thin film transistors connected to the pixel electrodes and attached to the pair of data lines and adjacent to each other; Board. A second substrate; A pair of gate lines arranged in parallel to each other and adjacent to each other, a data line insulated from the pair of gate lines, and a pair located between the pair of gate lines and attached to each gate line to face each other A first substrate connected to the pixel electrode and the pixel electrode, the first substrate having a pair of thin film transistors formed in an intersection region of the pair of gate lines and the data lines; And And a liquid crystal layer disposed between the first substrate and the second substrate. The method of claim 7, wherein And the thin film transistor has a U-shaped channel portion. A plurality of pixel electrodes arranged in a matrix form; A plurality of gate lines transferring a gate signal to a row direction pixel electrode among the plurality of pixel electrodes; A plurality of data lines transferring a data signal to column pixel electrodes of the plurality of pixel electrodes; And And a plurality of thin film transistors formed near an intersection of the gate line and the data line, and connected to the gate line, the data line, and the pixel electrode, respectively, wherein at least one thin film transistor among the plurality of thin film transistors is adjacent in a row direction. The first thin film transistor is substantially symmetrical with the first thin film transistor centered on the vertical bisector, and the second thin film transistor is substantially symmetrical with respect to the vertical bisector with the second thin film transistor adjacent in the column direction. Liquid crystal display panel comprising a. The method of claim 9, And the at least one thin film transistor has a horseshoe-shaped channel portion. The method of claim 10, And said horseshoe-shaped channel portion is substantially symmetrical about an imaginary line passing in a predetermined column direction or row direction.

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