KR20060083096A - Thin film transistor array panel - Google Patents

Abstract

A thin film transistor array panel according to an exemplary embodiment of the present invention includes a substrate, a gate line formed on the substrate, a data line insulated from and intersecting the gate line, a thin film transistor having a drain electrode, connected to each gate line and the data line, and a drain. A capacitive coupling electrode connected to the electrode, each of which is formed in a pixel surrounded by a gate line and a data line, and is separated from the first pixel electrode and the first pixel electrode connected to the drain electrode, and overlaps the capacitive coupling electrode. And a pixel electrode having a second pixel electrode. In this case, the first pixel electrode and the second pixel electrode of different pixels have a symmetrical structure.

LCD, vertical alignment, coupling electrode, visibility, symmetry

Description

Thin Film Transistor Display Panels {THIN FILM TRANSISTOR ARRAY PANEL}

1 is a layout view illustrating one pixel structure in a thin film transistor array panel for a liquid crystal display according to an exemplary embodiment of the present invention.

2 is a layout view illustrating one pixel structure in a common electrode display panel for a liquid crystal display according to an exemplary embodiment of the present invention.

3 is a layout view illustrating a structure of an A pixel in a liquid crystal display according to an exemplary embodiment including the two display panels of FIGS. 1 and 2.

4 and 5 are cross-sectional views of the liquid crystal display of FIG. 3 taken along lines IV-IV 'and V-V';

FIG. 6 is a layout view illustrating a structure of a B pixel in the liquid crystal display shown in FIGS. 1 to 5.

7 is a circuit diagram of a structure of a pixel in a liquid crystal display according to an exemplary embodiment of the present invention.

8 is a layout view illustrating an arrangement structure of pixels in a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 9 is a layout view illustrating an arrangement structure of pixels in a liquid crystal display according to another exemplary embodiment of the present invention.

10 is a layout view illustrating a structure of a pixel in a liquid crystal display according to another exemplary embodiment of the present invention.

FIG. 11 is a cross-sectional view of the liquid crystal display of FIG. 10 taken along the line XI-XI ′. FIG.

12 is a layout view illustrating a structure of a C pixel in a thin film transistor array panel for a liquid crystal display according to another exemplary embodiment of the present invention.

FIG. 13 is a layout view of a liquid crystal display according to another exemplary embodiment including the two display panels of FIGS. 12 and 2.

14 is a layout view illustrating an arrangement structure of pixels in a liquid crystal display according to another exemplary embodiment of the present invention.

FIG. 15 is a layout view illustrating another arrangement structure of pixels in a liquid crystal display according to another exemplary embodiment of the present invention.

FIG. 16 is a layout view illustrating a structure of a D or E pixel in a thin film transistor array panel for a liquid crystal display according to another exemplary embodiment of the present invention.

17 is a layout view illustrating one pixel structure in a common electrode display panel for a liquid crystal display according to another exemplary embodiment of the present invention.

FIG. 18 is a layout view of a liquid crystal display according to another exemplary embodiment including the two display panels of FIGS. 16 and 17.

19 and 20 are cross-sectional views of the liquid crystal display of FIG. 18 taken along lines XIX-XIX 'and IIX-IIX', respectively;

21 is a layout view illustrating an arrangement structure of pixels in a liquid crystal display according to another exemplary embodiment of the present invention.

FIG. 22 is a layout view illustrating another arrangement structure of pixels in a liquid crystal display according to another exemplary embodiment of the present invention. FIG.

<Description of the symbols for the main parts of the drawings>

11, 21: alignment film 12, 22: polarizing plate

100, 200: display panel 110, 210: insulating substrate

121: gate line 124: gate electrode

131: sustain electrode lines 133a, 133b, 133c, 133d: sustain electrode

140: gate insulating film 151, 154: semiconductor

161, 163, and 165: ohmic contacts 171 and 179: data lines

173: source electrode 175: drain electrode

176: coupling electrode 180: protective film

181, 182, and 185 contact holes 190a and 190b pixel electrodes

81, 82: contact auxiliary member 220: light blocking member

250: overcoat 270: common electrode

91, 92, 93a, 93b, 94a, 94b, 95a, 95b: cutout of the pixel electrode

71, 72, 73a, 73b, 74a, 74b, 75a, 75b: cutout of common electrode

3: liquid crystal layer 310: liquid crystal molecules

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor array panel, and more particularly, to a thin film transistor array panel of a vertical alignment mode liquid crystal display device that divides a pixel into a plurality of domains to obtain a wide viewing angle.

The liquid crystal display is one of the most widely used flat panel display devices. The liquid crystal display includes two display panels on which a field generating electrode is formed and a liquid crystal layer interposed therebetween, and applies a voltage to the field generating electrode. An image is displayed by generating an electric field and determining the alignment of liquid crystal molecules of the liquid crystal layer and controlling the polarization of incident light.

Among them, the vertical alignment mode liquid crystal display in which the long axis of the liquid crystal molecules are arranged perpendicular to the upper and lower display panels without an electric field applied to the display panel is high in contrast ratio and easy to implement a wide viewing angle.

Means for implementing a wide viewing angle in a vertical alignment mode liquid crystal display include a method of forming a cutout in the field generating electrode and a method of forming a protrusion on the field generating electrode. Since the direction in which the liquid crystal molecules are inclined by the cutout and the protrusion can be determined, the wide viewing angle can be secured by dispersing the inclination directions of the liquid crystal molecules in various directions.

However, the liquid crystal display of the vertical alignment type has a problem in that the side visibility is inferior to the front visibility.

An object of the present invention is to provide a thin film transistor array panel having excellent visibility.

In order to solve this problem, the present invention divides a pixel electrode into two or more sub pixel electrodes so that two different voltages are applied to the sub pixel electrode, and each pixel has at least two or more different structures of the sub pixel electrode. Arrange.

A thin film transistor array panel according to an exemplary embodiment of the present invention includes a substrate, a gate line formed on the substrate, a data line insulated from and intersecting the gate line, a thin film transistor having a drain electrode, connected to each gate line and the data line, and a drain. A capacitive coupling electrode connected to the electrode, each of which is formed in a pixel surrounded by a gate line and a data line, and is separated from the first pixel electrode and the first pixel electrode connected to the drain electrode, and overlaps the capacitive coupling electrode. And a pixel electrode having a second pixel electrode. In this case, the first pixel electrode and the second pixel electrode of different pixels have a symmetrical structure.

In this case, the first and second pixel electrodes have the same arrangement structure in the row direction, and the first and second pixel electrodes have the left-right symmetrical structure alternately in the column direction, or the first and second pixels in the column direction. The electrodes may have a left-right symmetrical structure alternately in units of two rows.

The pixels in which the first and second pixel electrodes have a symmetrical structure are preferably arranged in the same area or number.

Preferably, the pixel electrode has a domain dividing means that is an incision, and the incisions are connected to each other to form a gap separating the first pixel electrode and the second pixel electrode, and the gap is 45 ° with respect to the first signal line. Contains wealth.

In addition, the thin film transistor array panel according to the present invention includes a substrate, a gate line formed on the substrate, a data line insulated from and intersecting the gate line, a thin film having a drain electrode connected to each of the gate line and the data line. A first pixel electrode and a first pixel electrode formed on a transistor, a capacitive coupling electrode connected to the drain electrode, and a pixel surrounded by each of the gate line and the data line, respectively, and connected to the drain electrode; And a pixel electrode having a second pixel electrode that is separated and overlaps the capacitive coupling electrode, wherein the first pixel electrodes of the different pixels are adjacent to each other, and the second pixel electrodes are adjacent to each other. desirable.

In addition, the different pixels preferably have different positions of the first pixel electrodes connected to the drain electrodes.

In addition, it is preferable that the first pixel electrode of one pixel is adjacent to the second pixel electrode of another pixel adjacent in the vertical direction.

In addition, it is preferable that the pixel electrode has domain dividing means that is an incision.

The cutout may be connected to each other to form a gap separating the first pixel electrode and the second pixel electrode.

In addition, the gap preferably includes an oblique line portion that is 45 ° with respect to the first signal line.

In addition, a thin film transistor array panel according to an exemplary embodiment of the present invention may include a gate line transmitting a scan signal, a data line intersecting the gate line and transmitting an image signal, a thin film transistor connected to the gate line and the data line and having a drain electrode. A pixel electrode connected to the thin film transistor through a drain electrode and formed in a pixel surrounded by the gate line and the data line, respectively, wherein the pixel electrode includes first and second subpixel electrodes, The gate line includes a first gate line and a second gate line disposed with respect to the first and second subpixel electrodes, respectively, and the thin film transistor includes the first and second subpixel electrodes and the first and second subpixel electrodes. And first and second thin film transistors connecting second gate lines and the data lines, respectively. Electrodes are the first and the second electrode, and a drain, and with each other, and the first sub-pixel electrode of the other pixel are adjacent to each other, the second sub-pixel electrode may be located adjacent each other.

In addition, the different pixels preferably have different positions of the first subpixel electrode.

In addition, it is preferable that the first subpixel electrode of one pixel is adjacent to the second subpixel electrode of another pixel adjacent in the vertical direction.

The semiconductor device may further include a storage electrode line including first and second storage electrodes respectively overlapping the first and second subpixel electrodes.

The first and second subpixel electrodes may have a substantially symmetrical shape with respect to a straight line parallel to the gate line.

In addition, at least one of the first or second subpixel electrodes preferably has a cutout.

In addition, the common electrode preferably has a cutout.

In addition, it is preferable that at least one of the first or second pixel electrodes and the common electrode have cutouts arranged alternately.

The method may further include a shielding electrode overlapping the data line and positioned on the same layer as the first and second subpixel electrodes.

Then, embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, region, plate, etc. is said to be "on" another part, this includes not only the other part being "right over" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

A thin film transistor array panel according to an exemplary embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

FIG. 1 is a layout view illustrating one pixel structure in a thin film transistor array panel for a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 2 illustrates a common electrode panel for a liquid crystal display according to an exemplary embodiment of the present invention. 3 is a layout view illustrating a pixel structure, and FIG. 3 is a layout view illustrating a structure of an A pixel in a liquid crystal display according to an exemplary embodiment of the present invention including two display panels of FIGS. 1 and 2. 3 is a cross-sectional view of the liquid crystal display of FIG. 3 taken along lines IV-IV 'and VV', and FIG. 6 is a layout view illustrating a structure of a B pixel in the liquid crystal display of FIGS. 1 to 5. 7 is a circuit diagram illustrating a pixel structure in a liquid crystal display according to an exemplary embodiment of the present invention.

The liquid crystal display according to the present exemplary embodiment includes a thin film transistor array panel 100, a common electrode display panel 200, and a liquid crystal layer 3 interposed between the two display panels 100 and 200.

First, the thin film transistor array panel 100 will be described in detail with reference to FIGS. 1 and 3 to 6.

A plurality of gate lines 121 and a plurality of storage electrode lines 131 are formed on the insulating substrate 110.

The gate lines 121 mainly extend in the horizontal direction and are separated from each other, and transmit gate signals. Each gate line 121 includes a plurality of protrusions constituting the plurality of gate electrodes 124 and an end portion 129 having a large area for connecting another layer or an external device.

Each storage electrode line 131 mainly extends in the horizontal direction and is disposed adjacent to the gate line 121, and includes a plurality of sets of branches forming the first to fourth storage electrodes 133a, 133b, 133c, and 133d. do. The first storage electrode 133a and the second storage electrode 133b extend in the vertical direction, and the third and fourth storage electrodes 133c and 133d extend in an oblique direction and are disposed at both ends of the second storage electrode 133b. The first sustain electrode 133a is connected to and adjacent to each other. The third and fourth sustain electrodes 133c and 133d have inverted symmetry with respect to the center line between two adjacent gate lines 121. A predetermined voltage such as a common voltage applied to the common electrode 270 of the common electrode display panel 200 of the liquid crystal display device is applied to the sustain electrode line 131. The storage electrode line 131 includes a connection portion 133e that connects a pair of adjacent first to fourth storage electrodes 133a, 133b, 133c, and 133d to each other. 3 and 6, the third and fourth sustain electrodes 133c and 133d are inverted symmetry with respect to the data line 171 in the A-type pixel and the B-type pixel.

The gate line 121 and the storage electrode line 131 are preferably made of aluminum-based metal, silver-based metal, copper-based metal, molybdenum-based metal, chromium, titanium, tantalum, or the like, and have a single film structure or a multilayer film structure. Can be. It may include a multilayer film, for example, two films of different physical properties, that is, a lower film and an upper film thereon. One conductive film is a low resistivity metal such as aluminum (Al) or an aluminum alloy such as aluminum (Ag) or a silver alloy such as silver (Ag) or silver alloy to reduce signal delay or voltage drop. It may be made of a copper-based metal such as copper (Cu) or a copper alloy. In contrast, other conductive films have excellent contact properties with other materials, particularly indium tin oxide (ITO) and indium zinc oxide (IZO), such as chromium, molybdenum (Mo), molybdenum alloys, tantalum (Ta), or titanium (Ti). ) And the like. Good examples of the two conductive films include chromium / aluminum-neodymium (Nd) alloys or molybdenum or molybdenum alloys / aluminum alloys.

In addition, the side surfaces of the gate line 121 and the storage electrode line 131 are inclined with respect to the surface of the substrate 110, and the inclination angle is preferably about 30-80 °.

A gate insulating layer 140 made of silicon nitride (SiNx) is formed on the gate line 121 and the storage electrode line 131.

A plurality of linear semiconductors 151 made of hydrogenated amorphous silicon (amorphous silicon is abbreviated a-Si) and the like are formed on the gate insulating layer 140. Each linear semiconductor 151 extends mainly in the longitudinal direction from which a plurality of protrusions 154 extend toward the gate electrode 124. The protrusion 154 extends to an upper portion of the gate line 121 and the storage electrode line 131. The linear semiconductor 151 preferably extends wide under the data line 171 through which the connection portion 133e of the storage electrode line 131 passes to completely cover a portion of the storage electrode line 131.

A plurality of linear and island ohmic contacts 161 and 165 made of a material such as n + hydrogenated amorphous silicon doped with a high concentration of n-type impurities such as silicide or phosphorus on the semiconductor 151. Is formed. The linear contact member 161 has a plurality of protrusions 163, and the protrusions 163 and the island-like resistive contact members 165 are paired and disposed on the semiconductor 154, centered on the gate electrode 124. Face each other.

Side surfaces of the semiconductor 151 and the ohmic contacts 161 and 165 are also inclined with respect to the surface of the substrate 110, and the inclination angle is preferably 30 to 80 °.

A plurality of data lines 171 and a plurality of drain electrodes 175 separated therefrom are formed on the ohmic contacts 161 and 165 and the gate insulating layer 140, respectively.

The data line 171 mainly extends in the vertical direction and crosses the gate line 121 and the storage electrode line 131 and transmits a data voltage. Each data line 171 has a wide end portion 179 for connection with another layer or an external device.

Each drain electrode 175 includes an extension that extends wide. Each of the data lines 171 includes a plurality of protrusions, which are bent to partially surround one end portion of the drain electrode 175 positioned on the semiconductor 154 to form the source electrode 173. One gate electrode 124, one source electrode 173, and one drain electrode 175 together with the protrusion 154 of the semiconductor form one thin film transistor (TFT), and a channel of the thin film transistor. A channel is formed in the protrusion 154 between the source electrode 173 and the drain electrode 175.

In addition, the drain electrode 175 includes a capacitive coupling electrode 176 extending in the vertical direction to overlap the second storage electrode 133b. The capacitive coupling electrode 176 is connected to each other and has two diagonal portions 176a and 176b parallel to the third and fourth sustain electrodes 133c and 133d, respectively. Like the third and fourth sustain electrodes 133c and 133d, the two oblique portions 176a and 176b are inverted symmetrical with respect to the data line 171 in the A pixel and the B pixel.

On the same layer as the data line 171, a plurality of under-bridge metal pieces 178 are formed on the gate line 121, and the bridge metal pieces 178 are formed on the gate line 121. It is arranged to overlap with.

The data line 171 and the drain electrode 175 preferably include a refractory metal such as chromium or molybdenum-based metal, tantalum and titanium, and a single layer structure or a conductive film such as molybdenum, molybdenum alloy, and chromium (not shown). ) And a conductive film (not shown), which is an aluminum-based metal located above or below the structure, may have a multilayer structure.

Similar to the gate line 121 and the storage electrode line 131, the data line 171 and the drain electrode 175 are inclined at an angle of about 30-80 °, respectively.

The ohmic contacts 161 and 165 exist only between the semiconductor 151 below and the data line 171 and the drain electrode 175 above and serve to lower the contact resistance. The linear semiconductor 151 has a portion exposed between the source electrode 173 and the drain electrode 175 and not covered by the data line 171 and the drain electrode 175.

A passivation layer 180 is formed on the data line 171 and the drain electrode 175 and the portion of the semiconductor 151 that is not covered by them. The passivation layer 180 is a-Si: C: O, a-Si: O: F, which is formed of an organic material having excellent planarization characteristics and photosensitivity, and plasma enhanced chemical vapor deposition (PECVD). The low dielectric constant insulating material of 4.0 or less, or an inorganic material, such as silicon nitride and silicon oxide, is preferable. It may have a dual structure including a lower inorganic film and an upper organic film.

The passivation layer 180 is formed with a plurality of contact holes 182 and 185 respectively exposing the extension portion of the drain electrode 175 and the end portion 179 of the data line 171, and the gate insulating layer 140. ), A plurality of contact holes 181, 183a, and 183b exposing a portion of the end portion 129 of the gate line 121 and the sustain electrode line 131 are formed. The contact holes 181, 182, 183a, 183b, and 185 may be made in various shapes such as polygons or circles. Sidewalls of the contact holes 181, 182, 183a, 183b, 185 may be inclined or stepped at an angle of 30 ° to 85 °.

On the passivation layer 180, a plurality of first and second pixel electrodes 190a and 190b made of ITO or IZO, a sustain electrode line connecting leg 83, and a plurality of contact assistants 81 and 82. ) Is formed. Alternatively, the first / second pixel electrodes 190a and 190b may be made of a transparent conductive polymer, and in the case of a reflective liquid crystal display device, the first / second pixel electrodes 190a and 190b may be an opaque reflective metal. It can also be made. In this case, the contact assistants 81 and 82 may be made of a material different from that of the pixel electrode 190, for example, ITO or IZO.

The storage electrode line connecting leg 83 crosses the gate line 121 and the source electrode 173, and is disposed on the opposite side of the first storage electrode with the gate line 121 interposed therebetween through the contact holes 183a and 183b. It is connected to the exposed end of 133a and the exposed part of sustain electrode line 131. The sustain electrode lines 131 including the sustain electrodes 133a and 133b can be used to repair the defects of the sustain electrode line connecting leg 83 and the metal piece 178 and the gate line 121 or the data line 171 or the thin film transistor. have. When the gate line 121 is repaired, the gate line 121 is electrically connected to the gate line 121 and the storage electrode line connecting leg 83 by laser irradiation at the intersection of the gate line 121 and the storage electrode line connecting leg 83. ) And the storage electrode line 131 are electrically connected to each other. At this time, the metal piece 178 strengthens the electrical connection between the gate line 121 and the sustain wiring connecting bridge 83.

The first and second pixel electrodes 190a and 190b are physically and electrically connected to the drain electrode 175 through the contact hole 185 to receive a data voltage from the drain electrode 175. The first and second pixel electrodes 190a and 190b to which the data voltage is applied rearrange the liquid crystal molecules of the liquid crystal layer by generating an electric field together with the common electrode 270.

The first and second pixel electrodes 190a and 190b and the common electrode 270 form a capacitor (hereinafter referred to as a "liquid crystal capacitor") to maintain an applied voltage even after the thin film transistor is turned off. In order to enhance the voltage holding capability, another capacitor connected in parallel with the liquid crystal capacitor is provided, which is called a storage capacitor, which overlaps the first and second pixel electrodes 190a and 190b and the storage electrode line 131. And the like, in order to increase the capacitance of the storage capacitor, that is, the storage capacitance, the storage electrodes 133a, 133b, 133c, and 133d are disposed on the storage electrode lines 131 to the first and second pixel electrodes 190a and 190b. By extending and expanding the connected drain electrode 175, the distance between terminals is made close and the overlapping area is increased.

In this case, the first pixel electrode 190a and the second pixel electrodes 190a and 190b are separated from each other, and the first pixel electrode 190a is positioned above and below the second pixel electrode 190b. The second pixel electrode 190b is sandwiched between two portions of the first pixel electrode 190a. Two portions of the first pixel electrode 190a and the second pixel electrode 190b face each other and have sides that are inclined by ± 45 ° with respect to the gate line 121, so that a center line between two neighboring gate lines 121 is adjacent to each other. It has a symmetrical structure with respect to.

Here, each of the first pixel electrodes 190a is connected to the drain electrode 175 through the contact hole 185 and receives a data voltage directly therefrom, whereas the second pixel electrode 190b is the first pixel electrode ( It overlaps with the capacitive coupling electrode 176 connected to 190a. Therefore, the second pixel electrode 190b is electromagnetically coupled (capacitive) to the first pixel electrode 190a.

Each of the first pixel electrodes 190a is chamfered at the left corner in the A pixel, and is chamfered at the right corner in the B pixel, and the chamfered hypotenuse forms an angle of about ± 45 degrees with respect to the gate line 121.

The first and second pixel electrodes 190a and 190b have a center cutout 91, a lower cutout 92a, and an upper cutout 92b, and the first / second pixel electrodes 190a and 190b include these. It is divided into a plurality of areas by the cutouts 91, 92a and 92b. The cutouts 91, 92a, and 92b have almost inverted symmetry with respect to a horizontal centerline that bisects the first and second pixel electrodes 190a and 190b in parallel with the gate line 121. In this case, the lower and upper cutouts 92a and 92b are connected to each other to form a gap that divides the first pixel electrode 190a and the second pixel electrode 190b.

The lower and upper cutouts 92a and 92b extend obliquely from the right side to the left side of the first and second pixel electrodes 190a and 190b in the A pixel, and are obliquely extending from the left side to the right side in the B pixel. The first and second pixel electrodes 190a and 190b extend to each other and are positioned on the lower half and the upper half, respectively. The lower and upper cutouts 92a and 92b extend perpendicularly to each other at an angle of about 45 degrees with respect to the gate line 121.

One central cutout 91 is disposed at the center of the second pixel electrode 190b and has an inlet at the right and left sides of the A and B pixels. The inlet of the central incision 91 has a pair of hypotenuses substantially parallel to the lower incision 92a and the upper incision 92b, respectively.

Accordingly, the lower half of the first and second pixel electrodes 190a and 190b is divided into two regions by the lower cutout 92a, and the upper half is also divided into two regions by the upper cutout 92b. In the A and B pixels, the first and second pixel electrodes 190a and 190b have an inverted symmetry structure. In this case, the number of regions or the number of cutouts may vary depending on the size of the pixel, the ratio of the length of the horizontal side and the vertical side of the pixel electrode, the type and characteristics of the liquid crystal layer 3, and the inclination direction may also vary.

The first and second pixel electrodes 190a and 190b may also overlap the neighboring gate line 121 or the data line 171 to increase the aperture ratio.

The contact auxiliary members 81 and 82 are connected to the end portion 129 of the gate line 121 and the end portion 179 of the data line 171 through the contact holes 181 and 182, respectively. The contact auxiliary members 81 and 82 complement and protect the exposed end portions 129 of the gate lines 121 and the exposed end portions 179 of the data lines 171 and external devices and protect them. To do. The contact auxiliary members 81 and 82 are connected to the external device through an anisotropic conductive film (not shown) or the like.

When the gate driving circuit is integrated in the thin film transistor array panel 100, the contact auxiliary member 81 may serve to connect the metal layer of the gate driving circuit and the gate line 121. Similarly, when the data driving circuit is integrated in the thin film transistor array panel 100, the contact auxiliary member 82 may serve to connect the metal layer and the data line 171 of the data driving circuit.

Next, the common electrode display panel 200 will be described with reference to FIGS. 2 to 6.

A light blocking member 220 is formed on an insulating substrate 210 made of transparent glass, and the light blocking member 220 faces the first / second pixel electrodes 190a and 190b and faces the first / second pixel electrode. It has a plurality of openings having almost the same shape as 190a and 190b. Alternatively, the light blocking member 220 may be formed of a portion corresponding to the data line 171 and a portion corresponding to the thin film transistor.

A plurality of color filters 230 are also formed on the substrate 210 and are mostly located in an area surrounded by the light blocking member 220. The color filter 230 may extend in the vertical direction along the first and second pixel electrodes 190a and 190b. The color filter 230 may display one of primary colors such as red, green, and blue.

An overcoat 250 is formed on the color filter 230.

The common electrode 270 formed of a transparent conductor such as ITO or IZO is formed on the overcoat 250.

The common electrode 270 has a plurality of sets of cutouts 71, 72a, and 72b.

A pair of cutouts 71, 72a, 72b face the first and second pixel electrodes 190a, 190b and have a central cutout 71, a lower cutout 72a, and an upper cutout 72b. It includes. Each of the cutouts 71, 72a, 72b is disposed between the cutouts 91, 92a, 92b of the adjacent first / second pixel electrodes 190a, 190b or the edge cutouts 92a, 92b and the first / seconds. The pixel electrodes 190a and 190b are disposed between the hypotenuses. In addition, each of the cutouts 71, 72a, and 72b includes at least one diagonal line extending in parallel with the cutouts 91, 92a and 92b of the first and second pixel electrodes 190a and 190b.

Each of the lower and upper cutouts 72a and 72b extends from the right side of the first / second pixel electrode 190a and 190b toward the lower or upper side in the A pixel and approximately the first / second pixel electrode in the B pixel. It includes an oblique portion extending from the left side of the 190a, 190b toward the lower or upper side. In addition, a horizontal portion and a vertical portion extending from the ends of the diagonal portion and overlapping the sides along the sides of the first and second pixel electrodes 190a and 190b and forming an obtuse angle with the diagonal portion.

The central cutout 71 extends horizontally from the left side of the first and second pixel electrodes 190a and 190b in the A pixel and extends horizontally from the right side in the B pixel, the center at the end of the central horizontal part. A pair of diagonal portions extending toward the left and right sides of the first and second pixel electrodes 190a and 190b at an oblique angle with the horizontal portion, and the first and second pixel electrodes 190a and 190b from each end of the diagonal portion. A longitudinal longitudinal portion extending over and overlapping the left and right sides along the left and right sides of the oblique angle. Therefore, the cutouts 71, 72a, and 72b of the common electrode 270 in the A pixel and the B pixel have a mirror image symmetry structure.

The number of cutouts 71, 72a, 72b may vary depending on the design element, and the light blocking member 220 overlaps the cutouts 71, 72a, 72b so that the light leakage near the cutouts 71, 72a, 72b may occur. Can be blocked. In this embodiment, the oblique portions 17a and 176b of the capacitive coupling electrode 176 overlap the cut portions 71, 72a and 72b to block light leakage near the cut portions 71, 72a and 72b.

Vertical alignment layers 11 and 21 are coated on the inner surfaces of the display panels 100 and 200, and polarizing plates 12 and 22 are provided on the outer surfaces thereof.

The alignment layers 11 and 21 may be horizontal alignment layers.

The transmission axes of the two polarizing plates 12 and 22 are orthogonal, and one transmission axis is parallel to the gate line 121. In the case of a reflective liquid crystal display, one of the two polarizing plates 12 and 22 may be omitted.

A phase retardation film may be interposed between the display panels 100 and 200 and the polarizers 12 and 22 to compensate for the delay value of the liquid crystal layer 3, respectively. The phase retardation film has birefringence and serves to reversely compensate for the birefringence of the liquid crystal layer 3. As the retardation film, a uniaxial or biaxial optical film can be used, and in particular, a negative uniaxial optical film can be used.

The liquid crystal display may also include a backlight unit for supplying light to the polarizers 12 and 22, the phase retardation film, the display panels 100 and 200, and the liquid crystal layer 3.

The liquid crystal layer 3 has negative dielectric anisotropy, and the liquid crystal molecules 310 of the liquid crystal layer 3 are aligned such that their major axes are perpendicular to the surfaces of the two display panels in the absence of an electric field. Therefore, incident light does not pass through the quadrature polarizers 12 and 22 and is blocked.

When a common voltage is applied to the common electrode 270 and a data voltage is applied to the first and second pixel electrodes 190a and 190b, an electric field substantially perpendicular to the surface of the display panel is generated. The liquid crystal molecules 310 try to change the direction of the long axis perpendicular to the direction of the electric field in response to the electric field. Meanwhile, the cutouts 71, 72a, 72b, 91, 92a and 92b of the common electrode 270 and the first / second pixel electrodes 190a and 190b and the first / second pixel electrodes 190a and 190b may be formed. The hypotenuse distorts the electric field, creating a horizontal component that determines the tilt direction of the liquid crystal molecules. The horizontal component of the electric field is perpendicular to the sides of the cutouts 71, 72a, 72b, 91, 92a, 92b and the hypotenuse of the first / second pixel electrodes 190a, 190b. In addition, the horizontal components of the main electric field at two opposite sides of the cutouts 71, 72a, 72b, 91, 92a, and 92b are opposite to each other.

Through these electric fields, the cutouts 71, 72a, 72b, 91, 92a, and 92b control the direction in which the liquid crystal molecules of the liquid crystal layer 3 are inclined. Defined by adjacent cutouts 71, 72a, 72b, 91, 92a, 92b or defined by right and left hypotenuses of cutouts 72a, 72b and first / second pixel electrodes 190a, 190b. The liquid crystal molecules in each domain are inclined in a direction perpendicular to the longitudinal direction of the cutouts 71, 72a, 72b, 91, 92a, and 92b. The two longest sides of each domain are almost parallel to each other, and form approximately ± 45 degrees with the gate line 121. Most of the liquid crystal molecules in the domain are inclined in four directions, thereby expanding the viewing angle.

The width of the cutouts 71, 72a, 72b, 91, 92a, 92b is preferably about 9 μm to about 12 μm.

The at least one cutout 71, 72a, 72b, 91, 92a, 92b may be replaced with a protrusion (not shown) or depression (not shown). The protrusions may be made of organic or inorganic materials and may be disposed above or below the field generating electrodes 190a, 190b, and 270, and the width thereof is preferably about 5 μm to about 10 μm.

Meanwhile, when the inclination direction of the liquid crystal molecules 310 and the transmission axis of the polarizers 12 and 22 are 45 degrees, the highest luminance can be obtained. In the present embodiment, the inclination direction of the liquid crystal molecules 310 in all domains is the gate line. The gate line 121 is perpendicular or horizontal to the edges of the display panels 100 and 200 at an angle of 45 ° with the 121. Therefore, in the present exemplary embodiment, when the transmission axes of the polarizers 12 and 22 are attached to be perpendicular or parallel to the edges of the display panels 100 and 200, the highest luminance can be obtained and the polarizers 12 and 22 can be manufactured at low cost. Can be.

In the liquid crystal display according to the exemplary embodiment of the present invention, as described above, the second pixel electrode 190b is electromagnetically coupled (capacitively coupled) to the first pixel electrode 190a. Referring to FIG. 7, the first pixel electrode 190a is directly connected to the thin film transistor Q through the drain electrode 175 and transmitted through the data line 171 through the thin film transistor Q. In response to the voltage being applied, the voltage of the second pixel electrode 190b changes in capacitive coupling with the first pixel electrode 190a. In this embodiment, the absolute value of the voltage of the second pixel electrode 190b is always lower than that of the first pixel electrode 190a, and the reason thereof will be described in detail.

In FIG. 7, Clca represents a liquid crystal capacitor formed between the first pixel electrode 190a and the common electrode 270, and Csta represents a storage capacitor formed between the first pixel electrode 190a and the storage electrode line 131. . Clcb represents the liquid crystal capacitance formed between the second pixel electrode 190b and the common electrode 270, Cstb represents the storage capacitance formed between the second pixel electrode 190b and the storage electrode line 131, and Ccp represents A coupling capacitor formed between the second pixel electrode 190b and the first pixel electrode 190a is shown.

When the voltage of the first pixel electrode 190a with respect to the voltage of the common electrode 270 is called Va, and the voltage of the second pixel electrode 190b is called Vb, according to the voltage division law,

Vb = Va × [Ccp / (Ccp + Clcb + Cstb)]

Since Ccp / (Ccp + Clcb + Cstb) cannot always be greater than 1, Vb is always smaller than Va. At this time, the voltage of the common electrode 270 for Clca and Clcb and the voltages of the sustain electrode lines 131a and 131b for Csta and Cstb may be different. In this case, the voltage of the common electrode 270 applied to Clca and Clcb is the same. The absolute value of the image signal voltage Va applied to Clca always has a value greater than the absolute value of the image signal voltage Vb applied to Clcb. As such, when two pixel electrodes having different voltages are disposed in one pixel, the liquid crystal molecules may be driven at different voltages to be inclined at different tilt angles, thereby improving side visibility.

By adjusting Ccp, the ratio of Vb to Va can be adjusted. The adjustment of Ccp is possible by adjusting the overlapping area and distance of the capacitive coupling electrodes 176a and 176b and the second pixel electrode 190b. The overlap area can be easily adjusted by changing the width of the capacitive coupling electrode 176, and the distance can be adjusted by changing the formation position of the capacitive coupling electrode 176. That is, in the exemplary embodiment of the present invention, the capacitive coupling electrode 176 is formed on the same layer as the data line 171, but the capacitive coupling electrode 176 and the second pixel are formed on the same layer as the gate line 121. The distance between the electrodes 190b may be increased. At this time, it is preferable that Vb is 0.6 to 0.8 times with respect to Va.

Meanwhile, in another embodiment, a voltage whose absolute value is always higher than the voltage of the first pixel electrode 190a may be applied to the second pixel electrode 190b, which may be applied to the second pixel electrode 190b such as a common voltage. This is achieved by capacitively coupling the first pixel electrode 190a while an arbitrary voltage is applied.

The area ratio of the second pixel electrode 190b through which the high or low pixel voltage is transmitted with respect to the first pixel electrode 190a through which the image signal is directly transmitted is in a range of 1: 0.85-1: 1.15, and the first pixel Two or more second pixel electrodes 190b may be disposed to be capacitively coupled to the electrodes 190a.

As described above, in the liquid crystal display according to the exemplary embodiment of the present invention, the first and second pixel electrodes 190a and 190b and the common electrode 270 are arranged in mirror symmetry with each other, as shown in FIGS. 3 and 7. A and B pixels including the cut portions 71, 72a, and 72b. In this case, A pixels and B pixels may be arranged in various ways, which will be described in detail with reference to the accompanying drawings.

FIG. 8 is a layout view of an arrangement of pixels in a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 9 is a layout view of an arrangement of pixels in a liquid crystal display according to another exemplary embodiment of the present invention.

 As shown in FIG. 8, in the liquid crystal display according to the exemplary embodiment of the present invention, the A pixels and the B pixels are arranged in the same row direction, but are alternately arranged in the column direction.

Meanwhile, as shown in FIG. 9, in the liquid crystal display according to another exemplary embodiment of the present invention, the A pixels and the B pixels are alternately arranged in units of two rows, unlike the previous exemplary embodiment.

The liquid crystal display according to the exemplary embodiment of the present invention includes first and second pixel electrodes 190a and 190b and cutouts 71, 72a and 72b of the common electrode 270 arranged in a symmetrical structure. A and B pixels are alternately arranged. Therefore, domains inclined at different inclination angles are symmetrically arranged so that asymmetry of visibility disappears and uniform visibility can be secured. As a result, it is not necessary to arrange the cutouts 71, 72a, and 72b of the common electrode 270 asymmetrically to improve visibility of left and right asymmetry, and the aperture ratio may be maximized.

In this case, as long as the area or number of the A pixels and the B pixels that are symmetrically arranged on the entire thin film transistor array panel is the same, the arrangement of the pixels may be variously changed, and the pixels having different arrangement structures may be three or more.

A liquid crystal display according to another exemplary embodiment of the present invention will be described in detail with reference to FIGS. 10 and 11.

FIG. 10 is a layout view illustrating a structure of a liquid crystal display according to another exemplary embodiment. FIG. 11 is a cross-sectional view of the liquid crystal display of FIG. 10 taken along the line XI-XI ′.

10 and 11, the liquid crystal display according to the present exemplary embodiment also includes a thin film transistor array panel 100, a common electrode display panel 200, and a liquid crystal layer 3 inserted between the two display panels 100 and 200. And a pair of polarizers 12 and 22 attached to outer surfaces of the two display panels 100 and 200.

The layered structures of the display panels 100 and 200 according to the present exemplary embodiment are substantially the same as those of FIGS. 1 to 6.

Referring to the thin film transistor array panel 100, a plurality of holding lines including the plurality of gate lines 121 including the gate electrode 124 and the first to fourth storage electrodes 133a, 133b, 133c, and 133d, respectively. The electrode line 131 is formed on the substrate 110, and the gate insulating layer 140, the linear semiconductor 151, and the ohmic contacts 161 and 165 are sequentially formed thereon. A plurality of data lines 171 including the source electrode 173 and a plurality of drain electrodes 175 including the plurality of capacitive coupling electrodes 176 are formed on the gate insulating layer 140, and the passivation layer 180. A plurality of contact holes 181, 182, and 185 are formed in the passivation layer 180 and the gate insulating layer 140. A plurality of first / second pixel electrodes 190a and 190b and a plurality of contact auxiliary members 81 and 82 are formed on the passivation layer 180, and an alignment layer 11 is coated thereon.

Referring to the common electrode display panel 200, the light blocking member 220, the plurality of color filters 230, the overcoat 250, the common electrode 270, and the alignment layer 21 are formed on the insulating substrate 210. have.

Unlike the liquid crystal display of FIGS. 1 to 6, the linear semiconductor 151 has a shape substantially the same as that of the data line 171, the drain electrode 175, and the ohmic contacts 161 and 165 thereunder. However, the protrusion 154 of the linear semiconductor 151 has a portion not covered by the data line 171 and the drain electrode 175, such as a portion between the source electrode 173 and the drain electrode 175. The semiconductor 151 and the island-shaped ohmic contact 165 extend in the same shape to the lower portion of the capacitive coupling electrode 176.

The features of the present embodiment can be similarly applied to the liquid crystal display shown in FIGS. 1 to 6.

12 is a layout view illustrating a structure of a C pixel in a thin film transistor array panel for a liquid crystal display according to another exemplary embodiment of the present invention, and FIG. 13 is a cross-sectional view of another exemplary embodiment including two display panels of FIGS. 12 and 2. FIG. 14 is a layout view illustrating an arrangement of pixels in a liquid crystal display according to another exemplary embodiment. FIG. 15 is a layout view of pixels in a liquid crystal display according to another exemplary embodiment. It is the layout which shows another arrangement structure.

The structure of the C pixel of the liquid crystal display according to the exemplary embodiment of FIG. 12 and FIG. 13 has the following difference compared with that of the A pixel of FIG. 3.

That is, the second pixel electrode 190b is connected to the drain electrode 175 through the contact hole 185 and receives the data voltage directly therefrom, whereas the first pixel electrode 190a is the second pixel electrode 190b. ) And the capacitive coupling electrodes 176a and 176b connected to each other. Therefore, the first pixel electrode 190a is electromagnetically coupled (capacitive) to the second pixel electrode 190b.

As described above, in the A pixel, the first pixel electrode 190a serves as the main pixel, and the second pixel electrode 190b serves as the subpixel, and in the C pixel, the first pixel electrode 190a serves as the subpixel and the second pixel electrode. 190b serves as a subpixel.

In the case of the liquid crystal display including only A pixels, since the main pixel and the subpixel are continuously disposed at the same position, the left side is the main pixel 190a, that is, the high voltage region, and the right side is the subpixel based on the data line 171. 190b, that is, since it is a low voltage region, when viewed from the left and the right, respectively, the amount of transmitted light is different, so a difference in visibility between left and right occurs.

That is, when one pixel is viewed from the right side, the gamma distortion amount of each voltage appears to be small due to the relatively low luminance, whereas when viewed from the left side, the gamma distortion amount is large due to the relatively higher luminance than the right side, so that the left and right visibility differences Will occur.

In order to prevent this, in another embodiment of the present invention, as illustrated in FIG. 14, A pixels and C pixels are repeatedly arranged. In this case, the main pixel 190a of the A pixel and the main pixel 190b of the C pixel are disposed left and right on the boundary of the data line 171, and the subpixel 190b of the A pixel and the subpixel 190a of the C pixel are disposed. Is arranged left and right with respect to the data line 171. Therefore, since the adjacent pixels are pixels to which the same voltage is applied, the left and right luminance differences do not occur, and the left and right visibility do not occur.

As shown in FIG. 15, the main pixels 190a of the A pixels are arranged so as not to be adjacent to the same A pixels in all the up, down, left, and right directions, so that the subpixels are not connected in a line in the up and down direction, and the main pixels in the up and down direction. The pixels and sub-pixels are alternately arranged to have an overall mixing effect. Therefore, it is possible to prevent the occurrence of bands and the like in the vertical direction as a whole, thereby solving the problems of left and right and vertical asymmetry of visibility caused by side light leakage or texture.

Such another embodiment of the present invention can be applied not only to the case where the area ratios of the main pixel and the subpixel are the same, but also to the case where the area ratios are different.

On the other hand, the above embodiment is a method of electromagnetic coupling between the separated main pixel and the sub-pixel using one thin film transistor, or the method of separating and driving the main pixel and the sub-pixel by connecting the thin film transistor for each domain Even if the contents of the present invention can be applied.

FIG. 16 is a layout view illustrating a structure of a D or E pixel in a thin film transistor array panel for a liquid crystal display according to another exemplary embodiment of the present invention, and FIG. 17 illustrates a common electrode panel for a liquid crystal display according to another exemplary embodiment of the present invention. FIG. 18 is a layout view illustrating one pixel structure, and FIG. 18 is a layout view of a liquid crystal display according to another exemplary embodiment including the two display panels of FIGS. 16 and 17, and FIGS. 19 and 20 are liquid crystal displays of FIG. 18. FIG. 21 is a cross-sectional view of the device cut along the lines XIX-XIX 'and IIX-IIX', and FIG. 21 is a layout view illustrating an arrangement of pixels in a liquid crystal display according to another exemplary embodiment of the present invention, and FIG. FIG. Is a layout view illustrating another arrangement structure of pixels in a liquid crystal display according to another exemplary embodiment of the present invention. FIG.

16 to 20, a plurality of pairs of first and second gate lines 121a and 121b and a plurality of storage electrode lines are disposed on an insulating substrate 110 made of transparent glass or the like. 131 is formed.

The gate lines 121a and 121b mainly extend in the horizontal direction, are physically and electrically separated from each other, and transmit gate signals. The first and second gate lines 121a and 121b are disposed at an upper side and a lower side, respectively, and the plurality of first and second gate electrodes 124a and 124b protruding from the lower side and the upper side of the other layer or an external driving circuit are disposed. It includes wide end portions 129a and 129b for connection. In addition, the second gate line 121b includes protrusions 125 extending upward and downward, respectively, and the protrusions 125 have a boundary inclined by ± 45 ° with respect to the gate lines 121a and 121b.

The storage electrode line 131 extends mainly in the horizontal direction and is closer to the first gate line 121a than the second gate line 121b. Each storage electrode line 131 includes a plurality of pairs of first and second storage electrodes 137a and 137b extending up and down. The second storage electrode 137b has a longer length and a width than the first storage electrode 137a. Is narrow.

 However, the shape and arrangement of the storage electrode lines 131 including the storage electrodes 137a and 137b may be modified in various forms.

The gate line 121 and the storage electrode line 131 may be formed of aluminum-based metals such as aluminum (Al) and aluminum alloys, silver-based metals such as silver (Ag) and silver alloys, and copper-based metals such as copper (Cu) and copper alloys. , Molybdenum-based metals such as molybdenum (Mo) and molybdenum alloy, chromium (Cr), titanium (Ti), tantalum (Ta) and the like is preferably made. However, the gate line 121 and the storage electrode line 131 may have a multilayer structure including two conductive layers (not shown) having different physical properties. One of the conductive films may be formed of a low resistivity metal such as an aluminum-based metal, a silver-based metal, or a copper-based metal so as to reduce signal delay or voltage drop between the gate line 121 and the storage electrode line 131. Is done. In contrast, the other conductive film is made of a material having excellent contact properties with other materials, particularly indium tin oxide (ITO) and indium zinc oxide (IZO), such as molybdenum-based metals, chromium, titanium, tantalum, and the like. A good example of such a combination is a chromium bottom film and an aluminum top film, and an aluminum bottom film and a molybdenum top film. However, the gate line 121 and the storage electrode line 131 may be made of various metals and conductors.

In addition, side surfaces of the gate line 121 and the storage electrode line 131 are inclined with respect to the surface of the substrate 110, and the inclination angle is about 30-80 °.

A gate insulating layer 140 made of silicon nitride (SiNx) is formed on the gate lines 121a and 121b and the storage electrode line 131.

A plurality of island-like semiconductors 154a, 154b, and 152 made of hydrogenated amorphous silicon, polycrystalline silicon, and the like are formed on the gate insulating layer 140. The island semiconductors 154a and 154b are mainly located above the gate electrodes 124a and 124b.

A plurality of isotropic ohmic contacts 163a, 163b, 165a, and 165b formed of a material such as n + hydrogenated amorphous silicon doped with a high concentration of silicide or n-type impurities on the semiconductors 154a and 154b. ) Is formed. The two islands of ohmic contacts 163a, 163b, 165a, and 165b are arranged in pairs and disposed on the semiconductors 154a and 154b, respectively, facing each other with respect to the gate electrodes 124a and 124b. Although not shown, island contact members are also formed on the semiconductor 152.

Side surfaces of the semiconductors 154a, 154b, and 152 and the ohmic contacts 163a, 163b, and 165a and 165b are also inclined with respect to the surface of the substrate 110 and have an inclination angle of 30-80 °.

A plurality of data lines 171 and a plurality of pairs of first and second drain electrodes 175a and 175b are disposed on the ohmic contacts 163a, 163b, 165a, and 165b and the gate insulating layer 140, respectively. ) Is formed.

The data line 171 mainly extends in the vertical direction and crosses the gate line 121 and the storage electrode line 131 and transmits a data voltage. Each data line 171 is connected to a plurality of first and second source electrodes 173a and 173b extending toward the first and second drain electrodes 175a and 175b, respectively, from another layer or an external device. It includes an end portion 179 extending in width.

The first and second drain electrodes 175a and 175b extend from the rod-shaped end portions positioned on the semiconductors 154a and 154b, respectively, and have a large area that overlaps the first and second storage electrodes 137a and 137b. 177a, 177b). Each of the source electrodes 173a and 173b is bent to surround the rod-shaped ends of the drain electrodes 175a and 175b. The first and second gate electrodes 124a and 124b, the first and second source electrodes 173a and 173b, and the first and second drain electrodes 175a and 175b are formed together with the island-like semiconductors 154a and 154b. And a second thin film transistor (TFT) Qa / Qb, and the channels of the thin film transistors Qa / Qb are the first / second source electrodes 173a / 173b and the drain electrode 175a. / 175b) between the semiconductors 154a and 154b.

The data line 171 and the drain electrodes 175a and 175b are preferably made of refractory metals such as chromium, molybdenum-based metals, tantalum and titanium, and an underlayer (not shown) such as refractory metals and the like. It may have a multi-layer structure consisting of a low-resistance material upper layer (not shown) disposed above. Examples of the multilayer film structure include a triple film of molybdenum film, aluminum film, and molybdenum film in addition to the above-described double film of chromium lower film and aluminum upper film or aluminum lower film and molybdenum upper film.

Similar to the gate line 121 and the storage electrode line 131, the data line 171 and the drain electrodes 175a and 175b are also inclined at an angle of about 30 to 80 °.

The ohmic contacts 163a, 163b, 165a, and 165b exist only between the semiconductors 154a and 154b below and the data lines 171 and drain electrodes 175a and 175b above and serve to lower contact resistance. do. The island-type semiconductors 154a and 154b have portions exposed between the source electrodes 173a and 173b and the drain electrodes 175a and 175b, and not exposed to the data line 171 and the drain electrodes 175a and 175b. Since the width is increased at the portion where the lines 121a and 121b meet, the data line 171 covers the boundary portion of the gate lines 121a and 121b through which the data line 171 passes, thereby smoothing the profile of the surface at the boundary portion, thereby disconnecting the data line 171. To prevent. The island type semiconductor 152 is formed at a portion where the storage electrode line 131 and the data line 171 meet to cover the boundary of the storage electrode line 131 through which the data line 171 passes, thereby smoothing the profile of the surface at these boundary portions. Disconnection of the data line 171 is prevented.

A passivation layer 180 is formed on the data line 171, the drain electrodes 175a and 175b, and the exposed portions of the semiconductors 154a and 154b. The passivation layer 180 is formed of an inorganic material made of silicon nitride or silicon oxide, an organic material having excellent planarization characteristics, photosensitivity, or a-Si: C: O formed by plasma enhanced chemical vapor deposition (PECVD), It consists of low dielectric constant insulating materials, such as a-Si: O: F. However, the passivation layer 180 may have a double layer structure of the lower inorganic layer and the upper organic layer in order to protect the exposed portion of the semiconductor 151 while maintaining the excellent characteristics of the organic layer.

The passivation layer 180 includes a plurality of contact holes 182, 187a, and 187b exposing end portions 179 of the data line 171 and the extended portions 177a and 177b of the drain electrodes 175a and 175b, respectively. A plurality of contact holes 181a and 181b exposing end portions 129a and 129b of the gate lines 121a and 121b are formed in the passivation layer 180 and the gate insulating layer 140.

On the passivation layer 180, a plurality of pixel electrodes 190 including the first and second subpixel electrodes 190a and 190b, a plurality of shielding electrodes 88, and a plurality of contact assistants, respectively. ) 81a, 81b, 82 are formed. The pixel electrode 190, the shielding electrode 88, and the contact assistants 81a, 81b, and 82 may be formed of a transparent conductor such as ITO or IZO or a reflective conductor such as aluminum.

The first and second subpixel electrodes 190a and 190b are physically and electrically connected to the first and second drain electrodes 175a and 175b through the contact holes 185a and 185b to form the first and second drain electrodes ( Data voltage is applied from 175a / 175b).

The subpixel electrodes 190a and 190b to which the data voltage is applied generate an electric field together with the common electrode 270 to determine the arrangement of liquid crystal molecules of the liquid crystal layer 3 between the two electrodes 190 and 270.

In addition, as described above, each of the subpixel electrodes 190a and 190b and the common electrode 270 form the liquid crystal capacitors CLCa and CLCb to maintain the applied voltage even after the thin film transistors Qa and Qb are turned off. In order to enhance the holding capability, the storage capacitors CSTa and CSTb connected in parallel with the liquid crystal capacitors CLCa and CLCb include the first and second subpixel electrodes 190a and 190b and the drain electrodes 175a and 175b connected thereto. ) And the first and second sustain electrodes 137a and 137b and the like.

Each pixel electrode 190 is chamfered at the right corner, and the chamfered hypotenuse forms an angle of about 45 degrees with respect to the gate lines 121a and 121b. In this case, each of the chamfered hypotenuses is covered by the protrusion 125 of the second gate line 121b, and the protrusions 125 serve as a light shielding film to block light leakage generated near the chamfered hypotenuse of the pixel electrode 190. . Therefore, it is possible to prevent the luminance from increasing when displaying a dark color, thereby ensuring a high contrast ratio and improving display characteristics.

The pair of first and second subpixel electrodes 190a and 190b constituting one pixel electrode 190 are engaged with each other with a gap 92 therebetween, and an outer boundary thereof is substantially rectangular.

The first subpixel electrode 190a is a rotated equilateral trapezoid and has a right side positioned near the sustain electrode 137b, a left side positioned near the data line 171, and approximately 45 ° with the gate lines 121a and 121b. It has an upper hypotenuse and a lower hypotenuse. The second subpixel electrode 190b includes a pair of trapezoids facing the hypotenuse of the first subpixel electrode 190a and a vertical portion facing the right side of the first subpixel electrode 190a. Thus, the gap 92 has a substantially uniform width and includes a vertical portion having a substantially uniform width with upper and lower diagonal portions forming about 45 ° of the gate lines 121a and 121b.

The first subpixel electrode 190a has the central cutouts 91 and 94, the second subpixel electrode 190b has the lower and upper cutouts 93a and 93b, and the first and second subpixel electrodes. Each of 190a and 190b is divided into a plurality of partitions by these incisions 91, 94, 93a and 93b.

The lower and upper cutouts 93a and 93b are positioned at the lower half and the upper half of the pixel electrode 190, respectively, and the central cutouts 91 and 94 are positioned between the lower cutout 93a and the upper cutout 93b. do. The gap 92 and the cutouts 91, 94, 93a, and 93b form approximately inversion symmetry with respect to the storage electrode line 131.

The lower and upper cutouts 93a and 93b extend from near the right side of the second subpixel electrode 190b to near the lower and upper sides, respectively, and are parallel to the lower and upper oblique portions of the gap 92.

The central cutout 91 extends from the right side of the first subpixel electrode 190a to the horizontal portion extending substantially along the storage electrode line 131, and from the horizontal portion to the left side of the first subpixel electrode 190a. A pair of diagonal lines parallel to the lower and upper incisions 93a and 93b, respectively.

The central cutout 94 is recessed in the left side of the first subpixel electrode 190a and has a pair of hypotenuses parallel to the lower and upper cutouts 93a and 93b, respectively.

Therefore, the lower half of the first subpixel electrode 190a is divided into two parts by the central cutout 91, and the upper half is also divided into two parts by the central cutout 91 and the second subpixel electrode 190b. The lower half of is divided into two parts by the lower incision 93a, and the upper half is also divided into two parts by the upper incision 93b.

The number of regions or the number of cutouts varies depending on the size of the pixel, the ratio of the lengths of the horizontal and vertical sides of the first and second subpixel electrodes 190a and 190b, and the type and characteristics of the liquid crystal layer 3. Hereinafter, for convenience of description, the gap 92 is also expressed as a cutout.

In addition, the first subpixel electrode 190a overlaps the first gate line 121a, and the second subpixel electrode 190b overlaps both the first and second gate lines 121a and 121b.

The shielding electrode 88 extends along the data line 171 and completely covers the data line 171. A common voltage is applied to the shielding electrode 88, and is connected to the storage electrode line 131 through a contact hole (not shown) of the passivation layer 180 and the gate insulating layer 140, or the common voltage is applied to the thin film transistor array panel. The display device may be connected to a short point (not shown) transferred from the 100 to the common electrode display panel 200. At this time, it is preferable to minimize the distance between the shielding electrode 88 and the pixel electrode 190 so that the aperture ratio decreases to a minimum.

As such, when the shielding electrode 88 to which the common voltage is applied is disposed on the data line 171, the shielding electrode 88 is disposed between the data line 171 and the pixel electrode 190, and the data line 171 and the common electrode ( By blocking the electric field formed between the 270, the voltage distortion of the pixel electrode 190 and the signal delay of the data voltage transmitted by the data line 171 are reduced.

Also, in order to prevent a short circuit between the pixel electrode 190 and the shielding electrode 88, a distance is required between them so that the pixel electrode 190 is further away from the data line 171, thereby reducing the parasitic capacitance therebetween. Furthermore, since the permittivity of the liquid crystal layer 3 is higher than that of the passivation layer 180, the parasitic capacitance between the data line 171 and the shielding electrode 88 is absent when the shielding electrode 88 is absent. It is smaller than the parasitic capacitance between 171 and the common electrode 270.

In addition, since the pixel electrode 190 and the shielding electrode 88 are made of the same layer, the distance between them is kept constant and thus the parasitic capacitance between them is constant. Although the parasitic capacitance between the pixel electrode 190 and the data line 171 may still vary depending on the exposure area divided during the split exposure process, the parasitic capacitance between the pixel electrode 190 and the data line 171 is relatively low. The overall parasitic capacity is almost constant. Therefore, stitch defects can be minimized.

The contact auxiliary members 81a, 81b, and 82 may contact the end portions 129a and 129b of the gate lines 121a and 121b and the end portions 179 of the data lines 171 through the contact holes 181a, 181b and 182. Each is connected. The contact auxiliary members 81a, 81b, and 82 complement adhesiveness between the end portions 129a and 129b of the gate lines 121a and 121b and the respective end portions 179 of the data line 171 and the external device, and It protects you.

An alignment film 11 capable of orienting the liquid crystal layer 3 is coated on the pixel electrode 190, the contact auxiliary members 81a, 81b, 82, and the passivation layer 180.

Next, the common electrode display panel 200 will be described with reference to FIGS. 17 to 18.

A light blocking member 220 called a black matrix for preventing light leakage is formed on an insulating substrate 210 made of transparent glass or the like. The light blocking member 220 has a portion 221 corresponding to the data line 171 and a portion 224 corresponding to the thin film transistor. Alternatively, the light blocking member 220 may have a plurality of openings facing the pixel electrode 190 and having substantially the same shape as the pixel electrode 190. However, the light blocking member 220 may have various shapes to block light leakage near the pixel electrode 190 and the thin film transistors Qa and Qb.

A plurality of color filters 230 is also formed on the substrate 210. The color filter 230 may be mostly located in an area surrounded by the light blocking member 220, and may extend in the vertical direction along the pixel electrode 190. The color filter 230 may display one of primary colors such as red, green, and blue.

An overcoat 250 is formed on the color filter 230 and the light blocking member 220 to prevent the color filter 230 from being exposed and to provide a flat surface.

The common electrode 270 formed of a transparent conductor such as ITO or IZO is formed on the overcoat 250.

The common electrode 270 has a plurality of sets of cutouts 71, 72, 73a, 73b, 74a, and 74b.

One set of cutouts 71, 72, 73a, 73b, 74a, 74b faces a pair of first and second subpixel electrodes 190a, 190b and includes a plurality of lower and upper cutouts 73a, 74a. 73b, 74b and central incisions 71, 72. Each cutout 71, 72, 73a, 73b, 74a, 74b is disposed between adjacent cutouts 91, 92a, 92b of the pixel electrode 190 or between the edge cutouts 93a, 93b and the pixel electrode 190. It is placed between the hypotenuses. In addition, each of the cutouts 71, 72, 73a, 73b, 74a, and 74b includes at least one diagonal line extending in parallel with the lower or lower portions 91, 92a, 92b, 93a, and 93b of the pixel electrode 190. .

The cutout 71 includes a horizontal portion extending along a central horizontal line of the pixel electrode 190, a pair of diagonal portions extending from the horizontal portion to the left side of the pixel electrode 190, and the end of the pixel electrode 190 at the end of the diagonal portion. It includes a pair of vertical portions extending along the left side and overlapping the sides of the pixel electrode 190 and forming an obtuse angle with the oblique portion.

The cutout 72 extends along the vertical portion of the gap 92 near the center of the right side of the pixel electrode 190 and overlaps the right side of the first subpixel electrode 190a with the pixel at both ends of the central longitudinal portion. A pair of oblique portions extending to the left side of the electrode 190 and forming an obtuse angle with the central vertical portion, and extending along the left side of the pixel electrode 190 from the pair of diagonal portions, respectively, to the left of the pixel electrode 190. A longitudinal longitudinal portion that overlaps the sides and forms an obtuse angle with the oblique portion.

The lower and upper cutouts 73a and 73b respectively have an oblique portion extending from the upper left or lower left of the pixel electrode 190 near the right side of the pixel electrode 190 and a left or right side of the pixel electrode 190 at the end of the diagonal portion. It extends along the left side and includes a vertical portion overlapping the left side or the right side of the pixel electrode 190 and forms an obtuse angle with the oblique portion.

The lower and upper cutouts 74a and 74b respectively include diagonal portions extending from the right side of the pixel electrode 190 to the upper side or the lower side of the pixel electrode 190, and at the end of the diagonal portion of the pixel electrode 190. It includes a horizontal portion and a vertical portion extending along the side and overlapping the side of the pixel electrode 190 to form an obtuse angle with the oblique portion.

In addition, the cutouts 71, 72, 73a, 73b, 74a, and 74b of the common electrode 270 control the alignment of liquid crystal molecules in the cutouts 71, 72, 73a, 73b, 74a, and 74b. Is formed.

The number of cutouts 71, 72, 73a, 73b, 74a, 74b may vary depending on design elements, and the light blocking member 220 overlaps the cutouts 71, 72, 73a, 73b, 74a, 74b. Light leakage near the cutouts 71, 72, 73a, 73b, 74a, and 74b may be blocked.

At least one of the cutouts 91-93b and 71-74b may be replaced by a protrusion or a depression, and the shape and arrangement of the cutouts 91-93b and 71-74b may be modified.

An alignment layer 21 is disposed on the common electrode 270 to align the liquid crystal molecules.

Orthogonal polarizers 12 and 22 are provided on the outer surfaces of the display panels 100 and 200, and the transmission axes of the two polarization plates 12 and 22 are orthogonal, and one transmission axis (or absorption axis) is parallel to the horizontal direction. . In the case of a reflective liquid crystal display, one of the two polarizing plates 12 and 22 may be omitted.

The liquid crystal layer 3 has negative dielectric anisotropy and the liquid crystal molecules are aligned such that their major axes are substantially perpendicular to the surfaces of the two display panels 100 and 200 when there is no electric field.

When a common voltage is applied to the common electrode 270 and a data voltage is applied to the pixel electrode 190, an electric field substantially perpendicular to the surfaces of the display panels 100 and 200 is generated. The cutouts 91-93b and 71-74b of the electrodes 190 and 270 distort this electric field to produce a horizontal component perpendicular to the sides of the cutouts 91-93b and 71-74b. Accordingly, the electric field indicates a direction inclined with respect to the direction perpendicular to the surfaces of the display panels 100 and 200. In response to the electric field, the liquid crystal molecules change their directions so that their major axis is perpendicular to the direction of the electric field. In this case, the electric fields near the sides of the cutouts 91-93b and 71-74b and the pixel electrode 190 are formed of the liquid crystal molecules. Since the liquid crystal molecules are formed at an angle without being parallel to the major axis direction, the liquid crystal molecules rotate in a direction in which the movement distance is short on the plane formed by the major axis direction of the liquid crystal molecules and the electric field. Accordingly, one set of cutouts 91-93b and 71-74b and the sides of the pixel electrode 190 may move the portion of the liquid crystal layer 3 positioned on the pixel electrode 190 to a plurality of domains in which the liquid crystal molecules are inclined. The reference viewing angle is thus enlarged.

On the other hand, the difference between the data voltage applied to the subpixels PXa and PXb and the common voltage Vcom is shown as the charging voltage of the liquid crystal capacitors CLCa and CLCb, that is, the pixel voltage. The arrangement of the liquid crystal molecules varies according to the magnitude of the pixel voltage, thereby changing the polarization of light passing through the liquid crystal layer 3. The change in polarization is represented by a change in transmittance of light by a polarizer (not shown) attached to the display panels 100 and 200.

In such a liquid crystal display device, the gamma curves Ta and Tb of the subpixels PXa and PXb representing the change in transmittance with respect to the input grayscale GS1-GSF are different from each other. That is, the pixel voltage applied to the first subpixel Pxa has a gamma curve Ta and the pixel voltage applied to the second subpixel PXb has a gamma curve Tb, and gamma of one pixel PX. The curve becomes the curve T which synthesize | combined these. When determining the pixel voltage of each subpixel PXa, PXb, the composite gamma curve T is close to the reference gamma curve at the front side, for example, the composite gamma curve T at the front side is determined to be the most suitable front side. And the composite gamma curve T at the side to be closest to the reference gamma curve at the front. For example, lower gamma curves at lower gradations can improve visibility.

As such, since the two subpixels PXa and PXb are individually controlled based on independent gamma curves using separate thin film transistors Qa and Qb, the voltages of the two subpixels PXa and PXb are desired. In accordance with this, the luminance value for each gray level in each of the subpixels PXa and PXb is kept to a maximum, thereby improving visibility, increasing aperture ratio, and improving transmittance.

In such a liquid crystal display device, an area ratio of the first subpixel electrode 190a and the second subpixel electrode 190b of the first and second subpixels PXa and PXb is determined, and the first and second obtained accordingly. The first and second subpixels PXa and PXb are designed based on the ratio of the capacities of the liquid crystal capacitors CLCa and CLCb.

That is, the ratio of the capacitances of the first and second storage capacitors CSTa and CSTb and the first and second thin film transistors Qa and Qb are equal to the ratio of the capacitances of the first and second liquid crystal capacitors CLCa and CLCb. The ratio of the capacitances of the first and second parasitic capacitors CGDa and CGDb formed between the gate electrode and the drain electrode of the () is determined.

Assuming that the area of the gate electrodes of the first and second thin film transistors Qa and Qb is constant and the channel length L is fixed at the minimum line width, the gate electrode overlaps with the gate electrode as the width W increases. Since the area of the drain electrode is increased and the width W of the channel decreases, the area of the drain electrode overlapping with the gate electrode decreases, so that the capacitances of the first and second parasitic capacitors CGDa and CGDb are increased. The width W of the channels of the two thin film transistors Qa and Qb may be adjusted.

However, both the width W and the length L of the channel of the thin film transistors Qa and Qb may be adjusted, and the size of the thin film transistor may be determined by adjusting only the length L of the channel.

The pixel voltages of the first and second subpixels PXa and PXb correspond to the liquid crystal capacitors CLCa and CLCb, the storage capacitors CSTa and CSTb, and the parasitic capacitors CGDa and CGDb, as shown in Equation 1 below. It is influenced by the kickback voltage Vk whose magnitude is determined according to the capacity.

Where CLC is the capacitance of the liquid crystal capacitor, CST is the capacitance of the storage capacitor, CGS is the parasitic capacitance of the parasitic capacitor generated between the gate line electrode and the drain electrode of the thin film transistor, and ΔVg is the variation range of the gate signal. )

As a result, the ratio of the capacitances of the first and second sustain capacitors CSTa and CSTb and the first and second parasitic capacitors CGDa and CGDb is equal to the ratio of the capacitances of the first and second liquid crystal capacitors CLCa and CLCb. In the same manner, the magnitudes of kickback voltages generated in the first and second subpixels PXa and PXb are also the same. Furthermore, the capacitance ratios of the capacitances CLCa + CSTa and CLCb + CSTb of the first and second subpixels PXa and PXb are also equal to the capacitance ratios of the liquid crystal capacitors CLCa and CLCb.

In the pixel of FIG. 18, a pixel in which the first subpixel electrode 190a serves as a main pixel and the second subpixel electrode 190b serves as a subpixel is referred to as a D pixel, and the first subpixel electrode 190a is referred to as a subpixel. When the pixel in which the second subpixel electrode 190b serves as the main pixel is referred to as an E pixel, in the pixel arrangement of FIG. 21, the D pixel and the E pixel are repeatedly arranged.

In this case, the main pixel 190a of the D pixel and the main pixel 190b of the E pixel are disposed left and right on the boundary of the data line 171, and the subpixel 190b of the D pixel and the subpixel 190a of the E pixel. Is arranged left and right with respect to the data line 171. Therefore, since the adjacent pixels are pixels to which the same voltage is applied, the left and right luminance differences do not occur, and the left and right visibility do not occur.

In addition, as shown in FIG. 22, by arranging the main pixels 190a of the D pixels so as not to be adjacent to the same A pixel in all the up, down, left, and right directions, the subpixels are not connected in a line in the up and down direction, The pixels and sub-pixels are alternately arranged to have an overall mixing effect. Therefore, it is possible to prevent the occurrence of bands and the like in the vertical direction as a whole, thereby solving the problems of left and right and vertical asymmetry of visibility caused by side light leakage or texture.

The thin film transistor array panel according to the present invention can improve side visibility by displaying an image with two gamma curves on one pixel.

In particular, since the sub pixel electrode to which the image signal is directly transmitted and the sub pixel electrode to which the degraded pixel voltage is transmitted include pixels arranged in left and right symmetry, uniform side visibility can be secured.

In addition, since the main pixels of the pixels are arranged left and right at the boundary of the data line and the subpixels are arranged left and right at the boundary of the data line, adjacent pixels are applied with the same voltage to each other so that the left and right luminance difference does not occur and the left and right visibility The difference does not occur.

Although the preferred embodiments of the present invention have been described in detail above, those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Accordingly, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concept of the present invention as defined in the following claims also fall within the scope of the present invention.

Claims (22)

Board, A gate line formed on the substrate, A data line insulated from and intersecting the gate line; A thin film transistor connected to each of the gate lines and the data lines and having a drain electrode, A capacitive coupling electrode connected to the drain electrode, and A second pixel electrode formed in each pixel surrounded by each of the gate line and the data line and separated from the first pixel electrode and the first pixel electrode connected to the drain electrode and overlapping the capacitive coupling electrode; Including a pixel electrode having, The thin film transistor array panel of which the first pixel electrode and the second pixel electrode of the different pixels have a symmetrical structure. In claim 1, The thin film transistor array panel of claim 1, wherein the first and second pixel electrodes have the same array structure in a row direction, and the first and second pixel electrodes have a left-right symmetrical structure alternately in a column direction. In claim 1, The thin film transistor array panel of claim 1, wherein the first and second pixel electrodes have the same array structure in a row direction, and the first and second pixel electrodes have a left-right symmetrical structure alternately in units of two columns in a column direction. In claim 1, And the pixels having the symmetrical structure of the first and second pixel electrodes are arranged in the same area or number. In claim 1, And the pixel electrode has domain dividing means that is a cutout portion. In claim 5, And the cutouts are connected to each other to form a gap separating the first pixel electrode and the second pixel electrode. In claim 6, And the gap includes an oblique line portion that is 45 ° with respect to the first signal line. Board, A gate line formed on the substrate, A data line insulated from and intersecting the gate line; A thin film transistor connected to each of the gate lines and the data lines and having a drain electrode, A capacitive coupling electrode connected to the drain electrode, and A second pixel electrode formed in each pixel surrounded by each of the gate line and the data line and separated from the first pixel electrode and the first pixel electrode connected to the drain electrode and overlapping the capacitive coupling electrode; Including a pixel electrode having, The first pixel electrodes of the different pixels are adjacent to each other, and the second pixel electrode is adjacent to each other. In claim 8, The thin film transistor array panel of which the different pixels have different positions of the first pixel electrode connected to the drain electrode. In claim 8, The thin film transistor array panel of claim 1, wherein the first pixel electrode of one pixel is adjacent to the second pixel electrode of another pixel adjacent in the vertical direction. In claim 8, And the pixel electrode has domain dividing means that is a cutout portion. In claim 8, And the cutouts are connected to each other to form a gap separating the first pixel electrode and the second pixel electrode. In claim 8, And the gap includes an oblique line portion that is 45 ° with respect to the first signal line. A gate line transferring a scan signal, a data line intersecting the gate line and transmitting an image signal, a thin film transistor connected to the gate line and the data line, the thin film transistor having a drain electrode, and connected to the thin film transistor through the drain electrode A pixel electrode formed in each pixel surrounded by each of the gate lines and the data lines; The pixel electrode includes first and second subpixel electrodes, and the gate line includes a first gate line and a second gate line disposed with respect to the first and second subpixel electrodes, respectively. The transistor includes first and second thin film transistors connecting the first and second subpixel electrodes, the first and second gate lines, and the data line, respectively, and the drain electrode includes the first and second drain electrodes. Including, The first subpixel electrodes of the different pixels are adjacent to each other, and the second subpixel electrode is adjacent to each other. The method of claim 14, The thin film transistor array panel of which different pixels have different positions of the first subpixel electrode. The method of claim 14, The thin film transistor array panel on which the first subpixel electrode of one pixel is adjacent to the second subpixel electrode of another pixel adjacent in the vertical direction. The method of claim 14, And a storage electrode line including first and second storage electrodes overlapping the first and second subpixel electrodes, respectively. The method of claim 14, The first and second subpixel electrodes have a substantially symmetrical shape with respect to a straight line parallel to the gate line. The method of claim 18, And at least one of the first and second subpixel electrodes has a cutout portion. The method of claim 19, The common electrode may have a cutout. The method of claim 20, The thin film transistor array panel of claim 1, wherein at least one of the first and second pixel electrodes and the common electrode have cutouts arranged alternately. The method of claim 14, And a shielding electrode overlapping the data line and positioned on the same layer as the first and second subpixel electrodes.

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