KR20060081749A - Chip scale package having metal plate and stack package, semiconductor package module using thereof - Google Patents

Abstract

The present invention relates to a chip scale package and a laminated package, and a semiconductor module using the same, comprising: a substrate having a through hole formed in a central portion thereof; A semiconductor chip having bonding pads formed on an upper surface of the chip and attached to the substrate such that the bonding pads are exposed through the through hole; Bonding wires electrically connecting the semiconductor chip and the substrate via through holes; A resin molded part formed in the through-hole part to seal the bonding wires and the joining part thereof; And a material attached to the opposite side of the surface on which the semiconductor chip is attached to the substrate, and made of a material containing carbon fiber, having a coefficient of thermal expansion of -5 to 10 ppm / 占 폚 and a Young's Modulus of 80 to 150 Gpa. It characterized in that it comprises a; metal plate. According to this, the thermal expansion coefficient and Young's modulus are attached to the opposite side of the substrate on which the semiconductor chip is attached or the upper part of the resin molded part by attaching a metal plate having a physical property equal to or better than that of the semiconductor chip and having higher thermal conductivity than the substrate or the resin molded part The release characteristics can be improved and the package warpage can be prevented. Therefore, the reliability of the chip scale package, the stacked package and the semiconductor module using the same is improved.

Stacked Packages, Stacked Packages, Modules, Heat Resistant, Heat Spread, Warp, Warpage

Description

Chip scale package having metal plate and stack package, semiconductor package module using thereof

1 is a cross-sectional view showing an example of a laminated package according to the prior art.

2 is a cross-sectional view showing another example of a laminated package according to the prior art.

3 is a partial cross-sectional view showing an example of a semiconductor module according to the prior art.

4 is a partial cross-sectional view showing another example of a semiconductor module according to the prior art.

5 is a temperature distribution photograph showing a simulation result of the semiconductor module according to the prior art.

6 and 7 are cross-sectional views illustrating still another example of a semiconductor module according to the related art.

8 and 9 are schematic cross-sectional views for explaining the deflection of the chip scale package constituting the laminated package according to the prior art.

10 is a cross-sectional view showing a first embodiment of a chip scale package according to the present invention.

11 is a cross-sectional view showing a second embodiment of a chip scale package according to the present invention.                 

12A and 12B are a cross-sectional view and a plan view of a third embodiment of a chip scale package according to the present invention.

13A and 13B are a cross-sectional view and a plan view of a fourth embodiment of a chip scale package according to the present invention.

14 and 15 are cross-sectional views showing a fifth embodiment and a sixth embodiment of a chip scale package according to the present invention.

16 is a cross-sectional view showing a first embodiment of a laminated package according to the present invention.

17 is a cross-sectional view showing a second embodiment of a laminated package according to the present invention.

18 is a cross-sectional view showing a third embodiment of a laminated package according to the present invention.

19 is a sectional view showing a fourth embodiment of a laminated package according to the present invention.

20 is a sectional view showing a fifth embodiment of the laminated package according to the present invention.

21 is a sectional view showing a sixth embodiment of a laminated package according to the present invention.

22 is a sectional view showing a seventh embodiment of a laminated package according to the present invention.

23 is a sectional view showing an eighth embodiment of a laminated package according to the present invention.

24 is a cross-sectional view showing a first embodiment of a semiconductor module according to the present invention.

25 is a sectional view showing a second embodiment of a semiconductor module according to the present invention.

Explanation of symbols on the main parts of the drawings

100; Chip scale package 110; Laminated package

120; Semiconductor module 131; Semiconductor chip

132; Bonding pads 135; Board                 

136; Through-hole 137; Metal plate insertion hole

141; Bonding wire 143; Resin molding

145; Solder balls 151; plate

155; Dam 157; Push pin

161; Module board

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a chip scale package having a metal plate having improved thermal characteristics and package warpage and having improved reliability, and a stacked package and a semiconductor module using the same.

A stack package is a type of package in which a plurality of unit semiconductor chip packages, which have been manufactured through a semiconductor assembly process, are vertically stacked and implemented as a single unit semiconductor chip package. Since the stack package can increase its capacity within the same mounting area as that of the unit semiconductor chip package, there is an advantage in that it is advantageous compared to mounting a plurality of unit semiconductor chip packages.

BACKGROUND ART As a lamination package known recently, a lamination package in which a plurality of chip scale packages (CSPs) with a small mounting area and a thin package thickness are laminated is known. Such stacked packages are used, for example, in the manufacture of high speed and high capacity memory semiconductor modules used in high performance server systems. As a stacked package using a chip scale package, a dual stack package (DSP) in which two chip scale packages are stacked and a quad stack package (QSP) in which four chip scale packages are stacked are typical.

Examples of a stack package according to the related art and a semiconductor module manufactured using the stack packages will be described below.

1 is a cross-sectional view showing an example of a laminated package according to the prior art.

The stack package 910 illustrated in FIG. 1 includes a substrate 935 having a through hole 936 formed in a central portion thereof and a center pad type semiconductor chip 931 having bonding pads 932 formed in a central portion thereof. A dual stack package in which two BGA unit chip scale packages 900 using solder balls 945 as external connection terminals are vertically stacked.

In each unit chip scale package 900 constituting the stack package 910, a semiconductor chip 931 is attached to one surface of a substrate 935 so that a bonding pad 932 is positioned in a through hole 936 and a bonding wire. The semiconductor chip 931 and the substrate 935 are electrically connected by a bonding wire 941, and the bonding wire 941 and its bonding portion are epoxy molding compounds (EMC; Epoxy) in the through hole 936. It is sealed by a resin molding portion 943 formed of a molding resin such as a molding compound, and a plurality of solder balls 945 are formed on the edge of the chip mounting surface of the substrate 935.

The stacked unit chip scale packages 900 are electrically interconnected and physically coupled by attaching solder balls 945 of an upper unit chip scale package to a substrate 935 of a unit chip scale package disposed below.

2 is a cross-sectional view showing another example of a laminated package according to the prior art.

The stacked package 911 illustrated in FIG. 2 is a dual stack package having a structure similar to that of the above-described example, and the substrate 935 and the center pad-type semiconductor chip having the through-hole 936 formed in the center as in the above-described example ( Two unit chip scale packages 901 having 931 are stacked vertically, and unlike the above example, the semiconductor chip 931 is attached to the opposite side of the surface on which the solder balls 945 of the substrate 935 are formed. Structure.

3 is a partial cross-sectional view showing an example of a semiconductor module according to the prior art, and FIG. 4 is a partial cross-sectional view showing another example of a semiconductor module according to the prior art.

The semiconductor module 920 illustrated in FIG. 3 has a stack package 913 in the form of a quad stack package in which four unit chip scale packages 900 having a structure as described in the stack package 910 of FIG. 1 are vertically stacked. A plurality of structures are mounted on the module substrate 961. The solder ball 945 of the unit chip scale package located at the bottom is used as an external connection terminal of the stacked package 913.

In addition, the semiconductor module 921 illustrated in FIG. 4 has a stack package 914 in the form of a quad stack package in which four unit chip scale packages 901 having a structure as described in the stack package 911 of FIG. 2 are stacked. A plurality of structures are mounted on the module substrate 961. Like the semiconductor module 920 illustrated in FIG. 3, the solder ball 945 of the unit chip scale package 901 located at the bottom thereof is used as an external connection terminal of the stack package 914.                         

However, the stack package and the semiconductor module according to the related art as described above should be transferred to the module substrate or discharged to the atmosphere for high temperature heat generated during the operation for normal operation, but each unit chip scale package constituting the stack package There is a problem that heat dissipation does not occur smoothly due to the presence of air gaps between them and between the unit chip scale package and the module substrate or the mounting substrate. This is also true of simulation results.

5 is a temperature distribution photograph showing a simulation result of the semiconductor module according to the prior art.

As a result of simulation by mounting two memory semiconductor modules in a server system, the temperature distribution results as shown in FIG. 5 were obtained, and the contours were densely packed in the air gaps between the unit chip scale packages. This means that a large temperature difference is generated between the gap portion and the surrounding portion, and the heat dissipation effect is reduced. Here, the pitch between slots in which the semiconductor module is mounted was 10.16 mm.

Meanwhile, as the number of unit chip scale packages stacked in the stack package and the semiconductor module according to the prior art increases, the heat dissipation characteristics are worse. For example, quad stack packages are more vulnerable to heat dissipation due to their higher power consumption than dual stack packages. In addition, since the free space between slots on which the semiconductor module is mounted on the system board becomes narrower, the frictional resistance increases, thereby reducing the cooling effect of the system cooling fan. As a result, the deterioration of the product characteristics due to the rise in temperature appears. As such, a semiconductor module structure described below has been proposed as a method for improving the problem of deterioration of heat emission characteristics.

6 and 7 are cross-sectional views illustrating still another example of a semiconductor module according to the related art.

The semiconductor modules 922 and 923 shown in FIGS. 6 and 7 are proposed structures to improve heat dissipation characteristics, respectively. In the case of the semiconductor module 922 illustrated in FIG. 6, the unit located at the top of the stack package 915 is shown. The heat sink 951 is attached to the semiconductor chip 931 of the chip scale package 901. In the case of the semiconductor module 923 illustrated in FIG. 7, the unit chip scale package located at the top of the stack package 916 is shown. The heat sink 952 is attached to the substrate 901 via a dummy ball 946.

As described above, a laminated package in which a heat sink is locally attached to a semiconductor chip of a chip scale package located at the top or a heat sink is attached to a substrate through a dummy ball may be further heat discharged through the heat sink. Has heat release properties. However, in the case of such a laminated package, warpage of each unit chip scale package, which is not in direct contact with the heat sink, is severe, requiring structural supplementation in terms of package reliability.

8 and 9 are schematic cross-sectional views for explaining the deflection of the chip scale package constituting the laminated package according to the prior art.

8 and 9, the unit chip scale packages 900 and 901 may thermally expand the semiconductor chip 931, the substrate 935, and the resin molded part 943 when the temperature increases. Warpage occurs due to a difference in coefficient of thermal expansion (CTE). When the semiconductor chip 931 is attached to the solder ball forming surface of the substrate 935 as shown in FIG. 8, warpage occurs as shown in the package edge portion in the direction opposite to the surface on which the semiconductor chip 931 is attached. As shown in FIG. 9, when the semiconductor chip 931 is attached to a surface opposite to the solder ball forming surface of the substrate 935, the package edge portion is warped in the solder ball forming surface direction as shown in FIG.

In addition, semiconductor modules have been introduced to solve heat dissipation characteristics and chip protection problems by attaching an integrated heat spreader. However, the increase in the thickness of the semiconductor module does not meet customer requirements for thickness. Can be. In particular, since the pitch between the slots in which the memory semiconductor modules of the server system are mounted is gradually reduced, when a plurality of memory semiconductor modules are mounted in the slots, spaces between the semiconductor modules are not afforded to reduce heat dissipation efficiency. do. In addition, there is a problem in that the temperature of the memory semiconductor module is increased because the air flow rate effect by the system cooling fan is lessened, thereby degrading the characteristics of the product.

Accordingly, an object of the present invention is to provide a chip scale package, a laminated package, and a semiconductor module capable of efficiently dissipating heat generated in a package while preventing package warpage caused by heat generated in an operation process.

Chip scale package according to the present invention for achieving the above object is a substrate with a through hole formed in the center; A semiconductor chip having bonding pads formed on an upper surface of the chip and attached to the substrate such that the bonding pads are exposed through the through hole; Bonding wires electrically connecting the semiconductor chip and the substrate via through holes; A resin molded part formed in the through-hole part to seal the bonding wires and the joining part thereof; And a material attached to the opposite side of the surface on which the semiconductor chip is attached to the substrate, and made of a material containing carbon fiber, having a coefficient of thermal expansion of -5 to 10 ppm / 占 폚 and a Young's Modulus of 80 to 150 Gpa. It characterized in that it comprises a; metal plate.

In the chip scale package according to the present invention, the metal plate is preferably attached to the semiconductor chip or the resin molding. The metal plate may be in the form of a cover in which a cavity is formed. Alternatively, the metal plate may be in the form of a flat plate, in which case a dam is formed at a predetermined height on the substrate and the metal plate is attached to the dam. In addition, the metal plate is in the form of a cavity, a portion of the side wall may be through the substrate. Alternatively, the metal plate may have a flat plate shape, and a fixing pin may be formed through the substrate, and the metal plate may be attached to the fixing pin.

In addition, the laminated package according to the present invention for achieving the above object is a substrate with a through hole formed in the center portion, the bonding pads are formed on the chip upper surface and the semiconductor chip attached to the substrate so that the bonding pads are exposed in the through holes, and through A plurality of unit chips including bonding wires electrically connecting the semiconductor chip and the substrate via holes, a resin molded portion formed in the through-hole portion to seal the bonding wires and the bonding portion thereof, and solder balls formed on the substrate; Have scale packages; The solder balls of the plurality of unit chip scale packages are attached to the substrate of the chip scale package located at the top of the unit chip scale package, and are electrically stacked and physically coupled to each other, and at least one of the unit chip scale packages is stacked. It is made of a material containing carbon fiber in the thermal expansion coefficient of -5 ~ 10ppm / ℃ and Young's Modulus (Young's Modulus) is characterized in that the metal plate is attached to 80 ~ 150Gpa.

In the stacked package according to the present invention, it is preferable that the unit chip scale package located at the top has a semiconductor chip attached to the opposite side of the solder ball forming surface and a protective plate in the form of a flat plate attached to the chip of the semiconductor.

In addition, the semiconductor module according to the present invention for achieving the above object is characterized in that a plurality of laminated packages according to the present invention as described above is mounted on the module substrate.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the accompanying drawings, some of the components are somewhat exaggerated, schematically illustrated or omitted to facilitate a clear understanding of the drawings, and the actual size of each component is not entirely reflected.

10 is a cross-sectional view showing a first embodiment of a chip scale package according to the present invention.

The chip scale package 100 according to the present invention illustrated in FIG. 10 includes a substrate 135 having a through hole 136 formed in a central portion thereof, and a semiconductor pad 131 having a center pad type. A BGA type using 145 is a structure having a metal plate 151 attached to a substrate 135.                     

The semiconductor chip 131 is attached to one surface of the substrate 135 such that the bonding pads 132 are positioned in the through hole 136. The semiconductor chip 131 and the substrate 135 are electrically connected to each other by a bonding wire 141 via the through hole 136. The bonding wire 141 and its joined portion are sealed by the resin molded portion 143 formed in the through hole 136 portion. A plurality of solder balls 145 are formed at the edge of the chip mounting surface of the substrate 135.

The metal plate 151 is attached to a surface opposite to the surface on which the semiconductor chip 131 is mounted on the substrate 135. The metal plate 151 is a form in which the cavity 152 is formed, and the inner peripheral surface is attached to the resin molding part 143.

Here, the metal plate 151 is made of a material containing carbon fiber in order to have a property of being excellent in thermal conductivity and having a property that can be protected from physical impact from an external use environment while having a small difference in thermal expansion coefficient from the semiconductor chip 131. It has a coefficient of thermal expansion of less than 10 ppm and a Young's Modulus is made of the same or larger material as a semiconductor chip. Preferably the coefficient of thermal expansion is -5 ~ 10ppm / ℃ Young's Modulus (Young's Modulus) to be 80 ~ 150Gpa.

As can be seen in Table 1 below, since carbon has a small difference in thermal expansion coefficient from a semiconductor chip and a Young's modulus has excellent property values, the metal plate 151 containing carbon fiber has a small difference in thermal expansion coefficient from the semiconductor chip 131. During package assembly and reliability test, warpage due to temperature change can be suppressed and thermal conductivity can be improved simultaneously to improve package heat dissipation characteristics.

Copper aluminum magnesium Stainless steel silicon Carbon plate Modulus (Gpa) 110 70 44 171 ~ 200 112.4 231-500 CTE (μm / mC) 16.4 24 26.1 10-18.5 2.49 -1.4 K (W / mK) 385 210 159 10-20 124 185-600

11 is a cross-sectional view showing a second embodiment of a chip scale package according to the present invention.

The chip scale package 101 according to the present invention illustrated in FIG. 11 has a structure similar to that of the first embodiment described above and has a flat metal plate 153 unlike the first embodiment. A dam 155 is formed in the substrate 135 such that the metal plate 153 is positioned at a position higher than the resin molded part 143. An adhesive 156 is applied on the dam 155 to attach the metal plate 153, and the metal plate 153 is also attached to the resin molding 143. Here, the metal plate 153 also has the same physical properties as the metal plate 152 of the chip scale package 100 according to the first embodiment.

12A and 12B are a cross-sectional view and a plan view showing a third embodiment of a chip scale package according to the present invention, and FIGS. 13A and 13B are a cross-sectional view and a plan view showing a fourth embodiment of a chip scale package according to the present invention.

The chip scale package according to the present invention illustrated in FIGS. 12A and 12B has a structure similar to that of the first embodiment described above, and unlike the first embodiment, the metal plate 157 is coupled through the substrate 135. to be. The metal plate insertion hole 137 through which the side wall 157a of the metal plate 157 is partially penetrated is formed in the predetermined position of the board | substrate 135, and the side wall 157a of the metal plate 157 is formed in the metal plate insertion hole 137. It is combined in the inserted form. The side wall 157a of the metal plate 157 is in close contact with the side surface of the semiconductor chip 131. Since the metal plate 157 has a volume increase in the form formed through the substrate 135, the heat is released well. In addition, since the metal plate 157 is in contact with not only the resin forming portion 143 but also the semiconductor chip 131, heat dissipation is smoothly performed and generation of warpage is suppressed.

The chip scale package 103 according to the present invention illustrated in FIGS. 13A and 13B is similar to the chip scale package 102 of the third embodiment described above. Unlike the third embodiment, the chip scale package 103 has a through hole in the substrate 135. A plurality of fixing pin insertion holes 138 are formed at both periphery of 136, and a fixing pin 158a is inserted into the fixing pin insertion hole 138, and the upper portion of the fixing pin 158a is provided. The plate-shaped metal plate 158 is attached.

As the fixing pin 158a is inserted into the substrate 135 and the metal plate 158 of the flat plate form is attached to the fixing pin 158a, as shown in the chip scale package 102 of the third embodiment, smooth heat dissipation is achieved. Can be made and the occurrence of warpage is suppressed. Here, the material of the fixing pin 158a, the number and size of the fixing pin 158a and the fixing pin insertion hole 138 may be changed as necessary.

14 and 15 are cross-sectional views showing a fifth embodiment and a sixth embodiment of a chip scale package according to the present invention.

In the chip scale packages 104 and 105 illustrated in FIGS. 14 and 15, unlike the above-described embodiments, the semiconductor chip 131 is attached to the upper surface of the substrate 135, and the metal plates 151 and 157 are disposed on opposite sides of the chip mounting surface. This is an example of the structure in which the protective plates 171 and 172 of the metal material which are excellent in thermal conductivity are attached on the back surface of the semiconductor chip 131. As shown in FIG. The chip scale package 104 illustrated in FIG. 14 has a shape in which a metal plate 151 having a cavity 152 is attached to a substrate 135, and the chip scale package 105 illustrated in FIG. 15 is formed of a metal plate ( The 157 penetrates the substrate 135, and the protective plate 172 is attached to the metal plate 157 as well as the semiconductor chip 131. As a result, heat dissipation is smoother, and warpage is suppressed, and a semiconductor chip can be protected from a physical external environment.

As in the above-described embodiments, the chip scale package according to the present invention is a metal plate in which the semiconductor chip and the resin encapsulation are formed of a metal plate having a coefficient of thermal expansion and Young's modulus equal to or better than that of the semiconductor chip and having a higher thermal conductivity than the substrate or the resin molded part. By adhering to the part and the substrate, the amount of heat dissipation is increased due to the increase in the volume of the metal plate, and heat dissipation can be smoothly achieved, and the occurrence of package warpage is greatly reduced because the coefficient of thermal expansion is similar to that of the semiconductor chip and the Young's modulus is excellent. Moreover, the occurrence of warpage is further prevented by the metal plate providing physical support for warpage. Such a chip scale package may be used to manufacture a multilayer package and a semiconductor module having improved reliability, thereby improving reliability of the multilayer package and a semiconductor module.

16 is a cross-sectional view showing a first embodiment of a laminated package according to the present invention.

The stack package 110 illustrated in FIG. 16 has a structure in which two chip scale packages 100 according to the first embodiment of the present invention are stacked vertically. The chip scale packages 100 are attached to the substrate 135 of the chip scale package 100 at the bottom of the solder ball 145 of the chip scale package is located at the top of the electrical connection and physical coupling is made. Since each chip scale package 100 has a structure in which heat dissipation characteristics are improved and package warpage is suppressed, the laminated package 110 has overall improved heat dissipation characteristics and curvature generation is suppressed, thereby improving reliability.

17 is a cross-sectional view showing a second embodiment of a laminated package according to the present invention.

Unlike the stack package 110 of FIG. 17, the stack package 111 illustrated in FIG. 17 has a semiconductor chip 131 attached to a surface opposite to a surface on which the solder balls 145 are formed. The protection plate 173 made of a metal having excellent thermal conductivity is attached to the semiconductor chip 131 of the chip scale package 101 located at the top thereof. In addition to the metal plate 153, the heat dissipation is more smoothly performed by the protective plate 173, thereby improving reliability.

18 is a cross-sectional view showing a third embodiment of a laminated package according to the present invention.

The stack package 112 illustrated in FIG. 18 is an example of a stack package in which two chip scale packages 102 of the third embodiment according to the present invention are stacked vertically. Each unit chip scale package 102 penetrates the substrate 135 to increase the heat dissipation volume by the combined metal plate 157 and to contact the semiconductor chip 131 so that heat dissipation is more smoothly. Is improved.

19 is a sectional view showing a fourth embodiment of a laminated package according to the present invention.

The stacked package 113 illustrated in FIG. 19 is an example of a stacked package in which a plurality of unit chip scale packages 105 similar to the sixth embodiment are stacked. Unlike the stack package 112 structure of FIG. 18, each unit chip scale package 105 has a semiconductor chip 131 attached to a surface opposite to a surface on which a solder ball 145 is formed, and the chip scale package disposed at the top thereof. The protective plate 173 is attached to the semiconductor chip 131 and the metal plate 157 of 105. This laminated package is also improved in reliability as heat dissipation is performed not only by the metal plate 157 but also by the protective plate 172 as in the third embodiment.

20 is a sectional view showing a fifth embodiment of the laminated package according to the present invention.

In the multilayer package 114 according to the present invention illustrated in FIG. 20, each of the unit chip scale packages 107 having a shape similar to that of the unit chip scale package 104 of the fifth embodiment may include a plurality of rows of solder balls 145. ). This is an example that can be applied when the number of the input / output pins is large and the number of solder balls 145 is increased.

21 is a sectional view showing a sixth embodiment of a laminated package according to the present invention.

In the stack package 115 according to the present invention illustrated in FIG. 21, the chip scale package 108a located at the top has a row of solder balls 145a and the solder ball 145b in three rows at the bottom of the chip scale package 108b. It has a structure. The stack package 115 is an example in which a plurality of chip scale packages 108a and 108b having different solder balls 145a and 145b arrangement structures and shapes (diameter, height layout, position), and the like are stacked. Here, the metal plate 151 is formed on the unit chip scale package 108a located above the unit chip scale packages 108a and 108b.

22 is a sectional view showing a seventh embodiment of a laminated package according to the present invention.

In the multilayer package 200 illustrated in FIG. 22, a unit chip scale package 200 having a semiconductor chip 231 mounted by flip chip bonding on a substrate 235 on which a through hole is not formed. Two of them are stacked. The semiconductor chip 231 is attached to the surface on which the solder balls 245 are formed, and the metal plate 251 in the form of a plate is attached to the surface opposite to the chip mounting surface.

23 is a sectional view showing an eighth embodiment of a laminated package according to the present invention.

The stacked package 310 illustrated in FIG. 23 has a structure in which different types of chip scale packages 301 and 302 are vertically stacked, and the chip scale package 301 located on the top thereof has three semiconductor chips on the substrate 335. The stacks 311a, 311b and 311c are stacked chip packages. The chip scale package 302 located below the semiconductor chip 311d is mounted by flip chip bonding on a surface where the solder ball 345 of the substrate 335 on which the through hole is not formed is formed.

The stacked package 310 is mounted on a substrate 335 of a chip scale package 302 located below a chip scale package 301 located at an upper portion thereof. 335 is a structure that is attached to the separated plate-shaped metal plate 351. The stacked package 310 is also an example of a system in package mixed with a logic and a multi-chip package.

24 is a cross-sectional view showing a first embodiment of a semiconductor module according to the present invention, and FIG. 25 is a cross-sectional view showing a second embodiment of a semiconductor module according to the present invention.

The semiconductor module 120 illustrated in FIG. 24 is an example of a structure in which a plurality of the stack packages 110 according to the first embodiment are mounted on both surfaces of the module substrate 161 in the horizontal direction. In addition, the semiconductor module 121 according to the present invention illustrated in FIG. 25 has a structure in which a plurality of laminated packages 107 of the above-described fifth embodiment are mounted on both sides of the module substrate in the horizontal direction, respectively.

Meanwhile, the chip scale package according to the present invention, the stack package and the semiconductor module using the same are not limited to the above-described embodiments and may be variously modified within a range not departing from the technical spirit of the present invention.

According to the chip scale package having the metal plate according to the present invention, the laminated package and the semiconductor module using the same, the coefficient of thermal expansion and Young's modulus on the opposite side of the substrate on which the semiconductor chip is attached or on the resin molded part is equal to the semiconductor chip By attaching a metal plate having superior physical conductivity and physical properties higher than that of the substrate or the resin molded part, heat dissipation characteristics can be improved and package warping can be prevented. Therefore, the reliability of the chip scale package, the stacked package and the semiconductor module using the same is improved.

Claims (10)

A substrate having a through hole formed in the center portion thereof; A semiconductor chip having bonding pads formed on an upper surface of the chip and attached to the substrate to expose the bonding pads to the through holes; Bonding wires electrically connecting the semiconductor chip and the substrate via the through hole; A resin molding part sealing the bonding wires and the bonding portion thereof and formed in the through hole portion; And It is attached to the opposite side of the surface on which the semiconductor chip is attached to the substrate and made of a material containing carbon fiber, the coefficient of thermal expansion is -5 ~ 10ppm / ℃ and Young's Modulus is 80 ~ 150Gpa plate; Chip scale package comprising a. The chip scale package of claim 1, wherein the metal plate is attached to a semiconductor chip. The chip scale package of claim 1, wherein the metal plate is attached to the resin molding part. The chip scale package of claim 1, wherein the metal plate is in the form of a cover in which a cavity is formed. The chip scale package of claim 1, wherein the metal plate has a flat plate shape, a dam is formed at a predetermined height on the substrate, and the metal plate is attached to the dam. The chip scale package of claim 1, wherein the metal plate is formed with a cavity, and a portion of the sidewall penetrates through the substrate. The chip scale package of claim 1, wherein the metal plate has a flat plate shape, and a fixing pin is formed through the substrate, and the metal plate is attached to the fixing pin. A substrate having a through hole formed in a central portion thereof, a bonding pad formed on an upper surface of the chip, and a semiconductor chip attached to the substrate to expose the bonding pads to the through hole, and electrically connecting the semiconductor chip and the substrate via the through hole. Bonding wires connected to each other, a plurality of unit chip scale packages including a bonding portion sealing the bonding wires and a bonding portion thereof, a resin molded portion formed in the through hole portion, and a solder ball formed on the substrate; A plurality of unit chip scale packages are stacked by solder balls of the upper chip scale package attached to the substrate of the lower chip scale package to be electrically connected and physically coupled to each other, and at least one of the unit chip scale packages includes carbon fiber. A laminated package comprising a metal plate having a thermal expansion coefficient of -5 to 10 ppm / ℃ and a Young's Modulus of 80 to 150 Gpa. The multilayer package according to claim 8, wherein the unit chip scale package disposed at the top has a semiconductor chip attached to an opposite surface of the solder ball forming surface and a protective plate in the form of a plate is attached to the chip of the semiconductor. . A plurality of laminated packages according to claim 8 are mounted on a module substrate.

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