KR20060079159A - Light emitting diode with vertical electrode and manufacturing method of the same - Google Patents

Abstract

A sapphire base substrate having a via hole formed to penetrate up and down, a plurality of nitride based semiconductor layers formed on the sapphire base substrate, a first electrode pad formed on an exposed surface of the nitride based semiconductor layer exposed through a via hole of the sapphire base substrate, A vertical electrode light emitting diode including an ohmic electrode formed on a nitride based semiconductor layer, a seed metal formed on the ohmic electrode, and a receptor metal film formed on the seed metal is provided.

Light emitting diode, vertical electrode structure, oxide film, sapphire, via hole, nitride semiconductor, seed metal

Description

Light emitting diode with vertical electrode and manufacturing method of the same

1A to 1E illustrate an intermediate manufacturing process of a light emitting diode having a vertical electrode structure according to a first embodiment of the present invention.

2 is a graph showing the etching rates of sapphire and GaN by ICP / RIE dry etching.

3 is a graph showing an etching rate when wet etching sapphire and GaN with a mixed solution of sulfuric acid and phosphoric acid.

Figure 4 is a graph showing the etching rate of sapphire and GaN according to the temperature of the sulfuric acid and phosphoric acid mixed solution.

5 is a sapphire substrate surface photograph after wet etching the sapphire substrate after forming a specific pattern on the sapphire substrate by a wet etching method.

6 is a surface photograph of a buffer layer after removing a sapphire substrate by a wet etching method.

7 is a cross-sectional view and a plan view of a light emitting diode having a vertical electrode structure according to a second embodiment of the present invention.

8 is a cross-sectional view and a plan view of a light emitting diode having a vertical electrode structure according to a third embodiment of the present invention.

9 is a cross-sectional view and a plan view of a light emitting diode having a vertical electrode structure according to a fourth embodiment of the present invention.

10 is a cross-sectional view and a plan view of a light emitting diode having a vertical electrode structure according to a fifth embodiment of the present invention.

11A to 11F illustrate an intermediate manufacturing process of a light emitting diode having a vertical electrode structure according to a sixth embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

* 11 sapphire substrate 12 buffer layer

13 first ohmic contact layer 14 first cladding layer

15 Light emitting layer 16 Second cladding layer

17 Second ohmic contact layer 18 Ohmic electrode

19 oxide 20 seed metal

21 Receptor Metal Film 22 SiO ₂ Etch Mask

23 Via hole 24 First electrode pad

25 Dicing or Wall Improvement 26 Transparent or Light Transmissive Electrode

27 Mesh electrode 191 Second via hole

The present invention relates to a light emitting diode having a vertical electrode structure and a method of manufacturing the same.

A light emitting diode is a kind of photodiode that generates light when a constant current of a constant magnitude flows. The light emitting diode is a light emitting diode that emits red or green light by using a pin bonded structure of compound semiconductors such as indium phosphorus (InP), gallium arsenide (GaAs), and gallium phosphorus (GaP), and also emits blue and ultraviolet light. Light emitting diodes have been developed and widely used in display devices, light source devices, and environmental application devices. Recently, a color conversion light emitting diode that emits white light using three chips of red, green, and blue or a phosphor has been developed, and its application range has been widened as a lighting device.

In the case of using a nitride-based light emitting material as a thin film structure in such a light emitting diode, sapphire similar in lattice constant and crystal structure is used as a base substrate to reduce the occurrence of crystal defects during epitaxial growth.

However, since sapphire is an insulator, both the first electrode and the second electrode had to be formed on the growth surface of the epi layer. Thus, if both electrodes are formed on the same surface, the area of electrodes required for wire bonding must be secured. Therefore, the chip area of the light emitting diode is also over a certain size, which hinders the improvement of chip production per wafer, and uses an insulator as a substrate. Therefore, it is difficult to discharge static electricity flowing from the outside, which causes device defects due to static electricity. This leads to several limitations in the packaging process, such as lowering device reliability and incorporating zener diodes.

In addition, since sapphire has low thermal conductivity, it is difficult to dissipate heat generated while driving a light emitting diode to the outside, and thus there is a limit to applying a large current for high power.

In particular, since the light emitting diodes are manufactured by wet or dry etching the sapphire substrate, the nitride semiconductor layer and the electrode should not be damaged during sapphire etching and the chip performance should not be affected. Dicing equipment commonly used to separate semiconductor devices uses diamond blades. Cutting a sapphire substrate is rather cumbersome and reduces productivity.

Therefore, research for developing a light emitting diode structure having a vertical electrode structure is continuing in the art.

An object of the present invention is to provide a light emitting diode having a vertical electrode structure using a sapphire substrate etching technique and a method of manufacturing the same, and to simplify the method of manufacturing the same.

It is an object of the present invention to provide a light emitting diode having a vertical electrode structure having a new acceptor substrate and an internal connection structure, particularly in the case of using a light emitting diode in the case of using a receptor substrate to advantageously perform a multi-step process. .

In order to achieve the above object, the present invention proposes the following light emitting diode.

The present invention provides a sapphire base substrate having a via hole formed to penetrate up and down; A plurality of nitride-based semiconductor layers formed on the sapphire base substrate; A first electrode pad formed on the nitride-based semiconductor layer exposed surface exposed through the via hole of the sapphire base substrate; An ohmic electrode formed on the nitride based semiconductor layer; A seed metal formed on the ohmic electrode; And a receptor metal layer formed by plating on the seed metal.

Preferably, a light transmissive electrode or a transparent electrode is formed over the sapphire base substrate and the via hole, and the first electrode pad is formed at a position outside the via hole on the light transmissive electrode or the transparent electrode. More preferably, the light transmissive electrode includes at least one of Ni, Au, Pt, Ti, and Al. Also preferably, the transparent electrode is formed of ZnO or ITO (Indium Tin Oxide).

Also preferably, the sapphire base substrate is etched and completely removed, and the first electrode pad is formed on the nitride based semiconductor layer. Also preferably, a light transmissive electrode or a transparent electrode is formed on the nitride based semiconductor layer, and the first electrode pad is formed on the light transmissive electrode or the transparent electrode. More preferably, the light transmissive electrode includes at least one of Ni, Au, Pt, Ti, and Al. Also preferably, the transparent electrode is formed of ZnO or ITO (Indium Tin Oxide).

Also preferably, a mesh type electrode is formed on the nitride based semiconductor layer, and the first electrode pad is formed on the mesh type electrode. More preferably, the mesh type electrode is formed to include at least one of Ni, Au, Pt, Ti, Al.

Also preferably, an oxide film including a second via hole is formed on the ohmic electrode, and a seed metal is formed on the oxide film to be electrically connected to the ohmic electrode through the second via hole.

Also preferably, the ohmic electrode includes at least one of Pt, Ni, Au, Rh, and Pd. More preferably, the ohmic electrode is formed of Pt. Also preferably, the seed metal is formed of at least one of Au, W, Pt, Cu, and Ni. Also preferably, the receptor metal film is plated with at least one of Au, Cu, CuW, Mo, W, and Pt.

Also preferably, the nitride based semiconductor layer is composed of In _x (Al _y Ga _{1 -y} ) N nitride based semiconductor, and x and y have values of 1≥x≥0, 1≥y≥0, and x + y> 0. It is characterized by having. Also preferably, the first electrode includes at least one of Al, Pt, Ta, Cr, Ni, Au, and Ti.

The vertical electrode light emitting diode of the structure comprises the steps of forming a plurality of nitride-based semiconductor layer on the sapphire base substrate; Forming an ohmic electrode on the nitride based semiconductor layer; Forming a seed metal on the ohmic electrode; Plating and forming a receptor metal film on the seed metal; Processing the sapphire base substrate to a predetermined thickness, and then forming an etching mask on the sapphire base substrate; Partially etching the etching mask to expose the sapphire base substrate, and then etching the exposed sapphire base substrate to etch at least a portion of the nitride based semiconductor layer; And forming a first electrode pad on the exposed nitride based semiconductor layer.

Preferably, after the sapphire base substrate is etched, the etch mask is further removed by etching.

The method may further include forming a light transmissive electrode on the sapphire base substrate and the exposed nitride semiconductor layer after all the etching masks are removed by etching. The first electrode pad is formed on the light transmissive electrode. do. At this time, the step of forming the light transmissive electrode is any one of Ni / Au / Ni, Al, Ti / Al by depositing any one structure in a furnace containing oxygen or nitrogen at a temperature of 400 ℃ to 700 ℃ 1 minute to 5 minutes It is more preferable to heat-process for minutes.

The method may further include forming a transparent electrode on the sapphire base substrate and the exposed nitride-based semiconductor layer after all the etching masks are removed by etching, and the first electrode pad is formed on the transparent electrode.

Also preferably, the etching step of the sapphire base substrate is characterized in that to completely remove the sapphire base substrate by etching. In this case, the method may further include forming a light transmissive electrode on the exposed nitride semiconductor layer, and the first electrode pad may be formed on the light transmissive electrode. More preferably, the light transmissive electrode is deposited by any one structure of Ni / Au / Ni, Al, Ti / Al, and in a furnace containing oxygen or nitrogen at a temperature of 400 ° C. to 700 ° C. for 1 minute to 5 minutes. It is formed by heat treatment.

The method may further include forming a transparent electrode on the exposed nitride based semiconductor layer after etching and removing the sapphire base substrate, wherein the first electrode pad is formed on the transparent electrode.

The method may further include forming a mesh electrode on the exposed nitride-based semiconductor layer after etching and removing the sapphire base substrate, wherein the first electrode pad is formed on the mesh electrode. More preferably, the mesh electrode includes at least one of Ni, Au, Pt, Ti, and Al, and is 1 to 5 minutes at a temperature of 400 ° C to 700 ° C in an furnace containing oxygen or nitrogen. It is formed by heat treatment.

The method may further include forming an oxide film on the ohmic electrode after forming the ohmic electrode, and etching the oxide film to form a second via hole to expose the ohmic electrode, and forming a seed metal on the oxide film. It is characterized by.

Also preferably, the ohmic electrode is formed by depositing at least one of Pt, Ni, Au, Rh, and Pd and heat-treating at a temperature of 300 ° C to 700 ° C for 1 minute to 5 minutes in an atmosphere containing nitrogen or oxygen. Also preferably, the receptor metal film is formed by plating at least one of Au, Cu, CuW, Mo, W, and Pt by electroplating or electroless plating. Also preferably, the sapphire base substrate may be etched by an etching solution mixed with sulfuric acid (H ₂ SO ₄ ) and phosphoric acid (H ₃ PO ₄ ) at a temperature of 200 ° C. to 400 ° C. More preferably, in the etching step of the sapphire base substrate, at least a part of the nitride based semiconductor layer is etched and simultaneously formed cleavage lines for separating the base substrate by individual chips through etching. Also preferably, the first electrode pad is formed by heat-treating at least one of Al, Pt, Ta, Cr, Ni, Au, and Ti at a temperature of 300 ° C. to 600 ° C. for 2 minutes in a furnace in a nitrogen atmosphere.

Hereinafter, a vertical light emitting diode according to the present invention and a manufacturing method thereof will be described in detail.

<Formation of Nitride-Based Semiconductor Layer>

In _x (Ga _y Al _{1 -y} ) N nitride semiconductor layers are grown on a sapphire base substrate (Sapphire, Al ₂ O ₃ ) with a thickness of about 430 μm using metal organic chemical vapor deposition (MOCVD). . The composition ratio of the nitride semiconductor is 1≥x≥0, 1≥y≥0, and x + y> 0. The nitride-based semiconductor layer may include metal organic chemical vapor deposition, liquid phase epitaxy, hydrogen vapor phase epitaxy, molecular beam epitaxy, and MOVPE. It is also possible to grow with (metal organic vapor phase epitaxy).

The growing nitride semiconductor layer may be grown in a single layer or in multiple layers according to the type of device to be manufactured, and any one or a plurality of elements of Si, Mg, and Zn groups may be added as impurities to have a conductive property. Si may be added to form an n-type nitride semiconductor layer, and Mg may be added to form a p-type nitride semiconductor layer. The doping concentration depends on the type of device to be manufactured and may be doped at about 10 ¹⁵ / cm ³ to 10 ²¹ / cm ³ .

Therefore, depending on the doping concentration, the nitride semiconductor is classified into a high resistor or a conductive material, and in the case of a high resistor, the specific resistance is 10 ⁰ Ωcm As mentioned above, in the case of electroconductivity, it is preferable that it becomes 10 <^{-1> (} ohm) cm or less.

Buffer layer (undo layer + undoped In _x (Al _y Ga _{1 -y} ) N) (12), n-type conductive contact layer (13), n-type cladding on sapphire substrate (11) to fabricate vertical electrode type light emitting diode The In _x (Al _y Ga _1-y ) N nitride semiconductor layers of the layer 14, the light emitting layer 15, the p-type cladding layer 16, and the p-type conductive contact layer 17 were grown. That is, each layer 12, 13, 14, 15, 16, 17 can be formed of AlGaN, InGaN, AlGaInN or the like. In particular, the light-emitting layer _{(15) In x (Al y} Ga 1-y) N in the barrier layer and the _{In x (Al y Ga 1 -y} ) may have a single quantum well structure or a multiple quantum well structure comprising a well layer of N By controlling the composition ratio of In, Ga, and Al, it is possible to freely fabricate from a long wavelength having an InN (˜2.2 eV) band gap to a short wavelength light emitting diode having an AlN (˜6.4 eV) band gap.

Although not illustrated in the drawings, a light emitting diode including a buffer layer may be grown after forming a fine cluster of any one of SiO ₂ and SiN groups having a thickness of about 10 μs or a combination thereof on a sapphire base substrate. The SiN or SiO ₂ microstructure minimizes the stress between the sapphire base substrate and the nitride semiconductor layer, thereby improving the nitride semiconductor film quality and may be used as a stop layer for wet etching when removing the sapphire substrate using wet etching. The wafer coverage of the SiN or SiO ₂ microstructure covering the sapphire base substrate should be 90% or less. This is because when the SiN or SiO ₂ microstructure covers the entire sapphire substrate, the nitride semiconductor is not exposed because the sapphire on which the nitride is to be grown is not exposed, and the nitride semiconductor is not grown on the SiN or SiO _2. to be.

Hereinafter, exemplary embodiments of a light emitting diode having a vertical electrode structure according to the present invention will be described in detail with reference to the accompanying drawings.

<First Embodiment>

1A to 1E illustrate an intermediate manufacturing process of a light emitting diode having a vertical electrode structure according to a first embodiment of the present invention. As shown in FIG. 1A, when the nitride-based semiconductor layers 12, 13, 14, 15, 16, and 17 are grown on the sapphire substrate 11, the ohmic electrode 18 and the seed are disposed on the second ohmic contact layer 17. The metal 20 is deposited. The ohmic electrode 18 is deposited at any one of Pt, Ni, Au, Rh, Pd, and Ti or an alloy of these metals, and is heated at a temperature of 300 ° C to 700 ° C in a furnace containing nitrogen or oxygen. Heat treatment for minutes to 5 minutes.

In particular, the micro pipe formed due to the metal cluster formed during the metal deposition provides a passage through which the etching solution can flow, thereby allowing the etching solution to penetrate into the nitride semiconductor layer, thereby forming the second ohmic contact layer 17. In order to protect the second ohmic contact layer 17, Pt is preferably formed as an ohmic electrode because Pt is not damaged by the etching solution.

On the sapphire substrate 11, the buffer layer 12 and the n-type and p-type conductive contact layers 13 and 17, the n-type and p-type cladding layers 14 and 16, and the light emitting layer 15 are In _x (Al _y Ga). _{1- y} ) N nitride semiconductor, and x and y have values of 1 ≧ x ≧ 0, 1 ≧ y ≧ 0, and x + y> 0. The n-type conductive contact layer 13 is doped with a Si impurity of 10 ¹⁸ or more to have a resistivity of ¹ × 10 ⁻¹ Ωcm or less, and the p-type contact layer 17 is doped with a Mg impurity of 10 ¹⁹ or more to 1 × 10 ^{−. It} has a specific resistance of ¹ Ωcm or less.

The total thickness of the nitride-based semiconductor thin film preferably has a thickness of 1 μm to 100 μm in order to minimize the cracking of the nitride semiconductor due to stress when removing the sapphire substrate, and to improve the current diffusion and etching selectivity, 13), the thickness of 0.5 µm or more and the p-type contact layer 17 is preferably 0.1 µm or more.

Thereafter, as shown in Fig. 1B, the receptor metal film 21 is formed. The seed metal 20 varies depending on the type of metal to be plated, and the metal film is plated using any one of Au, W, Pt, Cu, and Ni as seed metals. Receptor metal film 21 is preferably plated at least one of Au, Cu, CuW, Pt, Mo, W in consideration of the electrical conductivity and thermal conductivity, and after the heat treatment by depositing the ohmic electrode and the seed metal electroplating or The plating may be performed by electroless plating. In the case of electroplating, the plating speed of the receptor metal film is accurately measured and plated at a thickness of 1 μm to 100 μm.

After the plating is finished, as shown in FIG. 1C, the sapphire substrate 11 is wrapped and polished, and SiO ₂ After the etching mask 22 was deposited about 1 μm, the sapphire substrate was etched to remove SiO ₂ of the portion to form the via hole, thereby exposing the sapphire substrate.

At this time, the lapping step may be performed before the plating, but may be preferable before the plating in consideration of the uniformity of the sapphire substrate thickness after lapping. The lapping thickness of the sapphire substrate 11 is preferably as thin as possible in order to minimize the etching process time. However, the lapping thickness of the sapphire substrate 11 is preferably about 5 μm to 200 μm because it may damage the nitride semiconductor during lapping. During the sapphire substrate etching, the roughness of the surface of the sapphire substrate 11 is transferred to the nitride semiconductor layers 12, 13, 14, 15, 16 and 17 as it is, so that the nitride semiconductor structure may be damaged. 11) It is desirable that the surface roughness be 20 μm or less.

The lapping of the sapphire substrate 11 may include chemical mechanical polishing (CMP), ICP / RIE dry etching, and alumina slurry (Al ₂ O _3). slurry), mechanical polishing with diamond slurry or hydrochloric acid (HCl), nitric acid (HNO ₃ ), potassium hydroxide (KOH), sodium hydroxide (NaOH), sulfuric acid (H ₂ SO ₄ ), phosphoric acid (H ₃ PO ₄ ), At least one or a combination of chromium oxide (CrO ₃ ), potassium hydroxide (KOH), potassium hydrogen sulfate (KHSO ₄ ), and aloe etch (4H ₃ PO ₄ + 4CH ₃ COOH + HNO ₃ + H ₂ O) By the wet etching which uses the mixed solution as an etching liquid. At this time, any one of BCL ₃ , Cl ₂ , HBr, Ar, or a mixed gas thereof is used as an etching gas of ICP / RIE or RIE.

Thereafter, the sapphire base substrate 11 was etched to expose the buffer layer 12 to secure the first electrode contact area (FIG. 1D). In this process, the etching mask 22 is preferably removed by etching.

The wet etching of the sapphire substrate 11 for exposing the buffer layer 12 is performed in the following manner. The etching rate of the sapphire substrate 11 by the etching solution mixed with sulfuric acid (H ₂ SO ₄ ) and phosphoric acid (H ₃ PO ₄ ) at a temperature of 200 ° C. to 400 ° C. was measured to add 5 μm to the thickness of the sapphire substrate 11. Immerse in the etching solution for enough time to etch the thickness.

When the etching solution used herein, the etching rate of the GaN nitride semiconductor was 1/10 or less than that of the sapphire substrate 11. That is, the etching selectivity of the nitride based semiconductor layers 12, 13, 14, 15, 16, and 17 with respect to the sapphire base substrate 11 is 10 or more. Therefore, even though the etching process is performed for a time remaining after the sapphire base substrate 11 is completely etched, the etching speed of the nitride semiconductor layers 12, 13, 14, 15, 16, and 17 is slow, so that the nitride semiconductor layers 12, 13, 14, 15, 16, 17) are less likely to be damaged.

On the other hand, it is preferable to maintain the temperature of the etching solution at 100 ℃ or more in order to shorten the etching time. The heating for maintaining the temperature of the etching solution above 100 ℃ may be a direct heating method to put the solution on the heater or directly contact the heater and the indirect heating method using light absorption.

ICP / RIE technology may be used to etch the sapphire base substrate 11 for forming the first electrode pad 24. In order to quickly etch the sapphire substrate 11, it is desirable to increase the ICP and RIE power as much as possible, but care must be taken because it may damage the epi layer.

2 is a graph showing the etching rates of sapphire and GaN by ICP / RIE dry etching. As shown in FIG. 2, as a result of experimenting at 100 sccm of BCl ₃ , 1800 W of inductive power, and 10 mTorr of chamber pressure, the sapphire and nitride semiconductors have increased etching rates as the ICP and RIE powers are increased. However, it can be seen that the etching ratio (Al ₂ O ₃ etching rate vs. GaN etching rate) between the sapphire and the nitride semiconductor is decreasing.

These results indicate that when the sapphire substrate 11 is etched by the ICP / RIE technique, which is a dry etching technique, it is difficult to stop the etching in the buffer layer 12 made of nitride-based semiconductor. In order to stop the etching in the buffer layer 12, an optical analysis is performed. Techniques such as methods or residual gas analysis methods should be used. Even with these analytical techniques, the probability of success is low. However, in the wet etching method, the nitride semiconductor layers 12 and 13 may be used as an etch stop layer to secure a process margin, which is a requirement for mass production.

3 is a graph showing the etching rate when wet etching sapphire and GaN with a mixture solution of sulfuric acid (H ₂ SO ₄ ) and phosphoric acid (H ₃ PO ₄ ). As can be seen in Figure 3, the sapphire etching rate of the nitride-based semiconductor of the solution of sulfuric acid and phosphoric acid is dependent on the mixing ratio of sulfuric acid and phosphoric acid and is rapidly etched as the sulfuric acid increases. The etching rate of GaN nitride semiconductor also depends on the mixing ratio of sulfuric acid, and the etching selectivity with sapphire is more than 20 at a specific ratio.

These results indicate that the nitride semiconductor layers 12 and 13 can be effectively used as an etch stop layer of the sapphire substrate 11, and as shown in FIG. 4, an etching selectivity of 20 or more can be obtained at a high temperature of 100 ° C. there was.

5 is a sapphire substrate surface photograph after forming a specific pattern on the sapphire substrate by the wet etching method, and etching the sapphire substrate by the wet etching method. 5, it can be seen that the etched slope and the bottom are very clean. The sapphire substrate 11 was etched at 22.4 μm for 20 minutes at a temperature of 325 ° C., resulting in an etching rate of 1.1 μm / min. This etching rate is remarkable, and considering the mass production is not a problem at all, wet etching is not limited by the productivity of the equipment can be said to have many advantages over any method in terms of mass production.

The sapphire substrate 11 etching technique may be used to form a dicing line or cleve, brake line of the device at the same time as the via hole is formed. When the sapphire substrate was etched with a mixture of sulfuric acid (H ₂ SO ₄ ) and phosphoric acid (H ₃ PO ₄ ) for a pattern having various line widths, the etched depth was different according to the open pattern width. The wider the pattern, the deeper the pattern and the narrower the line width.

In other words, in wet etching, the sapphire substrate is oriented in wet etching and the etching depth depends on the patterned line width. The base substrate 11 of sapphire mainly used is the C plane of (0001), and when the wet etching is performed, the angle of the etching surface forms an inclined surface of 54 ° or 25 ° depending on the M plane, the R plane, and the A plane. . This phenomenon is due to the difference in etching speed between C surface of (0001), M surface of (10-10), R surface of (-1012) and A-etched facet surface of (11-20). Because. In other words, the surface orientation dependence of sapphire etching speed was found to be C plane> R plane> M plane> A plane, and as a result, the etch depth is determined by the open line width. This means that you can control the depth of etching by yourself.

As shown in FIG. 6, when the surface was etched under a microscope, the surface morphology was very clean and no large thickness deviation could be observed. Etching the (0001) side of the sapphire substrate to a certain depth gave the etched cross section a V-grooved shape, making it cleaner than any diamond pen made a cleavage line. Dicing line should be 20μm line width and etching stops at a certain depth during via hole etching, so that scribing line is automatically formed, so dicing line can be formed to separate into individual chips without additional process after forming via hole. Can be.

As shown in FIG. 1E, the dicing line 25 is formed at a place where the device is to be separated by a method combining one or more wet or dry methods, and the device may be easily separated, and the cut surface may be removed. You can make a clean mirror.

When the sapphire wet etching technology is applied to mass production, another important factor is to secure process conditions that can increase the etching selectivity between the sapphire substrate 11 and the nitride semiconductor layers 12 and 13, and particularly the nitride semiconductor layer ( 12, 13) is effective as a sapphire etch stop layer. As the nitride semiconductor layers 12 and 13, an In _x (Ga _y Al _1-y ) N (1≥x≥0, 1≥y≥0, x + y> 0) series may be used, and preferably Al It is effective to increase the composition ratio of or to use p-type GaN doped with Mg, and if necessary, before forming the nitride semiconductor layer 12 on the sapphire substrate 11, a protective film such as SiO ₂ or SiNx is locally applied. It may be formed separately to form an etch stop layer. In particular, SiO ₂ has a high wet etching selectivity to sapphire.

6 is a photograph of the surface of the buffer layer 12 after the sapphire substrate is removed by a wet etching method. As can be seen in FIG. 6, even after the sapphire base substrate 11 was removed, almost no crack or damage of the thin film due to stress was found, and the surface of the nitride semiconductor layer 12 was also very clean.

Thereafter, the buffer layer 12 is dry etched using RIE to expose the first ohmic contact layer 13, and the first electrode pad 24 is formed to be heat-treated. In order to obtain a low contact resistance, the first electrode pad 24 is heat-treated by depositing any one of Al, Pt, Ta, Ni, Cr, Au, Ti, or an alloy of these metals. Heat treatment was performed for 2 minutes at a temperature of 300 ℃ to 600 ℃ in a furnace in a nitrogen atmosphere.

As shown in FIG. 1E, when forming a via hole for dicing a substrate, SiO ₂ was patterned to remove sapphire of a portion to be diced. Commonly used dicing equipment uses diamond blades, but cutting the sapphire substrate is rather cumbersome and reduces productivity. In order to solve this problem, the dicing line 25 is formed at the same time to form a via hole, which not only reduces the process time and the process cost but also separates the device through a cleavage process without using dicing equipment. This reduces the manufacturing cost. After the heat treatment is completed, the wafer can be separated by dicing according to the size of the device.

The characteristics of the light emitting diode manufactured in the first embodiment are summarized as follows. The vertical electrode diode is formed on the receptor metal film 21 serving as the second electrode, the seed metal 20 formed on the receptor metal film 21, the ohmic electrode 18, and the ohmic electrode 18. 1 ohmic contact layer 17, the second cladding layer 16, the light emitting layer 15, the first cladding layer 14, the first ohmic contact layer 13, the buffer layer 12 and the first electrode The first electrode pad 24 is present, and the first electrode pad 24 is connected to the first ohmic contact layer 13 through the via hole 23 formed by etching the sapphire substrate 11 and the buffer layer 12. It is electrically inter-connected. Here, the first electrode pad 24 covers a part of the inner surface of the via hole 23 and penetrates the via hole to contact the first ohmic contact layer 13, and the via hole 23 is fixed to a predetermined depth. It is formed in the form of filling. The horizontal cross-sectional shape of the via hole 23 may be variously modified, such as a circle or a quadrangle, and the number of the via holes 23 may be formed as well as a plurality. In this structure, light is generated in the light emitting layer 15 and emitted to the outside through the sapphire substrate 11. The first ohmic contact layer may be n-type, and the second ohmic contact layer may be p-type.

Second Embodiment

7 is a cross-sectional view and a plan view of a light emitting diode having a vertical electrode structure according to a second embodiment of the present invention. As shown in FIG. 7, the formation of the ohmic electrode 18, the seed metal 20, and the nitride-based semiconductor layers 12, 13, 14, 15, 16, and 17, etching of the sapphire base substrate, formation of a dicing line, etc. The detailed manufacturing method of the light emitting diode of the light emitting diode is similar to that of the first embodiment, but the sapphire base substrate 11 is formed without forming the light transmissive electrode or the transparent electrode 26 and the first electrode pad 24 in the via hole 23. What is formed above is different from the first embodiment.

The first electrode is formed of a light transmissive electrode or a transparent electrode 26 to facilitate current diffusion and light extraction. The light transmissive electrode is preferably formed of a thin metal of Ni, Au, Pt, Ti, Al or an alloy thereof to facilitate light transmission. In the case of a transparent electrode, ITO (Indium Tin Oxide), ZnO It is preferable to form any one of the current diffusion and transparency to facilitate light extraction.

When forming a transparent ohmic electrode from any one of Ni, Au, Pt, Ti, and Al or an alloy thereof, it is preferable to thin the current diffusion without causing problems, but the overall thickness is considered in consideration of current diffusion. It is preferable to make 10 kPa to 500 kPa. Ni / Au / Ni, Ti / Au, and Al are deposited to form a light transmissive electrode in a furnace containing oxygen or nitrogen at a temperature of 400 ° C. to 700 ° C. for 1 minute to 5 minutes. It is preferable to heat-treat. The wafer after heat treatment may be diced according to the size of the device to separate the device.

The characteristics of the light emitting diodes manufactured in the second embodiment are summarized as follows. The vertical electrode diode includes a receptor metal film 21 serving as a second electrode, a seed metal 19 formed on the receptor metal film 21, an ohmic electrode 18, and an ohmic electrode 18. 1 ohmic contact layer 17, second cladding layer 16, light emitting layer 15, first cladding layer 14, first ohmic contact layer 13, buffer layer 12 and sapphire base substrate 11 ), A light transmissive electrode or a transparent electrode 26 is present on the sapphire base substrate 11, and the light transmissive electrode or the transparent electrode 26 is a via hole formed by etching the sapphire substrate 11 and the buffer layer 12. 23 is electrically connected to the first ohmic contact layer 13. The first electrode pad 24 is formed at a position outside the via hole on the light transmissive electrode or the transparent electrode 26. Here, the light transmissive electrode or the transparent electrode 26 covers a part of the inner surface of the via hole and penetrates the via hole to contact the first ohmic contact layer 13. The transparent electrode or the transparent electrode 26 and the first electrode pad 24 serve as the first electrode. The first ohmic contact layer may be n-type, and the second ohmic contact layer may be p-type.

Third Embodiment

8 is a cross-sectional view and a plan view of a light emitting diode having a vertical electrode structure according to a third embodiment of the present invention. As shown in FIG. 8, the third embodiment is similar to the first embodiment in that the manufacturing method of the light emitting diode such as etching the ohmic electrode 18 and the seed metal 20, the sapphire base substrate, and forming the dicing line is similar. After the sapphire base substrate is etched to expose the buffer layer, the buffer layer is etched to expose the first ohmic contact layer 13 to form the first electrode pad 24.

Specific embodiments are as follows. After the growth of the nitride based semiconductor layers 12, 13, 14, 15, 16, and 17 on the sapphire substrate 11, the ohmic electrode 18 and the seed metal 20 are deposited on the second ohmic contact layer 17. The ohmic electrode 18 is deposited with any one of Pt, Ni, Au, Rh, Pd, Ti, or an alloy of these metals, and then, for 1 minute at a temperature of 300 ° C to 700 ° C in a furnace containing nitrogen or oxygen. Heat treatment for 5 minutes.

On the sapphire substrate 11, the buffer layer 12 and the n-type and p-type conductive contact layers 13 and 17, the n-type and p-type cladding layers 14 and 16, and the light emitting layer 15 are In _x (Al _y Ga). _{1- y} ) N nitride semiconductor, and x and y have values of 1≥x≥0, 1≥y≥0, and x + y> 0. The n-type conductive contact layer 13 is doped with a Si impurity of 10 ¹⁸ or more to have a resistivity of ¹ × 10 ⁻¹ Ωcm or less, and the p-type contact layer 17 is doped with a Mg impurity of 10 ¹⁹ or more to 1 × 10 ^{−. It} has a specific resistance of ¹ Ωcm or less.

The total thickness of the nitride-based semiconductor thin film preferably has a thickness of 1 μm to 100 μm in order to minimize the cracking of the nitride semiconductor due to stress when removing the sapphire substrate, and to improve the current diffusion and etching selectivity, 13), the thickness of 0.5 µm or more and the p-type contact layer 17 is preferably 0.1 µm or more.

The seed metal 20 varies depending on the type of metal to be plated, and the receptor metal film 21 is plated using any one of Au, W, Pt, Cu, and Ni as seed metals. Receptor metal film 21 is preferably plated at least one of Au, Cu, CuW, Pt, Mo, W in consideration of electrical conductivity and thermal conductivity, by depositing the ohmic electrode 18 and the seed metal 20 After heat treatment, plating is performed by electroplating or electroless plating. In the case of electroplating, the plating rate of the receptor metal film may be accurately measured and plated at a thickness of 0.1 μm to 100 μm.

After the plating is completed, the sapphire substrate 11 is wrapped and polished, the SiO ₂ etching mask 22 is deposited by about 1 μm, and the sapphire substrate is etched to remove SiO ₂ in the portion to form the via hole, thereby removing the sapphire substrate. Exposed. At this time, the lapping step may be performed before the plating, but may be preferable before the plating in consideration of the uniformity of the sapphire substrate thickness after the lapping. The lapping thickness of the sapphire substrate 11 is preferably as thin as possible in order to minimize the etching process time. However, if the thickness of the sapphire substrate 11 is too thin, the nitride semiconductor may be damaged during lapping.

In addition, since the roughness of the surface of the sapphire substrate 11 is transferred to the nitride semiconductor layers 12, 13, 14, 15, 16, and 17 as it is, during the sapphire substrate etching, the nitride semiconductor structure may be damaged. 11) It is preferable to make the surface roughness into 20 micrometers or less. The lapping of the sapphire substrate 11 is performed by chemical mechanical polishing (CMP), ICP / RIE dry etching, mechanical polishing using alumina (Al ₂ O ₃ ) powder or hydrochloric acid (HCl), nitric acid (HNO ₃ ), potassium hydroxide (KOH). ), Sodium hydroxide (NaOH), sulfuric acid (H ₂ SO ₄ ), phosphoric acid (H ₃ PO ₄ ), chromium oxide (CrO ₃ ), potassium hydroxide (KOH), potassium hydrogen sulfate (KHSO ₄ ) and aloe etch (4H ₃ PO ₄ + 4CH ₃ COOH + HNO ₃ + H ₂ O) proceeds by wet etching with a mixed solution of at least one or a combination thereof as an etching solution. At this time, any one of BCL ₃ , Cl ₂ , HBr, Ar, or a mixed gas thereof is used as an etching gas of ICP / RIE or RIE.

Subsequently, all of the sapphire substrates were etched to expose the buffer layer 12 completely, followed by dry etching of the buffer layer 12 to secure a contact area of the first electrode pad 24. The wet etching of the sapphire substrate 11 for exposing the buffer layer 12 is performed in the following manner. An etching rate of the sapphire substrate 11 by the etching solution mixed with sulfuric acid (H ₂ SO ₄ ) and phosphoric acid (H ₃ PO ₄ ) at a temperature of 200 ° C. to 400 ° C. was measured to be about 5 μm thicker than the thickness of the sapphire substrate 11. Immerse the etch solution for the time to etch the thickness plus thickness.

On the other hand, it is preferable to maintain the temperature of the etching solution at 100 ℃ or more in order to shorten the etching time. The heating for maintaining the temperature of the etching solution above 100 ℃ may be a direct heating method to put the solution on the heater or directly contact the heater and the indirect heating method using light absorption.

By using the sapphire substrate 11 etching technology, the dicing line or cleavage line 25 of the device may be formed at the same time as the via hole formation, and dicing at a place where the device is to be separated by a combination of one or more wet or dry methods. By forming lines, not only can the device be easily separated, but also the cut surface can be made into a clean mirror surface.

Thereafter, the buffer layer 12 is dry etched using ICP / RIE or RIE to expose the first ohmic contact layer 13, and the first electrode pad 24 is formed to be heat-treated. In order to obtain a low contact resistance, the first electrode pad 24 is heat-treated by depositing any one of Al, Pt, Ta, Ni, Cr, Au, Ti, or an alloy of these metals. The heat treatment was carried out for 2 minutes at a temperature of 300 ℃ to 600 ℃ in a furnace containing nitrogen. The wafer after heat treatment may be diced according to the size of the device to separate the device.

As shown in FIG. 8, the characteristics of the light emitting diode manufactured in the third embodiment are summarized as follows. The vertical electrode diode includes a receptor metal film 21 serving as a second electrode, a seed metal 20 formed on the receptor metal film 21, an ohmic electrode 18, and a first ohmic contact layer 17. The second cladding layer 16, the light emitting layer 15, the first cladding layer 14, the first ohmic contact layer 13, and the first electrode pad 24 serving as the first electrode are present.

Fourth Embodiment

9 is a cross-sectional view and a plan view of a light emitting diode having a vertical electrode structure according to a fourth embodiment of the present invention. As shown in FIG. 9, the detailed manufacturing method of the light emitting diode such as etching of the ohmic electrode 18 and the seed metal 20, the sapphire base substrate, and the formation of the dicing line is similar to that of the third embodiment. Forming the transparent electrode 26 and the first electrode pad 24 is different from the third embodiment.

The first electrode is formed of a light transmissive electrode or a transparent electrode 26 to facilitate current diffusion and light extraction. The light transmissive electrode is preferably formed of a thin metal of any one of Ni, Au, Pt, Ti, and Al or an alloy thereof to facilitate light transmission, and in the case of a transparent electrode, ITO (Indium Tin Oxide) or ZnO It is preferable to form any one so as to secure current diffusion and transparency to facilitate light extraction.

When forming a transparent ohmic electrode made of any one of Ni, Au, Pt, Ti, and Al or an alloy thereof, it is preferable to thin the film within a limit that does not cause a problem in current spreading. It is preferable to make 10 kPa to 500 kPa. Ni / Au / Ni, Ti / Au, and Al are deposited to form a light transmissive electrode in a furnace containing oxygen or nitrogen at a temperature of 400 ° C. to 700 ° C. for 1 minute to 5 minutes. It is preferable to heat-treat. The wafer after heat treatment may be diced according to the size of the device to separate the device.

The characteristics of the light emitting diodes manufactured in the fourth embodiment are as follows. The vertical electrode diode includes a receptor metal film 21 serving as a second electrode, a seed metal 20 formed on the receptor metal film 21, an ohmic electrode 18, and an ohmic electrode 18. A first ohmic contact layer 17, a second cladding layer 16, a light emitting layer 15, a first cladding layer 14, a first ohmic contact layer 13 and a light transmissive electrode or a transparent electrode 26, The first electrode pad 24 is present on the light transmissive electrode or the transparent electrode 26. The transparent electrode 26 or the transparent electrode 26 and the first electrode pad 24 become the first electrode. The first ohmic contact layer may be n-type, and the second ohmic contact layer may be p-type.

Fifth Embodiment

10 is a cross-sectional view and a plan view of a light emitting diode having a vertical electrode structure according to a fifth embodiment of the present invention. As shown in FIG. 10, the detailed manufacturing method of the light emitting diode such as etching the ohmic electrode 18 and the seed metal 20, the sapphire base substrate, and forming the dicing line is similar to that of the fourth embodiment, but the light transmitting electrode or It is different from the fourth embodiment to form the mesh type electrode 27 instead of the transparent electrode.

The first electrode was formed of a mesh type electrode 27 to facilitate light extraction. The mesh type electrode 27 is formed of a metal of any one of Ni, Au, Pt, Ti, and Al or an alloy thereof, and is 1 minute to 5 minutes at a temperature of 400 ° C. to 700 ° C. in a furnace containing oxygen or nitrogen. Preference is given to heat treatment for minutes.

The lower part of the first electrode pad 24 is exposed to make a contact contact or to insert an insulator in the lower part of the electrode pad to prevent concentration of current to the lower part of the current pad. The wafer after heat treatment may be diced according to the size of the device to separate the device.

The features of the vertical light emitting diodes manufactured in the fifth embodiment are summarized as follows. The vertical electrode diode is formed of a receptor metal film 21 serving as a second electrode, a seed metal 20 and an ohmic electrode 18 formed on the receptor metal film 21, and an ohmic electrode 18. 1 ohmic contact layer 17, second cladding layer 16, light emitting layer 15, first cladding layer 14, first ohmic contact layer 13, mesh electrode 27 and first electrode There is a pad 24. The mesh type electrode 27 and the first electrode pad 24 become the first electrode. Here, the first ohmic contact layer may be n-type and the second ohmic contact layer may be p-type.

Sixth Embodiment

11A to 11F illustrate an intermediate manufacturing process of a light emitting diode having a vertical electrode structure according to a sixth embodiment of the present invention. As shown in FIG. 11A, when the growth of the nitride based semiconductor layers 12, 13, 14, 15, 16, and 17 on the sapphire substrate 11 is completed, the ohmic electrode 18 is placed on the second ohmic contact layer 17. Deposit. The ohmic electrode 18 is deposited at any one of Pt, Ni, Au, Rh, Pd, Ti, or an alloy of these metals, and then, for 1 minute to 5 minutes at a temperature of 300 ° C. to 700 ° C. in a furnace containing nitrogen or oxygen. Heat treatment for minutes.

In particular, the micro pipe formed due to the metal crust formed during the metal deposition provides a passage through which the etching solution can flow, thereby allowing the etching solution to penetrate into the nitride semiconductor layer, thereby forming the second ohmic contact layer 17. In order to protect the second ohmic contact layer 17, it is preferable to form Pt, which is not damaged by the etching solution, as the ohmic electrode.

Thereafter, an oxide film 19 of SiO ₂ is deposited on the ohmic electrode 18, and a second via hole 191 is formed to electrically connect the ohmic electrode 18 and the receptor metal film 21. Since the deposition of the SiO ₂ oxide film does not protect the nitride semiconductor layer with only the ohmic electrode 18 when the sapphire substrate is wet-etched, the SiO ₂ oxide film is less susceptible to acid to protect the nitride semiconductor layer. For sake. Thereafter, the seed metal 20 is deposited on the oxide film 19 of SiO ₂ to be electroplated.

The light emitting diode structure on the sapphire substrate 11 includes the buffer layer 12 and the n-type and p-type conductive contact layers 13 and 17, the n-type and p-type cladding layers 14 and 16, and the light-emitting layer 15 is In _x. (Ga _y Al _{1 -y} ) N nitride semiconductor, and x and y have values of 1≥x≥0, 1≥y≥0, and x + y> 0. The n-type conductive contact layer 13 is doped with a Si impurity of 10 ¹⁸ or more and has a resistivity of 1x10 ^-1 Ωcm or less, and the p-type contact layer 17 is doped with a Mg impurity of 10 ¹⁹ or more to 1x10 ^It has a specific resistance of ^-1 Ωcm or less.

The total thickness of the nitride-based semiconductor thin film preferably has a thickness of 1 μm to 100 μm in order to minimize the cracking of the nitride semiconductor due to stress when removing the sapphire base substrate, and the n-type ohmic contact layer ( 13), the thickness of 0.5 µm or more and the p-type contact layer 17 is preferably 0.1 µm or more.

The seed metal 20 varies depending on the type of metal to be plated, and the receptor metal film 21 is plated using any one of Au, W, Pt, Cu, and Ni as seed metals. Receptor metal film 21 is preferably plated at least one of Au, Cu, CuW, W, Pt, Mo in consideration of electrical conductivity and thermal conductivity, by depositing the ohmic electrode 18 and the seed metal 20 After heat treatment, plating is performed by electroplating or electroless plating. In the case of electroplating, the plating rate of the receptor metal film is accurately measured and plated to a thickness of 0.1 μm to 100 μm.

As shown in FIG. 11E, the plated sample may wrap and polish the sapphire substrate 11, deposit the SiO ₂ etching mask 22 by about 1 μm, and etch the sapphire substrate to form the via hole 23. The part of SiO ₂ was removed to expose the sapphire substrate.

At this time, the lapping step may be performed before the plating, but may be preferable before the plating in consideration of the uniformity of the sapphire substrate thickness after lapping. The lapping thickness of the sapphire substrate 11 should be as thin as possible in order to minimize the etching process time. However, if the thickness is too thin, the nitride semiconductor may be damaged during ripping. In addition, since the roughness of the surface of the sapphire substrate 11 during the etching of the sapphire base substrate is transferred to the nitride semiconductor layers 12, 13, 14, 15, 16 and 17 as it is, the mirrored polished sapphire The roughness of the surface of the base substrate 11 is preferably 20 μm or less.

The lapping of the sapphire substrate 11 is performed by chemical mechanical polishing (CMP), ICP / RIE dry etching, mechanical polishing using alumina (Al ₂ O ₃ ) powder or hydrochloric acid (HCl), nitric acid (HNO ₃ ), potassium hydroxide (KOH). ), Sodium hydroxide (NaOH), sulfuric acid (H ₂ SO ₄ ), phosphoric acid (H ₃ PO ₄ ), chromium oxide (CrO ₃ ), potassium hydroxide (KOH), potassium hydrogen sulfate (KHSO ₄ ) and aloe etch (4H ₃ PO ₄ + 4CH ₃ COOH + HNO ₃ + H ₂ O) proceeds by wet etching with a mixed solution of at least one or a combination thereof as an etching solution. At this time, any one of BCL ₃ , Cl ₂ , HBr, Ar, or a mixed gas thereof is used as an etching gas of ICP / RIE or RIE.

After removing all of the SiO ₂ etching mask 22, the sapphire substrate was etched to expose the buffer layer 12 to secure the contact area of the first electrode pad 24 (FIG. 11F). The wet etching of the sapphire substrate 11 for exposing the buffer layer 12 is performed in the following manner. The etching rate of the sapphire substrate 11 by the etching solution mixed with sulfuric acid (H ₂ SO ₄ ) and phosphoric acid (H ₃ PO ₄ ) at a temperature of 200 ° C. to 400 ° C. was measured to measure about 5 μm from the thickness of the sapphire substrate 11. Immerse the etch solution for the amount of time to add the additional thickness.

When the etching solution used herein, the etching rate of the GaN nitride semiconductor was 1/10 or less than that of the sapphire substrate 11. That is, the etching selectivity of the nitride based semiconductor layers 12, 13, 14, 15, 16, and 17 with respect to the sapphire base substrate 11 is 10 or more. Therefore, even though the etching process is performed for a time remaining even after the sapphire base substrate 11 is completely etched, the etching rate of the nitride semiconductor layers 12, 13, 14, 15, 16, and 17 is slow. , 14, 15, 16, 17) are less likely to be damaged.

On the other hand, it is preferable to maintain the temperature of the etching solution at 100 ℃ or more in order to shorten the etching time. The heating for maintaining the temperature of the etching solution above 100 ℃ may be a direct heating method to put the solution on the heater or directly contact the heater and the indirect heating method using light absorption.

ICP / RIE technology may be used for etching the sapphire base substrate 11. In order to quickly etch the sapphire substrate 11, it is desirable to increase the ICP and RIE power as much as possible, but care must be taken because it may damage the epi layer.

By using the sapphire substrate 11 etching technology, the dicing line 25 of the device may be formed at the same time as the via hole is formed. When the sapphire substrate was etched with a mixture of sulfuric acid (H ₂ SO ₄ ) and phosphoric acid (H ₃ PO ₄ ) for a pattern having various line widths, the etched depth was different depending on the open pattern width. The wider the pattern, the deeper the pattern and the narrower the line width.

In other words, in wet etching, the sapphire substrate is oriented in wet etching and the etching depth depends on the patterned line width. The sapphire base substrate 11, which is mainly used, is the C plane of (0001), and when the wet etching is performed, the angle of the etching plane forms an inclined plane of about 54 ° or 25 ° depending on the M plane, the R plane, and the A plane. This phenomenon is due to the difference in etching speed between C surface of (0001), M surface of (10-10), R surface of (-1012), and A surface-etched facet surface of (11-20). Because. In other words, the surface orientation dependence of sapphire etching speed was found to be C plane> R plane> M plane> A plane, and as a result, the etch depth is determined by the open line width. This means that you can control the depth of etching by yourself.

When the sapphire wet etching technology is applied to mass production, another important factor is to secure process conditions for increasing the etching selectivity between the sapphire substrate 11 and the nitride semiconductor layers 12 and 13, and in particular, the nitride semiconductor layer ( 12, 13) is effective as a sapphire etch stop layer. As the nitride semiconductor layers 12 and 13, an In _x (Ga _y Al _1-y ) N (1≥x≥0, 1≥y≥0, x + y> 0) series may be used, and preferably Al It is effective to increase the composition ratio of or to use p-type GaN doped with Mg, and if necessary, before forming the nitride semiconductor layer 12 on the sapphire substrate 11, a protective film such as SiO ₂ or SiNx is locally applied. It may be formed separately to form an etch stop layer. In particular, SiO ₂ has a sapphire and a high wet etching selectivity.

Thereafter, as shown in FIG. 11F, the buffer layer 12 is dry-etched using ICP / RIE or RIE to expose the first ohmic contact layer 13, and the first electrode pad 24 is formed to be heat treated. In order to obtain a low contact resistance, the first electrode pad 24 is heat-treated by depositing any one of Al, Pt, Ta, Ni, Cr, Au, Ti, or an alloy of these metals. The heat treatment was carried out for 2 minutes at a temperature of 300 ℃ to 600 ℃ in a furnace containing nitrogen. After the heat treatment is completed, the wafer can be separated by dicing according to the size of the device.

The characteristics of the light emitting diode manufactured in the sixth embodiment are as follows. The vertical electrode type diode includes a receptor metal film 21 serving as a second electrode, a seed metal 20 formed on the receptor metal film 21, and a second via hole 191 formed on the seed metal 20. The formed oxide film 19, the ohmic electrode 18 formed on the oxide film 19, the ohmic electrode 18 and the seed metal 20 are electrically connected to each other through a second via hole 191. The first ohmic contact layer 17, the second cladding layer 16, the light emitting layer 15, the first cladding layer 14, the first ohmic contact layer 13, and the buffer layer may be disposed on the ohmic electrode 18. 12) and the sapphire base substrate 11, and the first electrode pad 24 serving as the first electrode has a first ohmic contact through the via hole 23 formed by etching the sapphire substrate 11 and the buffer layer 12. It is electrically inter-connected with layer 13. Here, the first electrode pad 24 covers a part of the inner surface of the via hole 23, contacts the first ohmic contact layer 13 through the via hole, and fills the via hole 23 to a predetermined depth. It is. The first electrode pad 24 becomes the first electrode.

The horizontal cross-sectional shape of the via hole 23 may be variously modified, such as a circle or a square, and the number of via holes may be formed as well as a plurality. In this structure, light is emitted from the light emitting layer 15 and emitted to the outside through the sapphire base substrate 11. The first ohmic contact layer may be n-type, and the second ohmic contact layer may be p-type.

In the present invention, since the sapphire substrate is removed by using back grinding and dry or wet etching, the productivity is greatly improved, and in the case of the laser lift-off method, thermal damage that the epi layer can receive can be prevented. In addition, by utilizing the etching selectivity between the sapphire substrate and the nitride semiconductor can be easily improved the reproducibility of the process, and the standardized process is possible to facilitate mass production.

The present invention can be applied to all nitride based semiconductors of In _x (Ga _y Al _{1 -y} ) N series grown on a sapphire base substrate as well as a blue nitride based light emitting device having a wavelength of 470 nm. In the case of fabricating a nitride-based light emitting device, since the GaN layer used as a buffer layer can be removed, it can be very useful for a device emitting light in an ultraviolet region of 365 nm or less, which is a GaN bandgap wavelength. It is a key technology in the LED lighting field that enables the production of high brightness / high performance nitride semiconductor light emitting devices by improving reliability and brightness, reducing device size, and improving productivity and device performance.

As described above, in the vertical light emitting diode having the same structure as the present invention, since the first electrodes 24, 26, 27 and the second electrode 21 are formed on both upper and lower sides of the chip, a light emitting diode having a vertical electrode structure is manufactured. In addition, the chip area can be reduced, thereby greatly improving the chip yield per wafer.

In addition, since the receptor metal film 21 serves as a second electrode, and the thermocompression bonding process of the eutectic metal is unnecessary, the manufacturing process can be simplified and the manufacturing efficiency can be increased.

In addition, since the via holes 23 are formed in the sapphire substrate 11 and the first electrodes 24, 26, 27 are formed of metal, heat and static electricity are efficiently discharged through the first electrode and the receptor metal film, thereby improving reliability of the device. Contributes greatly. In addition, since the current flows uniformly through the entire area of the chip, driving is possible even at a large current, and high light output can be obtained even in a single device.

The characteristics of such devices satisfy the high luminance characteristic, which is an essential requirement for the back light unit of lighting and liquid crystal display devices.

In the present invention, since the sapphire substrate is removed using back grinding and dry or wet etching, productivity is greatly improved, and thermal damage that an epitaxial layer can receive in the case of a laser lift-off method can be prevented. In addition, by utilizing the etching selectivity between the sapphire substrate and the nitride semiconductor can be easily improved the reproducibility of the process, and the standardized process is possible to facilitate mass production.

While the invention has been shown and described with respect to particular embodiments, it will be understood that various changes and modifications can be made in the art without departing from the spirit or scope of the invention as set forth in the claims below. It will be appreciated that those skilled in the art can easily know.

Claims (23)

Sapphire base substrate; A plurality of nitride-based semiconductor layers formed on the sapphire base substrate; An ohmic electrode formed on the nitride based semiconductor layer; A seed metal formed on the ohmic electrode; And And a receptor metal film formed by plating on the seed metal. The sapphire base substrate is etched and completely removed, the first electrode pad is formed on the nitride-based semiconductor layer exposed surface exposed through the etching of the sapphire substrate, the vertical electrode type light emitting diode. The vertical electrode type light emitting diode of claim 1, wherein a light transmissive electrode or a transparent electrode is formed on the nitride based semiconductor layer, and the first electrode pad is formed on the light transmissive electrode or the transparent electrode. The vertical electrode type light emitting diode of claim 2, wherein the light transmissive electrode comprises at least one of Ni, Au, Pt, Ti, and Al. The vertical electrode type light emitting diode of claim 2, wherein the transparent electrode is made of ZnO or Indium Tin Oxide (ITO). The vertical type light emitting diode of claim 1, wherein a mesh electrode is formed on the nitride semiconductor layer, and the first electrode pad is formed on the mesh electrode. The vertical electrode type light emitting diode of claim 5, wherein the mesh electrode comprises at least one of Ni, Au, Pt, Ti, and Al. The vertical electrode light emitting diode of any one of claims 1 to 6, wherein the ohmic electrode includes at least one of Pt, Ni, Au, Rh, and Pd. The vertical electrode type light emitting diode of claim 7, wherein the ohmic electrode is formed of Pt. The vertical electrode type light emitting diode of any one of claims 1 to 6, wherein the seed metal is formed of at least one of Au, W, Pt, Cu, and Ni. The vertical electrode light emitting diode according to any one of claims 1 to 6, wherein the receptor metal film is plated with at least one of Au, Cu, CuW, Mo, W, and Pt. The nitride-based semiconductor layer of claim 1, wherein the nitride-based semiconductor layer is formed of an In _x (Al _y Ga _1-y ) N nitride-based semiconductor, wherein x and y are 1 ≧ x ≧ 0, 1 ≧ y Vertical electrode type light emitting diode having a value of ≥ 0, x + y> 0. The vertical electrode type light emitting diode of any one of claims 1 to 6, wherein the first electrode comprises at least one of Al, Pt, Ta, Cr, Ni, Au, and Ti. a. forming a plurality of nitride-based semiconductor layers on the sapphire base substrate; b. forming an ohmic electrode on the nitride based semiconductor layer; c. forming a seed metal on the ohmic electrode; d. forming a receptor metal film on the seed metal; e. processing the sapphire base substrate to a predetermined thickness; f. Etching the sapphire base substrate to remove it completely and exposing the nitride semiconductor layer g. Forming a first electrode pad on the exposed nitride-based semiconductor layer; manufacturing method of a vertical electrode type light emitting diode comprising a. The method of claim 13, and f2. forming a light transmissive electrode on the exposed nitride-based semiconductor layer, wherein in step g, the first electrode pad is formed on the light transmissive electrode. . 15. The method of claim 14, wherein the step f2 is Ni / Au / Ni, Al, Ti / Al by depositing any structure of the furnace in the atmosphere containing oxygen or nitrogen at a temperature of 400 ℃ to 700 ℃ 1 minute to 5 minutes Method for producing a vertical light emitting diode, characterized in that the heat treatment for minutes. The method of claim 13, f2. The method of claim 1, further comprising forming a transparent electrode on the exposed nitride-based semiconductor layer, wherein in step g, the first electrode pad is formed on the transparent electrode. The method of claim 13, f2. A method of manufacturing a vertical light emitting diode, further comprising the step of forming a mesh electrode on the exposed nitride-based semiconductor layer, wherein the first electrode pad is formed on the mesh electrode in step g. . The method of claim 17, wherein the step f2 is formed by containing at least one of Ni, Au, Pt, Ti, Al, and 1 minute to 5 to a temperature of 400 ℃ to 700 ℃ in a furnace containing oxygen or nitrogen Method for producing a vertical light emitting diode, characterized in that the heat treatment for minutes. 19. The method of any one of claims 13 to 18, wherein step b deposits at least one of Pt, Ni, Au, Rh, Pd, and contains nitrogen or oxygen in a temperature of 300 ° C to 700 ° C. Method for manufacturing a vertical light emitting diode, characterized in that the heat treatment for 1 minute to 5 minutes. 19. The vertical light emitting diode of any one of claims 13 to 18, wherein the d step is performed by plating at least one of Au, Cu, CuW, Mo, W, and Pt by electroplating or electroless plating. Manufacturing method. 19. The etching method of any one of claims 13 to 18, wherein the etching of the sapphire base substrate in step f is performed by mixing sulfuric acid (H ₂ SO ₄ ) and phosphoric acid (H ₃ PO ₄ ) at a temperature of 200 ° C to 400 ° C. Method for producing a vertical light emitting diode, characterized in that the wet etching with a solution. 19. The method of any one of claims 13 to 18, wherein the step f is performed to etch at least a portion of the nitride based semiconductor layer and simultaneously cut off the cleavage line for separating the base substrate into individual chips through etching. Method for producing a vertical light emitting diode, characterized in that formed. 19. The method of any one of claims 13 to 18, wherein the step g comprises at least one of Al, Pt, Ta, Cr, Ni, Au, and Ti at a temperature of 300 ° C to 600 ° C for 2 minutes in a furnace in a nitrogen atmosphere. Method of manufacturing a vertical light emitting diode, characterized in that the heat treatment.

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