KR20060079041A - Shift resister - Google Patents

Abstract

The present invention relates to a shift register.

The shift register of the present invention is a shift register for shifting an output of a front stage in a next stage, wherein each stage has a second width different from the first width after a first pulse having a first width is supplied. An output buffer configured to output a dual pulse supplied with a second pulse to the first output line; A start pulse supply unit connected to the output buffer and supplying the front stage output as a start pulse of the next stage through a second output line; And a control unit controlling a supply time point of the dual pulse and the start pulse.

Description

Shift Resister}

1 is a view showing a conventional liquid crystal display device.

2 is a diagram illustrating a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 3 is a waveform diagram illustrating driving waveforms supplied to the liquid crystal display shown in FIG. 2.

4 illustrates a shift register according to an embodiment of the present invention.

5 is a waveform diagram illustrating a driving waveform supplied to the shift register of FIG. 4.

FIG. 6 is a diagram illustrating a driving waveform supplied to drive a plurality of shift registers shown in FIG. 4.

7 is a table showing drive waveforms supplied to each shift register.

FIG. 8 is a diagram illustrating each stage implemented according to the table shown in FIG. 7.

9 is a view illustrating another liquid crystal display device which may include a shift register according to an exemplary embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

2,8 LCD panel 4,10 Data driver

6,12 gate driver 30 control unit

40: start pulse supply unit 50: output buffer

The present invention relates to a shift register, and more particularly, to a shift register capable of generating a dual pulse and supplying an output line.

The liquid crystal display device displays an image by adjusting the light transmittance of the liquid crystal using an electric field. To this end, the liquid crystal display device includes a liquid crystal panel having a pixel matrix and a driving circuit for driving the liquid crystal panel. The driving circuit drives the pixel matrix so that the image information is displayed on the display panel.

1 is a view showing a conventional liquid crystal display device.

Referring to FIG. 1, a conventional liquid crystal display device includes a liquid crystal panel 2, a data driver 4 for driving data lines DL1 to DLm of the liquid crystal panel 2, and a liquid crystal panel 2. A gate driver 6 for driving the gate lines GL0 to GLn is provided.

The liquid crystal panel 2 is a thin film transistor TFT formed at the intersection of the gate lines GL0 to GLn and the data lines DL1 to DLm, and a liquid crystal connected to the thin film transistor TFT and arranged in a matrix form. With cells.

The gate driver 6 sequentially supplies gate signals to the gate lines GL0 to GLn according to a control signal from a timing controller (not shown). The data driver 4 converts the data (R, G, B) supplied from the timing controller into a video signal, which is an analog signal, for one horizontal line for each horizontal period in which the gate signal is supplied to the gate lines GL0 to GLn. Is supplied to the data lines DL1 to DLm.

The thin film transistor TFT supplies data from the data lines DL1 to DLm to the liquid crystal cell in response to gate signals from the gate lines GL0 to GLn. The liquid crystal cell is composed of a common electrode facing each other with a liquid crystal interposed therebetween, and a pixel electrode connected to the thin film transistor TFT, so that the liquid crystal cell may be equivalently represented as a liquid crystal capacitor Clc. The liquid crystal cell includes a storage capacitor (not shown) connected to the previous gate line to maintain the data voltage charged in the liquid crystal capacitor Clc until the next data voltage is charged.

Since the liquid crystal cells of the conventional liquid crystal display are positioned at the intersections of the gate lines GL0 to GLn and the data lines DL1 to DLm, the number of data lines DL1 to DLm is equal to (m). G) form a vertical line. In other words, the liquid crystal cells are arranged in a matrix to form m vertical lines and n horizontal lines.

As can be seen here, m data lines DL1 to DLm are conventionally required to drive m vertical liquid crystal cells. Therefore, in the related art, a plurality of data lines DL1 to DLm are formed to drive the liquid crystal panel 2, and thus, a process time and a manufacturing cost are wasted.

Accordingly, an object of the present invention is to provide a shift register capable of generating a dual pulse and supplying it to an output line.

In order to achieve the above object, the shift register of the present invention is a shift register for shifting the output of a previous stage in a next stage, wherein each of the stages is provided with a first pulse after a first pulse having a first width is supplied. An output buffer configured to output a dual pulse supplied with a second pulse having a second width different from the first output line; A start pulse supply unit connected to the output buffer and supplying the front stage output as a start pulse of the next stage through a second output line; And a control unit controlling a supply time point of the dual pulse and the start pulse.

The output buffer includes a pull-up switch for controlling the supply of the dual pulse; And a pull-down switch connected between the pull-up switch and the low potential voltage.

The control unit includes a first switch for controlling the high potential voltage in response to the supply of the first clock; A second switch connected to a gate terminal of the first switch and a drain terminal connected to a low potential voltage; A third switch supplied with a second clock, connected between the source terminals of the second switch, and connected to the source terminal and the gate terminal; A fourth switch connected to the drain terminal of the third switch and controlling the high potential voltage; A fifth switch connected to a drain terminal of the first switch and connected between the fourth switch and the low potential voltage; A second node connected to the drain terminal of the fourth switch; A source terminal is connected to the first node between the drain terminal of the first switch and the pull-up switch, a gate terminal is connected to the second node between the drain terminal of the fourth switch and the pull-down switch; And a sixth switch connected to the low potential voltage.

The start pulse supply unit may include: a ninth switch having a gate terminal connected to the first node and controlling supply of the start pulse; And a tenth switch connected to the second node and connected between the ninth switch and the low potential voltage.

The first clock has a high state of the first width and is supplied before the first pulse.

The second clock has a high state of the first width and is supplied before the first pulse, and has a low state while the first pulse and the second pulse are supplied.

The front start pulse has a high state and a low state of the same width as the second clock, and is supplied by twice the first width of the second clock.

The next stage start pulse has a high state of the first width and is supplied to the next stage stage while the first pulse and the second pulse are output.

The dual pulse has a low state equal to the first width between the first pulse and the second pulse.

The width of the first pulse has a width twice the width of the second pulse.

Other objects and features of the present invention in addition to the above objects will become apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 2 to 8.

Referring to FIG. 2, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal panel 8, a data driver 10 for driving data lines DL1 to DLm / 2 of the liquid crystal panel 8. And a gate driver 12 for driving the gate lines GL0 to GLn of the liquid crystal panel 8.

The liquid crystal panel 8 includes the first liquid crystal cell 9 and the second liquid crystal cell 11 formed at the intersection of the gate lines GL0 to GLn and the data lines DL1 to DLm / 2. The first liquid crystal cell 9 is formed on the left side of the data line DL. The second liquid crystal cell 11 is formed on the right side of the data line DL. That is, the first liquid crystal cell 9 and the second liquid crystal cell 11 are formed at left and right sides with one data line DL interposed therebetween, and supply a video signal from adjacent data lines DL. Receive. In other words, the first liquid crystal cell 9 and the second liquid crystal cell 11 which are vertically adjacent to each other are supplied with a video signal from one data line DL, so that the liquid crystal display according to the embodiment of the present invention. Is reduced to half the number of data lines DL.

On the other hand, the first liquid crystal cell 9 includes first and second thin film transistors TFT1 and TFT2. The gate terminal of the first thin film transistor TFT1 is connected to the i (i is an integer) th gate line GLi, and the source terminal is connected to the i + 1 th gate line GLi + 1. The gate terminal of the second thin film transistor TFT2 is connected to the drain terminal of the first thin film transistor TFT1 and the source terminal is connected to the adjacent data line DL, and the drain terminal is the liquid crystal capacitor Clc (that is, Pixel electrode). Here, the liquid crystal capacitor Clc is represented by equally representing the common electrode facing the liquid crystal and the pixel electrode connected to the second thin film transistor TFT2.

The second liquid crystal cell 11 includes a third thin film transistor TFT3. The gate terminal of the third thin film transistor TFT3 is connected to the i-th gate line GLi, the source terminal is connected to an adjacent data line DL, and the drain terminal thereof is the liquid crystal capacitor Clc (that is, the pixel electrode). Is connected to.

The gate driver 12 sequentially supplies the first gate signal SP1 and the second gate signal SP2 to the gate lines GL0 to GLn according to a control signal from a timing controller (not shown). Here, the first gate signal SP1 is supplied after the second gate signal SP2 is supplied and has a narrower width than the second gate signal SP2. The data driver 10 converts the data R, G, and B supplied from the timing controller into a video signal, which is an analog signal, and supplies them to the data lines DL1 through DLm / 2.

The driving process of the liquid crystal display according to the exemplary embodiment of the present invention will be described in detail with reference to FIG. 3. FIG. 3 is a diagram illustrating a process of driving the i-th gate line GLi and the i + 1 th gate line GLi + 1.

Referring to FIG. 3, the gate driver 12 supplies the first gate signal SP1 to the i + 1 th gate line GLi + 1 and the second gate signal SP2 to the i th gate line GLi. ). Here, since the width of the second gate signal SP2 is set to be wider than the width of the first gate signal SP1, the first gate signal SP1 and the second gate signal SP2 simultaneously operate during the first period TA. Only the second gate signal SP2 is applied during the second period TB subsequent to the first period TA.

During a first period TA in which the first gate signal SP1 is applied to the i + 1 th gate line GLi + 1 and the second gate signal SP2 is applied to the i th gate line GLi. The first video signal DA is supplied to the first liquid crystal cell 9 connected to the i-th gate line GLi. In detail, the first gate signal SP1 supplied to the i + 1 th gate line GLi + 1 is the first thin film transistor formed on the first liquid crystal cell 9 of the i th gate line GLi. It is supplied to the source terminal of (TFT1). At this time, since the first thin film transistor TFT1 is turned on by the second gate signal SP2 supplied to the i-th gate line GLi, the first thin film transistor TFT1 is supplied to the source terminal of the first thin film transistor TFT1. The gate signal SP1 is supplied to the gate terminal of the second thin film transistor TFT2 to turn on the second thin film transistor TFT2. When the second thin film transistor TFT2 is turned on, the first video signal DA supplied to the data line DL is supplied to the liquid crystal capacitor Clc of the first liquid crystal cell 9. That is, the first period TA in which the first gate signal SP1 is applied to the i + 1 th gate line GLi + 1 and the second gate signal SP2 is applied to the i th gate line GLi. The first video signal DA is supplied to the first liquid crystal cells 9 formed in the i-th gate line GLi.

Subsequently, in the second period TB, the third thin film transistor TFT3 connected to the i-th gate line GLi is turned on. When the third thin film transistor TFT3 is turned on, the second video signal DB supplied to the data line DL is supplied to the second liquid crystal cell 11 during the second period TB.

Here, each stage of the shift register for generating a driving waveform according to the exemplary embodiment of the present invention illustrated in FIG. 3 will be described in detail with reference to FIGS. 4 and 5.

Each stage of the shift register according to an exemplary embodiment outputs a dual scan pulse CLK_DMT to which a second pulse having a second width different from the first width is supplied after a first pulse having a first width is supplied. A start pulse supply unit 40 connected to the output buffer 50, the output buffer 50 and supplying the start clock CLK_ST to the next stage start pulse Vst2, and the dual scan pulse and the start clock CLK_ST. A control unit 30 for controlling the supply time point is provided.

The output buffer 50 includes a pull-up switch NTFT7 for controlling the supply of the dual scan pulse CLK_DMT, and a pull-down switch NTFT8 connected between the pull-up switch NTFT7 and the low potential voltage VSS.

The controller 30 is connected to the first switch NTFT1 for controlling the high potential voltage VDD according to the supply of the start pulse Vst, the gate terminal is connected to the gate terminal of the first switch NTFT1, and the drain terminal is The third switch NTFT3 connected between the source terminal of the second switch NTFT2 and the source terminal of the second switch NTFT2 supplied with the second switch NTFT2 connected to the low potential voltage VSS, and the source terminal and the gate terminal connected thereto. ), The gate terminal is connected to the drain terminal of the third switch NTFT3, the fourth switch NTFT4 for controlling the high potential voltage VSS, and the gate terminal is connected to the drain terminal of the first switch NTFT1. A fifth switch NTFT5 connected between the fourth switch NTFT4 and the low potential voltage VSS, and a source terminal having a first node between the drain terminal of the first switch NTFT1 and the pull-up switch NTFT7. Q), and the gate terminal is loosened with the drain terminal of the fourth switch NTFT4. Switch (NTFT8) is connected to the second node (QB) in between, and the drain terminal of a sixth switch (NTFT6) connected to said low-potential voltage (VSS).

The start pulse supply unit 40 has a gate terminal connected to the first node Q, a ninth switch NTFT9 controlling the supply of the start clock CLK_ST pulse, and a gate terminal connected to the second node QB. And a tenth switch NTFT10 connected between the ninth switch NTFT9 and the low potential voltage VSS.

An operation process of the shift register according to the exemplary embodiment of the present invention having such a structure will be described in detail with reference to the driving waveform shown in FIG. 5.

Referring to FIG. 5, in the period A, the start pulse Vst and the end clock CLK_END become high, and the remaining clocks remain low. Therefore, as the first transistor NTFT1 is activated by the start pulse Vst, the first node Q is charged by the high potential voltage VDD. The amount of charge charged in the first node Q is supplied to the gate terminal of the fifth transistor NTFT5 to activate the fifth transistor NTFT5, and is supplied to the gate terminals of the ninth and seventh transistors NTFT9 and NTFT7. Each transistor (NTFT9, NTFT7) is turned on. In addition, the drain terminal of the third transistor NTFT3 is charged by the AND clock CLK_END, and accordingly the fourth transistor NTFT4 is activated, so that the high potential voltage connected to the source terminal of the fourth transistor NTFT7 is maintained. VDD) charges the second node QB. Here, the fifth transistor NTFT5 is formed larger than the size of the fourth transistor NTFT4 to connect the second node QB to the low potential voltage VSS. Accordingly, the gate terminals of the sixth transistor NTFT6, the tenth transistor NTFT10, and the eighth transistor NTFT8 are kept low, and each transistor is turned off.

In period B, as the start pulse Vst remains low, the first node Q is floated high. Meanwhile, as the AND clock CLK_END maintains a low state, the third transistor NTFT3 and the fourth transistor NTFT4 are turned off. As the first node Q is floated to the high state, the ninth and seventh transistors NTFT9 and NTFT7 are turned on. Accordingly, the low state of the start clock CLK_ST charges the next node NEXT to the low state, and the first pulse SP1 of the dual scan pulse CLK_DMT is output through the seventh transistor NTFT7. It is supplied to the output line through. In this case, the gate terminal of the seventh transistor NTFT7 is floated to the high state in the first pulse SP1 supplied to the seventh transistor NTFT7. Accordingly, the voltage Vq of the first node Q is boot-strapped to expand the channel of the seventh transistor NTFT7 so that the first pulse SP1 is rapidly connected to the output line through the output node OUT. Will be supplied.

In the C period, the start clock CLK_ST becomes high. Here, as the gate terminal of the ninth transistor NTFT9 maintains floating in a high state, a bootstrapping phenomenon is generated by the start clock CLK_ST supplied to the source terminal of the ninth transistor NTFT9. Accordingly, the start clock CLK_ST is supplied to the start pulse Vst2 of the next stage at a high speed through the ninth transistor NTFT9 and the next node NEXT. The low state of the dual scan pulse CLK_DMT is supplied to the output line through the seventh transistor NTFT7 and the output node OUT.

In the D period, as the start clock CLK_ST has a low state, the next node NEXT remains low, and the second pulse SP2 of the dual scan pulse CLK_DMT turns the output node OUT. Through the output line. Here, the pulse width of the first pulse SP1 is set to about half of the second pulse SP2. In this case, the bootstrapping phenomenon occurs in the seventh transistor NTFT7 having the gate terminal floating to the high state by the second pulse SP2 supplied to the source terminal. Accordingly, the second pulse SP2 is rapidly supplied to the output line through the seventh transistor NTFT7 and the output node OUT.

In the E period, as the AND clock CLK_END has a high state and the start pulse Vst maintains a low state, the third transistor NTFT3 is turned on, and accordingly, the fourth transistor NTFT4 is turned on. Is turned on. The high potential voltage VDD connected to the source terminal of the fourth transistor NTFT4 is supplied to the gate terminals of the sixth transistor NTFT6, the tenth transistor NTFT10, and the eighth transistor NTFT8. The first node Q, the next node NEXT, and the output node OUT are connected to the low potential voltage VSS. Accordingly, the output of the output line is kept low.

6 to 8 show a stage driven by the driving waveform shown in FIG. It is a figure which shows the driving method.

6 to 8, each stage according to an embodiment of the present invention is repeatedly driven by each clock and dual scan pulses of the type shown in the table for every 15 stages. For example, the first stage is driven by the first dual scan pulse CLK_DMT1, the start clock CLK_ST by the third clock CLK3, and the AND clock CLK_END by the first clock CLK1, The fifteenth stage is driven by the third dual scan pulse CLK_DMT3, the start clock CLK_ST by the first clock CLK1, and the AND clock CLK_END by the fourth clock CLK4. That is, the signals supplied to each stage are repeatedly supplied with the first dual pulses to the third dual pulses CLK_DMT1 to CLK_DMT3 to the output buffer 50 of each stage, and the start clock CLK_ST of each stage is a third clock. (CLK3), the fifth clock (CLK5), the second clock (CLK2), the fourth clock (CLK4), the first clock (CLK1) is repeatedly supplied in order, and the first clock (CLK_END) of each stage CLK1, third clock CLK3, fifth clock CLK5, second clock CLK2, and fourth clock CLK4 are sequentially supplied. Each stage stage according to the driving waveform shown in FIG. 7 is illustrated in FIG. 8.

Meanwhile, the liquid crystal display according to the exemplary embodiment of the present invention may have a liquid crystal cell structure sharing a data line as shown in FIG. 9.

In addition, the shift register according to the embodiment of the present invention may be formed by depositing amorphous silicon (Amorphous-Si) at low temperature, and thus may have an internal structure formed in the gate driver.

As described above, the shift register according to the present invention may constitute a shift register for generating a dual scan pulse and supplying it to an output line. In addition, the shift register and the gate driver having the shift register may form a shift register that is repeated every 15 stages according to a combination of a 5-phase clock and three dual scan pulses.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (10)

In the shift register for shifting the output of the previous stage in the next stage, Each of the stages, An output buffer configured to output a dual pulse supplied with a second pulse having a second width different from the first width to a first output line after a first pulse having a first width is supplied; A start pulse supply unit connected to the output buffer and supplying the front stage output as a start pulse of the next stage through a second output line; And a control unit controlling a supply time point of the dual pulse and the start pulse. The method of claim 1, The output buffer A pull-up switch controlling the supply of the dual pulses; And a pull-down switch connected between said pull-up switch and a low potential voltage. The method of claim 2, The control unit A first switch for controlling the high potential voltage in response to the supply of the first clock; A second switch connected to a gate terminal of the first switch and a drain terminal connected to a low potential voltage; A third switch supplied with a second clock, connected between the source terminals of the second switch, and connected to the source terminal and the gate terminal; A fourth switch connected to the drain terminal of the third switch and controlling the high potential voltage; A fifth switch connected to a drain terminal of the first switch and connected between the fourth switch and the low potential voltage; A second node connected to the drain terminal of the fourth switch; A source terminal is connected to the first node between the drain terminal of the first switch and the pull-up switch, a gate terminal is connected to the second node between the drain terminal of the fourth switch and the pull-down switch; And a sixth switch connected to the low potential voltage. The method of claim 3, wherein The start pulse supply unit A ninth switch connected to the first node by a gate terminal and controlling a supply of the start pulse; And a tenth switch having a gate terminal connected to the second node and connected between the ninth switch and the low potential voltage. The method of claim 3, wherein The first clock is And a high state of said first width and supplied prior to said first pulse. The method of claim 3, wherein The second clock is And having a high state of the first width and supplied before the first pulse and having a low state while the first and second pulses are supplied. The method of claim 6, The shear start pulse is The shift register having a high state and a low state of the same width as the second clock, and is supplied by twice the first width later than the second clock. The method of claim 6, The next stage start pulse And a high state of said first width and supplied to said next stage while said first pulse and said second pulse are output. The method of claim 1, The dual pulse And a low state equal to the first width between the first and second pulses. The method of claim 1, And the width of the first pulse has a width twice the width of the second pulse.

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