KR20060073132A - Gate electrode of semiconductor device and forming method thereof - Google Patents
Gate electrode of semiconductor device and forming method thereof Download PDFInfo
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- KR20060073132A KR20060073132A KR1020040111992A KR20040111992A KR20060073132A KR 20060073132 A KR20060073132 A KR 20060073132A KR 1020040111992 A KR1020040111992 A KR 1020040111992A KR 20040111992 A KR20040111992 A KR 20040111992A KR 20060073132 A KR20060073132 A KR 20060073132A
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- 238000000034 method Methods 0.000 title claims abstract description 24
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 229910000789 Aluminium-silicon alloy Inorganic materials 0.000 claims abstract description 25
- 239000002184 metal Substances 0.000 claims abstract description 25
- 229910052751 metal Inorganic materials 0.000 claims abstract description 25
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 17
- 229920005591 polysilicon Polymers 0.000 claims abstract description 17
- 230000004888 barrier function Effects 0.000 claims abstract description 14
- 150000004767 nitrides Chemical class 0.000 claims abstract description 13
- 238000000151 deposition Methods 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 238000002955 isolation Methods 0.000 claims abstract description 5
- 238000000059 patterning Methods 0.000 claims abstract description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 230000008021 deposition Effects 0.000 claims description 3
- 238000005137 deposition process Methods 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 4
- 238000005516 engineering process Methods 0.000 abstract description 2
- 239000011229 interlayer Substances 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 description 5
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 229910052741 iridium Inorganic materials 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000015654 memory Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4941—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a barrier layer between the silicon and the metal or metal silicide upper layer, e.g. Silicide/TiN/Polysilicon
Abstract
본 발명은 반도체 제조 기술에 관한 것으로, 특히 반도체 소자 제조 공정 중, 게이트 산화막의 신뢰성 및 안정성을 향상시키는 반도체 소자의 게이트 전극 형성 공정에 관한 것이다. 본 발명의 일측면에 따르면, 소자분리막이 형성된 기판 상에 게이트 산화막과 게이트 폴리실리콘막을 순차적으로 증착하는 단계, 상기 게이트 폴리실리콘막 상에 장벽금속막인 AlSixNy막을 형성하는 단계, 상기 AlSix
Ny막 위에 게이트 금속막과 하드마스크 질화막을 순차적으로 증착하는 단계, 상기 하드마스크 질화막이 형성된 결과물을 패터닝하여 게이트 전극을 형성하는 단계를 수행하는 반도체 소자의 게이트 전극 형성 방법이 제공된다.
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a process of forming a gate electrode of a semiconductor device which improves the reliability and stability of the gate oxide film during the semiconductor device manufacturing process. According to an aspect of the invention, the step of sequentially depositing a gate oxide film and a gate polysilicon film on the substrate on which the device isolation film is formed, forming an AlSi x N y film as a barrier metal film on the gate polysilicon film, the AlSi A method of forming a gate electrode of a semiconductor device is provided by sequentially depositing a gate metal film and a hard mask nitride film on a x N y film, and patterning a resultant product on which the hard mask nitride film is formed.
트랩 사이트, 장벽금속막, 층간절연막, 게이트 산화막, 하드마스크 질화막 Trap site, barrier metal film, interlayer insulating film, gate oxide film, hard mask nitride film
Description
도1a 내지 도1d은 종래기술에 따른 반도체 소자의 게이트 전극 공정을 나타낸 단면도.1A to 1D are cross-sectional views illustrating a gate electrode process of a semiconductor device according to the prior art.
도2는 본 발명의 일실시예에 따른 반도체 소자의 게이트 전극 공정을 나타낸 단면도.
2 is a cross-sectional view showing a gate electrode process of a semiconductor device according to an embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
200 : 실리콘 기판 11 : 소자분리막200: silicon substrate 11: device isolation film
12 : 게이트 산화막 13 : 게이트 폴리실리콘막12
14 : 장벽금속막(AlSixNy) 15 : 게이트 금속막14 barrier metal film (AlSi x N y ) 15 gate metal film
16 : 게이트 하드마스크 질화막
16: gate hard mask nitride film
본 발명은 반도체 제조 기술에 관한 것으로, 특히 반도체 소자 제조 공정 중 게이트 전극 형성 공정에 관한 것이다.BACKGROUND OF THE
DRAM(Dynamic Random Access Memories)을 비롯한 반도체 소자의 신뢰도 및 안정성을 확보하는데 있어서 게이트 구조가 미치는 영향은 거의 절대적이라 할 수 있다.The influence of the gate structure on the reliability and stability of semiconductor devices including DRAM (Dynamic Random Access Memories) is almost absolute.
도1a 내지 도1d는 종래기술에 따른 반도체 소자의 게이트 전극 형성 공정을 나타낸 단면도이다.1A to 1D are cross-sectional views illustrating a gate electrode forming process of a semiconductor device according to the prior art.
종래기술에 따른 게이트 전극 형성 공정은 우선, 도1a에 도시된 바와 같이, 소자분리막이 형성된 실리콘 기판(100) 표면에 게이트 산화막(2)을 성장시키고, 그 상단에 게이트 폴리실리콘막(3)을 증착한다.In the gate electrode forming process according to the related art, first, as shown in FIG. Deposit.
다음으로, 도1b에 도시된 바와 같이, 게이트 폴리실리콘막(3) 위에 장벽금속막으로서 WN막(4)을 증착한다.Next, as shown in Fig. 1B, a WN
계속해서, 도1c에 도시된 바와 같이, 상기 WN막(4) 위에 게이트 금속막(5)과 하드마스크 질화막(6)을 형성한다.Subsequently, as shown in FIG. 1C, the
계속해서, 도1d에 도시된 바와 같이, 게이트 하드마스크 질화막(6), 게이트 금속막(5), 장벽금속막인 WN막(4), 게이트 폴리실리콘막(3), 게이트 산화막(2)을 게이트 전극 마스크를 사용하여 사진 및 식각 공정을 통해 게이트 전극을 형성한다.Subsequently, as shown in FIG. 1D, the gate hard
그런데, WN막(4)은 계면특성 및 산화 장벽이 우수하지 못하고, 트랩 사이트 유발 소스의 확산을 차단하기 어려운 문제점이 있다.
However, the WN
본 발명은 상기한 종래기술의 문제점을 해결하기 위해 제안된 것으로서, 게이트 금속 원소의 게이트 절연막으로의 확산을 최소화할 수 있는 반도체 소자의 게이트 전극 및 그 형성 방법을 제공하는 것을 그 목적으로 한다.
The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a gate electrode of a semiconductor device and a method of forming the same, which can minimize diffusion of a gate metal element into a gate insulating film.
상기의 목적을 달성하기 위한 본 발명의 일측면에 따르면, 실리콘 기판 상에 제공되는 게이트 절연막, 상기 게이트 절연막 상에 제공되는 폴리실리콘막, 상기 폴리실리콘막상에 제공되는 장벽금속막으로서의 AlSixNy막, 상기 AlSixN y막 상에 제공되는 금속막을 구비하는 반도체 소자의 게이트 전극이 제공된다.According to an aspect of the present invention for achieving the above object, a gate insulating film provided on a silicon substrate, a polysilicon film provided on the gate insulating film, AlSi x N y as a barrier metal film provided on the polysilicon film A gate electrode of a semiconductor device having a film and a metal film provided on the AlSi x N y film is provided.
상기의 목적을 달성하기 위한 본 발명의 다른 측면에 따르면, 소자분리막이 형성된 기판 상에 게이트 산화막과 게이트 폴리실리콘막을 순차적으로 증착하는 단계, 상기 게이트 폴리실리콘막 상에 장벽금속막인 AlSixNy막을 형성하는 단계, 상기 AlSixNy막 위에 게이트 금속막과 하드마스크 질화막을 순차적으로 증착하는 단계, 상기 하드마스크 질화막이 형성된 결과물을 패터닝하여 게이트 전극을 형성하는 단계를 수행하는 반도체 소자의 게이트 전극 형성 방법이 제공된다.According to another aspect of the present invention for achieving the above object, the step of sequentially depositing a gate oxide film and a gate polysilicon film on the substrate on which the device isolation film is formed, AlSi x N y as a barrier metal film on the gate polysilicon film forming a film, comprising the steps of sequentially depositing a gate metal film and a hard mask, the nitride film on the AlSi x N y film, a gate electrode of a semiconductor element for performing the step of forming a gate electrode by patterning the resultant is the hard mask nitride film formed Formation methods are provided.
본 발명은 현재 장벽금속막으로 사용되고 있는 WN막 대신에 계면특성 및 산 화 장벽이 우수하고, 트랩 사이트 유발 소스의 확산을 차단할 수 있는 AlSixNy막을 적용하여 형성한다. 여기서, AlSixNy막은 전도성을 가지고 비정질(Amorphous) 특성을 유지하고 있어서 결정립계면의 확산을 완전 차단할 수 있고, 후속 금속막을 증착할 때 표면 거칠기가 우수하여 계면 특성이 우수하다.
The present invention is formed by applying an AlSi x N y film having excellent interfacial properties and an oxidation barrier, and blocking the diffusion of a trap site-induced source, instead of the WN film currently used as a barrier metal film. Here, the AlSi x N y film has conductivity and maintains amorphous properties to completely block diffusion of grain boundaries, and has excellent surface roughness when depositing subsequent metal films, thereby providing excellent interfacial properties.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .
도2는 본 발명의 일실시예에 따른 게이트 전극의 구조를 나타낸 단면도이다.2 is a cross-sectional view showing the structure of a gate electrode according to an embodiment of the present invention.
본 발명에 따른 게이트 전극 형성 공정은 우선, 소자분리막이 형성된 실리콘 기판(200) 표면에 게이트 산화막(12)을 성장시키고, 그 상단에 게이트 폴리실리콘막(13)을 증착한다.In the gate electrode forming process according to the present invention, first, the
여기서, 게이트 폴리실리콘막(13)은 10~5000Å의 두께와, 650℃이하의 증착온도를 갖는 것이 바람직하며, 저온 층착된 비정질 물질을 사용하는 것이 바람직하다.Here, the
다음으로, 게이트 폴리실리콘막(13) 위에 장벽금속막으로서 AlSixNy(14)막을 증착한다.Next, an AlSi x N y (14) film is deposited on the
또한, AlSixNy막은 ALD(Atomic Layer Deposition), CVD(Chemical vapor deposition), PVD(Physical vapor deposition) 및 PECVD(Plasma Enhanced Chemical Vapor Deposition) 방식으로 증착하며, ALD 방식은 소스 분사후 표면 흡착된 소스와 후속 질화막을 형성하기 위하여 분사 반응 소스는 NH3, N2, Ar등 환원 분위기를 이용한다. 막을 형성할 때 증착온도는 25~500℃범위를 갖는 것이 바람직하다.In addition, AlSi x N y film is deposited by ALD (Atomic Layer Deposition), CVD (Chemical Vapor Deposition), PVD (Physical Vapor Deposition) and PECVD (Plasma Enhanced Chemical Vapor Deposition) method. In order to form the source and the subsequent nitride film, the injection reaction source uses a reducing atmosphere such as NH 3 , N 2 , or Ar. When forming the film, the deposition temperature is preferably in the range of 25 ~ 500 ℃.
반응을 가속시키기 위해 플라즈마 에너지는 10~10kW의 파워범위를 갖는 것이 바람직하며, 0.1~50Torr의 압력 범위를 갖는 것이 바람직하다.In order to accelerate the reaction, the plasma energy preferably has a power range of 10 to 10 kW, and preferably has a pressure range of 0.1 to 50 Torr.
그리고, AlSixNy막은 1~100Å의 두께와 x의 범위는 0.1~5이고 y의 범위는 0.1~5를 조성비를 갖는 것이 바람직하다.The AlSi x N y film preferably has a thickness of 1 to 100 GPa and a range of x to 0.1 to 5, and a range of y to 0.1 to 5.
계속해서, 상기 AlSixNy(14) 위에 게이트 금속막(15)과 하드마스크 질화막(16)을 형성한다.Subsequently, a
게이트 금속막(15)은 W, Ir, Ru, Pt등을 사용하며, 두께 범위는 100~5000Å를 갖는 것이 바람직하다.The
계속해서, 게이트 하드마스크 질화막(16), 게이트 금속막(15), 장벽금속막인 AlSixNy(14), 게이트 폴리실리콘막(13), 게이트 산화막(12)을 게이트 전극 마스크를 사용하여 사진 및 식각 공정을 통해 게이트 전극을 형성한다Subsequently, the gate hard
AlSixNy막은 기존에 사용되던 WN막 보다 계면 특성 및 산화막과 트랩 사이트 유발 소스의 확산을 완벽하게 차단할 수 있으며, 전도성을 가지고 비정질(Amorphous)특성을 유지하고 있어서 결정립계면의 확산을 차단할 수 있다.
AlSi x N y film can completely block interfacial properties and diffusion of oxide and trap site-induced sources than WN film, which is used in the past. .
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.
The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.
이상에서 살펴본 바와 같이, 본 발명은 AlSixNy막을 적용하여 게이트 산화막의 신뢰성을 높이고 저전압 브레이크다운을 억제시켜 DRAM 소자의 안정한 게이트 모듈을 형성시키는 효과가 있다.As described above, the present invention has an effect of forming a stable gate module of a DRAM device by applying an AlSi x N y film to increase the reliability of the gate oxide film and to suppress the low voltage breakdown.
Claims (8)
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| KR1020040111992A KR20060073132A (en) | 2004-12-24 | 2004-12-24 | Gate electrode of semiconductor device and forming method thereof |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100772108B1 (en) * | 2006-06-30 | 2007-11-01 | 주식회사 하이닉스반도체 | Semiconductor device and method of manufacturing for the same |
| US20120156836A1 (en) * | 2009-06-26 | 2012-06-21 | Cornell University | Method for forming iii-v semiconductor structures including aluminum-silicon nitride passivation |
| KR101358854B1 (en) * | 2007-09-06 | 2014-02-06 | 삼성전자주식회사 | Semiconductor device and method for fabricating metal gate of the semiconductor device |
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2004
- 2004-12-24 KR KR1020040111992A patent/KR20060073132A/en not_active Application Discontinuation
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100772108B1 (en) * | 2006-06-30 | 2007-11-01 | 주식회사 하이닉스반도체 | Semiconductor device and method of manufacturing for the same |
| KR101358854B1 (en) * | 2007-09-06 | 2014-02-06 | 삼성전자주식회사 | Semiconductor device and method for fabricating metal gate of the semiconductor device |
| US20120156836A1 (en) * | 2009-06-26 | 2012-06-21 | Cornell University | Method for forming iii-v semiconductor structures including aluminum-silicon nitride passivation |
| US9991360B2 (en) * | 2009-06-26 | 2018-06-05 | Cornell University | Method for forming III-V semiconductor structures including aluminum-silicon nitride passivation |
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