KR20060072980A - Method for forming mos transistor - Google Patents

Abstract

The present invention discloses a method of forming a MOS transistor. A method of forming a MOS transistor according to the present disclosure includes: sequentially etching the first pad nitride layer and the first pad oxide layer to expose a gate region; Forming an oxide spacer on sidewalls of the etched first pad nitride layer and the first pad oxide layer; Forming a groove by first etching the exposed portion of the silicon substrate of the exposed gate region using the first pad nitride layer and the oxide spacer as a mask; Forming a first gate oxide layer on an entire surface of the substrate resultant; Forming a first polysilicon film in the groove including the first gate oxide film; Etching the first gate oxide layer and the oxide spacer using the first pad nitride layer as a mask, and forming a trench by second etching the silicon substrate; Forming a first LDD region in the trench surface; Forming a second gate oxide layer and a nitride spacer on the first LDD region; Depositing a second polysilicon film to fill a trench on the substrate resultant; Forming a recess gate by CMPing the second polysilicon layer to expose the pad nitride layer; Removing the pad nitride film; Forming a second LDD region in a surface of a substrate on both sides of a recess gate including the first LDD region; And forming a source / drain region in the substrate surface on both sides of the recess gate.

Description

Method for forming MOS transistor

1A to 1E are cross-sectional views illustrating processes for forming a conventional MOS transistor.

2A through 2E are cross-sectional views of processes for describing a MOS transistor forming method according to the present invention.

* Description of the symbols for the main parts of the drawings *

21: silicon substrate 22: first pad oxide film

23: first pad nitride film 24: oxide film spacer

26: first gate oxide film 27: first polysilicon film

28: first LDD region 29: second gate oxide film

31 nitride film spacer 32 second polysilicon film

33: second LDD region 35: source / drain region

The present invention relates to a method of forming a MOS transistor, and more particularly, to a method of forming a MOS transistor capable of reducing the parasitic resistance between a gate and a source / drain and improving a short channel effect.

A MOS transistor is a semiconductor device capable of forming a charge channel using an electric field generated by a gate voltage and controlling the flow of electric charge by a change in the gate voltage. Morse transistors are the mainstay of integrated circuits due to their low energy consumption, simple process, and small transistor size compared to bipolar transistors.

However, as the speed and speed of integration of semiconductor integrated circuits are accelerated, the channel length is also shortened, which is greatly affected by the short channel effect. The short channel effect refers to a phenomenon in which the length of the effective channel decreases due to the expansion of the depletion region near the drain as the drain voltage increases, which affects the magnitude of the threshold voltage, which is the gate voltage when the channel is formed. Makes control difficult. To reduce the effects of drain on short channels, shallow junctions between gate, drain and source are needed. However, such a shallow junction region has a problem in that the sheet resistance and the junction leakage current increase due to a decrease in the cross-sectional area through which current flows.

1A to 1D are cross-sectional views illustrating a conventional MOS transistor forming method.

Referring to FIG. 1A, a pad oxide film 2 and a pad nitride film 3 are formed on a semiconductor substrate 1, and then a mask (not shown) is formed on the resultant, and the pad nitride film 3 is formed using the pad oxide film 3. ) And the pad oxide film 2 are selectively etched to expose the gate region. Thereafter, a first nitride layer is deposited on the resultant, and a first nitride layer spacer 4 is formed on sidewalls of the etched pad nitride layer 3 and the pad oxide layer 2 through an etching process.

Referring to FIG. 1B, a field oxide film 5 is formed by performing a LOCOS process on the exposed gate region.

Referring to FIG. 1C, after forming the trench 6 by selectively removing the field oxide film 5 using the first nitride film spacer 4 as a mask, a threshold voltage control ion implantation process is performed.

Referring to FIG. 1D, after a thermal oxide film (not shown) is grown on the resultant product, a polysilicon film is embedded in the trench to form a recess gate electrode 7.

Referring to FIG. 1E, after the pad nitride layer 3 and the first nitride layer spacer 4 are removed, the second nitride layer spacer 8 is formed on both sidewalls of the gate electrode 7 and the field oxide layer 5. Then, the source / drain regions 9 are formed in the surface of the substrate on both sides of the recess gate 7 including the second nitride film spacer to complete the manufacture of the MOS transistor.

However, as described above, in the conventional recess gate structure in which the gate is formed in the trench of the active region, the thickness difference between the channel and the source / drain silicon film depends only on the loss of the silicon film due to the growth of the LOCOS oxide. Spike is easy to occur during contact formation of / drain junction, it is difficult to secure sufficient thickness of silicon film to reduce parasitic series resistance, and channel area is reduced due to bird's beak. There is.

In addition, since the gate-junction separation is performed only by the gate oxide layer, the parasitic capacitance between the gate and the source / drain junction increases by at least 50% more than that of a general transistor in the recessed gate structure fabricated on a conventional bulk substrate. RC delay time is increased during signal transmission, there is a problem that high speed operation is difficult.

In addition, the oxide layer at the gate edge is thin and thus the gate-induced-drain-leakage (GIDL) characteristics are weak, and a strong electric field is formed by the channel shape near the channel edge, thereby making the hot carrier characteristic weak.

Accordingly, an object of the present invention is to provide a MOS transistor forming method capable of reducing the parasitic resistance between the gate and the source / drain and improving the short channel effect.

In order to achieve the above object, the present invention comprises the steps of sequentially forming a first pad oxide film and a first pad nitride film on a silicon substrate; Sequentially etching the first pad nitride layer and the first pad oxide layer to expose a gate region; Forming an oxide spacer on sidewalls of the etched first pad nitride layer and the first pad oxide layer; Forming a groove by first etching the exposed portion of the silicon substrate of the exposed gate region using the first pad nitride layer and the oxide spacer as a mask; Forming a first gate oxide layer on an entire surface of the substrate resultant; Forming a first polysilicon film in the groove including the first gate oxide film; Etching the first gate oxide layer and the oxide spacer using the first pad nitride layer as a mask, and forming a trench by second etching the silicon substrate; Forming a first LDD region in the trench surface; Forming a second gate oxide layer and a nitride spacer on the first LDD region; Depositing a second polysilicon film to fill a trench on the substrate resultant; Forming a recess gate by CMPing the second polysilicon layer to expose the pad nitride layer; Removing the pad nitride film; Forming a second LDD region in a surface of a substrate on both sides of a recess gate including the first LDD region; And forming a source / drain region in the surface of the substrate on both sides of the recess gate.

After the step of forming the groove by primary etching the silicon substrate, and before the step of forming the first gate oxide film, further comprising the step of injecting a threshold voltage control ion into the substrate product.

The first pad oxide film may be formed to a thickness of 100 GPa or more, and the second pad oxide film may be formed to a thickness of 500 to 1000 GPa.

Preferably, the first pad nitride film is formed to a thickness of 1500 GPa or more, and the second pad nitride film is formed to a thickness of 300 to 500 GPa.

The first gate oxide film may be formed to a thickness of 20 to 50 GPa, and the second gate oxide film may be formed to a thickness of 100 to 200 GPa.

It is preferable that the primary etching of the silicon substrate etch a thickness of 1000 to 1500 kPa, and the secondary etching etch a thickness of 300 to 500 kPa.                     

The first polysilicon is formed to a thickness of 500 to 1000 kPa, and the second polysilicon is formed to a thickness of 500 to 1500 kPa.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2A through 2F are cross-sectional views illustrating a method of forming a gate of a semiconductor device in accordance with an embodiment of the present invention.

Referring to FIG. 2A, the first pad oxide layer 22 and the first pad nitride layer 23 are sequentially deposited on the silicon substrate 21, and then a mask (not shown) is used to expose a region where a gate is to be formed. The first pad nitride layer 23 and the first pad oxide layer 22 may be selectively etched to form the first pad nitride layer 23. Thereafter, a second pad oxide film is deposited on the entire surface of the etched first pad nitride film 23 and the first pad oxide film 22 and then etched to form a first pad nitride film 23 and a first pad oxide film 22. The oxide film spacers 24 are formed on the sidewalls of the substrate. Here, the first pad oxide film 22 is deposited to a thickness of about 100 GPa, and the first pad nitride film 23 is deposited to a thickness of about 1500 GPa. In addition, the second pad oxide film is deposited to a thickness of about 500 to 1000 Å so as to obtain a desired gate length.

Referring to FIG. 2B, a groove 25 is formed by first etching a portion of the silicon substrate 21 of the exposed gate region using the first pad nitride layer 23 and the oxide spacer 24 as a mask. At this time, the primary etching of the silicon substrate 21 is preferably etched by a thickness of 1000 to 1500Å. As a result, the step of the silicon film between the gate and the source / drain region to be formed subsequently becomes 100 to 1500 mW, and the channel region and the source / drain region are almost in line with each other, thereby reducing the parasitic series resistance between the gate and the source / drain region. You can do it.

Then, a threshold voltage regulation ion is implanted on the front surface of the substrate. By implanting the threshold voltage regulation ion after the primary etching of the silicon substrate 21, the impurity concentration distribution is increased only in the channel region and the concentration near the junction is kept low, thereby improving the short channel effect.

Referring to FIG. 2C, the substrate resultant is heat-treated to form a first gate oxide layer 26 having a thickness of 20 to 50 GPa on the entire surface of the silicon substrate. At this time, by growing the first gate oxide layer 26 by the oxide spacer 24, the shape of the channel region is rounded to improve the corner effect where the electric field is concentrated.

Referring to FIG. 2D, a first polysilicon film 27 is deposited to a thickness of 500 to 1000 로 on the entire surface of the substrate resultant. Then, the first polysilicon film 27 is etched back so as to remain only in the groove including the first gate oxide film.

Referring to FIG. 2E, the first gate nitride film 23 is used as a mask, the first gate oxide film and the oxide film spacer 24 are etched, and the silicon substrate 21 is etched secondly to form the trench 30. Form. At this time, the secondary etching of the silicon substrate 21 is preferably performed to a depth of 300 to 500Å. Here, after the silicon substrate is primarily etched using the above-described oxide film spacer, it is easy to adjust the length of the gate by removing the oxide film spacer and secondly etching the silicon substrate.                     

Next, ions are implanted into the exposed silicon substrate at an angle of 10 to 20 degrees to form the first LDD region 28 in the trench 30 surface. The first LDD region 28 is formed to increase the junction concentration of undoped portions during subsequent second LDD ion implantation and source / drain ion implantation, thereby improving driving current of the transistor and increasing gate induced drain (GIDL). Leakage) has the effect of reducing.

Referring to FIG. 2F, a second gate oxide layer 29 is formed on the substrate resultant. In this case, the second gate oxide film 29 is formed to a thickness of 100 to 200 Å thicker than the first gate oxide film 26.

Referring to FIG. 2G, a second pad nitride layer is deposited on the second gate oxide layer 29 to a thickness of 300 to 500 Å. Thereafter, the second pad nitride layer is etched to form the nitride spacer 31 on the first LDD region 28. When the second pad nitride layer is etched, a portion of the second gate oxide layer on the first polysilicon layer 27 is removed to expose the first polysilicon layer 27. By forming the second gate oxide film and the nitride film spacer 31 in the gate, parasitic resistance existing between the gate and the source / drain regions may be reduced.

Referring to FIG. 2H, the second polysilicon 32 is deposited to a thickness of 500 to 1500 Å to fill the trench on the substrate resultant, and then CMP to form a recess gate. Thereafter, wet etching is performed to remove the first pad nitride layer over the first pad oxide layer 22. Next, ions are implanted at an angle of 20 to 45 degrees to form a second LDD region 33 in the substrate surface on both sides of the recess gate including the first LDD region.                     

Referring to FIG. 2I, ion implantation is performed in the substrate surfaces on both sides of the recess gate to form a source / drain region 35 to complete formation of a MOS transistor. Since the source / drain regions 35 were formed after the first and second LDD regions were formed by two ion implantations, the change in the impurity concentration was moderate, and the short channel effect was improved, and the electric field strength at the junction was improved. There is an effect that the reduced hot carrier characteristics are improved.

As described above, the present invention can reduce the parasitic resistance between the gate and the source / drain by etching the silicon substrate over the secondary to form the recess gate, thereby preventing the spiking phenomenon in the subsequent contact forming process.

In addition, when the gate oxide film grows, the oxide film thickness of the edge portion of the gate electrode becomes thick, so that an electric field near the gate edge overlapping the drain region is reduced, thereby reducing leakage current by the gate electric field.

After implanting LDD ions twice at large inclination angles, source / drain regions are formed to slowly change the impurity concentration at the source / drain junction, thereby reducing the electric field strength at the junction, thereby reducing the short channel effect and hot carrier. Properties can be improved.

Therefore, the present invention can ensure the reliability of the MOS transistor itself, as well as improve the reliability and manufacturing yield of the semiconductor device.

While the invention has been shown and described with respect to certain preferred embodiments thereof, the invention is not so limited, and the invention is not limited to the spirit and scope of the invention as defined by the following claims. It will be readily apparent to one of ordinary skill in the art that various modifications and variations can be made.

Claims (7)

Sequentially forming a first pad oxide film and a first pad nitride film on the silicon substrate; Sequentially etching the first pad nitride layer and the first pad oxide layer to expose a gate region; Forming an oxide spacer on sidewalls of the etched first pad nitride layer and the first pad oxide layer; Forming a groove by first etching the exposed portion of the silicon substrate of the exposed gate region using the first pad nitride layer and the oxide spacer as a mask; Forming a first gate oxide layer on an entire surface of the substrate resultant; Forming a first polysilicon film in the groove including the first gate oxide film; Etching the first gate oxide layer and the oxide spacer using the first pad nitride layer as a mask, and forming a trench by second etching the silicon substrate; Forming a first LDD region in the trench surface; Forming a second gate oxide layer and a nitride spacer on the first LDD region; Depositing a second polysilicon film to fill a trench on the substrate resultant; Forming a recess gate by CMPing the second polysilicon layer to expose the pad nitride layer; Removing the pad nitride film; Forming a second LDD region in a surface of a substrate on both sides of a recess gate including the first LDD region; And Forming a source / drain region in the substrate surface on both sides of the recess gate. The method of claim 1, Fabricating a MOS transistor after the etching of the silicon substrate to form a groove and before the forming of the first gate oxide layer, implanting a threshold voltage control ion into the substrate resultant. Way. The method of claim 1, And the first pad oxide film is formed to a thickness of 100 GPa or more, and the second pad oxide film is formed to a thickness of 500 to 1000 GPa. The method of claim 1, And the first pad nitride film is formed to a thickness of 1500 kPa or more, and the second pad nitride film is formed to a thickness of 300 to 500 kPa. The method of claim 1, Wherein the first gate oxide film is formed to a thickness of 20 to 50 kV, and the second gate oxide film is formed to a thickness of 100 to 200 kV. The method of claim 1, The method of claim 1, wherein the primary etching of the silicon substrate to etch a thickness of 1000 to 1500Å, the secondary etching to a thickness of 300 to 500Å. The method of claim 1, Wherein the first polysilicon is formed to a thickness of 500 to 1000 kPa, and the second polysilicon is formed to a thickness of 500 to 1500 kPa.

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