KR20060067443A - Method for forming isolation of semiconductor device - Google Patents

Abstract

The present invention relates to a method of forming a device isolation film of a semiconductor device capable of preventing the generation of moats. A device isolation film forming method of a semiconductor device according to the present invention includes forming a pad oxide film on a semiconductor substrate; Forming a high temperature oxide film (HTO) on the pad oxide film; Forming a pad nitride film on the high temperature oxide film; Etching the pad nitride film, the high temperature oxide film, the pad oxide film, and the substrate to form a trench; Filling the trench with a buried insulating film; CMPing the buried insulating film to expose the pad nitride film: removing the pad nitride film; And removing the buried insulating film portion disposed higher than the active region while removing the high temperature oxide film and the pad oxide film.

Description

Method for forming isolation of semiconductor device

1 is a cross-sectional view illustrating a problem in forming a device isolation film of a semiconductor device according to the prior art.

2A to 2D are cross-sectional views illustrating a method of forming a device isolation film of a semiconductor device in accordance with an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

20: substrate 21: pad oxide film

22: high temperature oxide film 23: pad nitride film

24: trench 25: buried insulation film

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a device isolation film of a semiconductor device capable of preventing generation of moats.

With the advance of semiconductor technology, the speed and the high integration of semiconductor elements are progressing rapidly, and with this, the demand for refinement | miniaturization of a pattern and high precision of a pattern dimension is increasing. This requirement applies not only to patterns formed in device regions, but also to device isolation films that occupy a relatively large area. That is, since the width of the device region is decreasing toward the higher integration device, it is necessary to decrease the width of the device isolation region in order to relatively increase the width of the device region.

Currently, most semiconductor devices form a device isolation layer using a shallow trench isolation (STI) process having a small width and excellent device isolation characteristics.

The conventional device isolation film forming method using the STI technology will be briefly described as follows.

After the pad oxide film and the pad nitride film are sequentially formed on the silicon substrate, the pad nitride film is etched according to a known lithography process, and then the pad nitride film is removed to etch the exposed pad oxide film portion and the lower silicon substrate portion. Form a trench. Then, the oxide film is CMP while the oxide film is deposited so as to completely fill the trench, and then the pad nitride film is removed to form a trench type device isolation film.

However, after the pad nitride film is removed after the oxide film CMP in the device isolation film forming process of the 100 nm or less device, as shown in FIG. 1, an excessive etching of the oxide film 15 occurs at the interface between the active and device isolation films. . This is called the moat 15a. Reference numeral 10 denotes a substrate, 16 gate oxide film, and 17 polysilicon.

The generation of the mote 15a adversely affects the electrical characteristics of the device. That is, as polysilicon is deposited in the moat 15a in the gate poly 17 deposition process, a poly wrap-around occurs to leak current of a MOSFET acting in a subthreshold region. And increase Reverse-Narrow-Width-Effect. In addition, as the depth of the moat 15a increases, the threshold voltage decreases and the electrical field width of the MOSFET decreases.

As the mote 15a becomes smaller as the device becomes smaller, the area occupied by the MOSFET is relatively increased, which causes great difficulty in device development.

Therefore, the present invention has been made to solve the problems of the prior art, an object of the present invention is to form a device isolation film of a semiconductor device capable of preventing the occurrence of moat in the boundary region between the active region and device isolation In providing a method.

In addition, another object of the present invention is to provide a method of forming a device isolation film of a semiconductor device that can improve the device characteristics by preventing the occurrence of moat.

Method for forming a device isolation film of a semiconductor device according to the present invention for achieving the above object comprises the steps of forming a pad oxide film on a semiconductor substrate; Forming a high temperature oxide film (HTO) on the pad oxide film; Forming a pad nitride film on the high temperature oxide film; Etching the pad nitride film, the high temperature oxide film, the pad oxide film, and the substrate to form a trench; Filling the trench with a buried insulating film; CMPing the buried insulating film to expose the pad nitride film: removing the pad nitride film; And removing the buried insulating film portion disposed higher than the active region while removing the high temperature oxide film and the pad oxide film.

The pad oxide film and the HTO film were deposited to a thickness of 100 to 150 GPa and 300 to 400 GPa, respectively.

The HTO film is deposited using a flow rate of dichlorosilane (SiH 2 Cl 2) at 9 to 11 cc and a flow rate of N 2 O at a temperature of 800 to 850 ° C. and a pressure of 0.1 to 0.3 Torr.

After deposition of the HTO film, annealing is performed for 30 minutes or more at a nitrogen atmosphere and a temperature of 1000 to 1100 ° C.

The pad nitride film is deposited to a thickness of 100 to 150 GPa.

Forming the trench by etching the pad nitride film, the high temperature oxide film, the pad oxide film, and the substrate is performed using any one gas selected from the group consisting of CxFy-based gas, CxFyHz-based gas, NF3, SF6, and CF3Cl gas. .

The etching is performed by adding H2 or O2 gas to the stock angle gas.

The step of filling the trench with a buried insulating film is performed as a SiO 2 film using a high density chemical vapor deposition (HDP-CVD) method.

The CMP of the buried insulating film is primarily performed by using only a silica slurry to reduce the step difference generated when forming the buried insulating film to 500 mW or less and secondly to prevent dishing by using a high selectivity slurry for oxide CMP.                     

The step of removing the high temperature oxide film and the pad oxide film and the portion of the buried insulating film disposed higher than the active region is performed using a 50: 1 HF solution, a 300: 1 BOE solution, and a mixed solution thereof.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2A through 2D are cross-sectional views illustrating a method of forming a device isolation film of a semiconductor device in accordance with an embodiment of the present invention.

Referring to FIG. 2A, the pad oxide film 21 is formed on the semiconductor substrate 20 to have a thickness of 100 to 150 Å. Subsequently, a high temperature oxide film (HTO) 22 is deposited on the pad oxide film 21 at a thickness of 300 to 400 kPa. The high temperature oxide film 22 is deposited at a temperature of 800 to 850 ° C. and a pressure of 0.1 to 0.3 Torr with a flow rate of dichlorosilane (SiH 2 Cl 2) of 9 to 11 cc and a flow rate of N 2 O of 90 to 110 cc. After the deposition of the high temperature oxide film 22, annealing is performed for 30 minutes or more at a nitrogen atmosphere and a temperature of 1000 to 1100 ° C. to improve the deposition uniformity. Subsequently, a pad nitride film 23 is deposited on the high temperature oxide film 22 to a thickness of 100 to 150 kPa.

Then, after etching the pad nitride layer 23 according to a known lithography process, the pad nitride layer 23 is removed to expose the exposed high temperature oxide layer 22, the pad oxide layer 21, and the substrate 20 thereunder. The portion is etched to form the trench 24. At this time, etching is performed using a CxFy-based gas, a CxFyHz-based gas, NF3, SF6, or CF3Cl gas, and H2 or O2 gas may be added to the stock gas.                     

Referring to FIG. 2B, the trench 24 is filled with a buried insulating film 25. At this time, as the buried insulating film 25, an HDP-CVD oxide film having excellent trench filling characteristics is used.

Referring to FIG. 2C, the buried insulating film 25 is CMP to expose the pad nitride film. In this case, the buried insulating film 25 CMP is first used only a low slurry slurry for the oxide CMP, the silica slurry is lowered to less than 500Å step to form a buried insulating film, then secondly using a high selectivity slurry for the oxide film CMP Do not cause dishing. Then, the pad nitride film is removed.

Referring to FIG. 2D, a device isolation film is formed by removing the high temperature oxide film 22 and the pad oxide film 21 and simultaneously removing a portion of the buried insulating film 25 disposed higher than the active region. At this time, the membranes are removed using a 50: 1 HF solution, a 300: 1 BOE solution, and a mixed solution thereof.

Thereafter, the gate oxide layer 26 and the gate poly 27 are formed and patterned to form a gate. Here, no moat is generated, so that device characteristics can be improved.

Table 1 is a table comparing wet etching rates of three kinds of oxide films according to etchant.

Table 1

(Å / sec) 50: 1 HF 300: 1 BOE Remarks Thermal oxide One 0.27 Used as pad oxide High temperature oxide film 1.25 0.32 30 minutes annealing at 1050 ℃ HDP oxide 1.28 0.34 30 minutes annealing at 1050 ℃

Here, since the etching rate of the high temperature oxide film is larger than the etching rate of the pad oxide film and smaller than that of the HDP oxide film, the high temperature oxide film and the HDP oxide film on the active layer can be simultaneously etched. Accordingly, excessive etching of the HDP oxide film can be suppressed to prevent the occurrence of moats.

At this time, since both the high temperature oxide film and the pad oxide film are to be removed while all the HDP-CVD oxide films disposed higher than the active are removed, the thickness of the pad nitride film, the high temperature oxide film and the pad oxide film should be appropriately adjusted according to the type of etchant to be used.

As described above, according to the present invention, by depositing a high temperature oxide film between the pad oxide film and the pad nitride film, excessive etching of the HDP oxide film can be suppressed to prevent the occurrence of moat at the edge of the device isolation film. In addition, by preventing the occurrence of the moat, it is possible to improve the device isolation characteristics to ensure excellent device characteristics.

While the present invention has been illustrated and described with reference to certain preferred embodiments, the invention is not limited thereto, and the invention is not limited to the spirit or field of the invention as defined by the following claims. It will be readily apparent to one of ordinary skill in the art that various modifications and variations can be made.

Claims (10)

Forming a pad oxide film on the semiconductor substrate; Forming a high temperature oxide film (HTO) on the pad oxide film; Forming a pad nitride film on the high temperature oxide film; Etching the pad nitride film, the high temperature oxide film, the pad oxide film, and the substrate to form a trench; Filling the trench with a buried insulating film; CMPing the buried insulating film to expose the pad nitride film: Removing the pad nitride film; Removing the high temperature oxide film and the pad oxide film and simultaneously removing a portion of the buried insulating film disposed higher than an active region. The method of claim 1, Wherein the pad oxide film and the HTO film are deposited to a thickness of 100 to 150 GPa and 300 to 400 GPa, respectively. The method of claim 2, The HTO film is formed by depositing dichlorosilane (SiH 2 Cl 2) at a temperature of 800 to 850 ° C. and a pressure of 0.1 to 0.3 Torr using a flow rate of 9 to 11 cc and a flow rate of N 2 O to 90 to 110 cc. Way. The method of claim 3, wherein And annealing at least 30 minutes at a nitrogen atmosphere and at a temperature of 1000 to 1100 ° C. after the deposition of the HTO film. The method of claim 1, Wherein the pad nitride film is deposited to a thickness of 100 to 150 kHz. The method of claim 1, Forming the trench by etching the pad nitride film, the high temperature oxide film, the pad oxide film and the substrate is performed using any one gas selected from the group consisting of CxFy-based gas, CxFyHz-based gas, NF3, SF6 and CF3Cl gas. A device isolation film forming method of a semiconductor device, characterized in that. The method of claim 6, The etching is performed by adding H 2 or O 2 gas to the stock angle gas. The method of claim 1, The method of forming a device isolation film of a semiconductor device according to claim 1, wherein the filling of the trench with a buried insulating film is performed with a SiO 2 film using a high density chemical vapor deposition (HDP-CVD) method. The method of claim 1, The CMP of the buried insulating film may be performed by using only a silica slurry as the first step to lower the level difference generated when the buried insulating film is formed to 500 Å or less, and then secondly to prevent dishing using a high selectivity slurry for oxide CMP. A device isolation film forming method of a semiconductor device. The method of claim 1, The removing of the high temperature oxide film and the pad oxide film and simultaneously removing the portion of the buried insulating film disposed higher than the active region is performed using a 50: 1 HF solution, a 300: 1 BOE solution, and a mixed solution thereof. Device isolation film formation method of the device.

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