KR20060064149A - Method of programming a nand type flash memory device - Google Patents

Abstract

The present invention relates to a method of programming a NAND type flash memory device, and in particular, a plurality of memory cells are connected in series, and the memory cells connected in series share a drain and a source through a drain select transistor and a source select transistor. A cell configured to be electrically connected to the drain select transistor and electrically located far from the page buffer of the NAND type flash memory device including a page buffer configured to sense the state of the cell; Program the NAND-type flash memory device that can sense the correct cell state by prolonging the voltage application time and secure the threshold voltage margin of the flash memory cell to improve sensing speed or develop multilevel cells. The method is presented.

NAND flash, program, program voltage application time

Description

Method of programming a NAND type flash memory device             

1 is a cell string configuration diagram of a typical NAND type flash memory device.

FIG. 2 is a diagram illustrating cell threshold voltage variation by a program method of a general NAND type flash memory device.

3 (a) and 3 (b) are program bias timing diagrams and threshold voltage distribution diagrams of the conventional NAND type flash memory device.

4 (a) and 4 (b) are program bias timing diagrams and threshold voltage distribution diagrams of the NAND type flash memory device according to the present invention.

The present invention relates to a method of programming a NAND type flash memory device, and in particular, by increasing the program voltage application time of a cell located far from the sensing node from a cell located close to the sensing node, the cell can secure a threshold voltage margin. The present invention relates to a method of programming a NAND type flash memory device.

There is an increasing demand for semiconductor memory devices that can be electrically programmed and erased and that do not require a refresh function that rewrites data at regular intervals. In order to develop a large-capacity memory device capable of storing a large amount of data, research on high integration technology of memory devices has been actively conducted. Here, the program refers to an operation of writing data to a memory cell, and the erasing refers to an operation of removing data written to the memory cell.

As shown in FIG. 1, a plurality of memory cells M0 to Mx (where x = 2 ⁿ and n are natural numbers) are connected in series and have a drain select transistor between adjacent cells. NAND-type flash memory devices have been developed in which a drain and a source are shared with each other through N1) and a source select transistor N2 to form a string. Here, a plurality of cells of different strings sharing one word line WL0 to WLx constitute one page, the drain select transistor N1 is driven by the drain select line DSL, and the source select transistor. N2 is driven by the source select line SSL. Unlike NOR-type flash memory devices, NAND-type flash memory devices are memory devices that read information sequentially. The program and erase of the NAND type flash memory device is performed by controlling the threshold voltage of the memory cell while injecting or emitting electrons into the floating gate using an FN tunneling method.

A NAND type flash memory device uses a page buffer to store a large amount of information or to read stored information in a short time. The page buffer receives a large amount of data from an input / output pad and provides the memory cells or stores and outputs data of the memory cells. The page buffer is connected to the drain select transistor to serve as a sensing node SEN for sensing a state of a cell.

In the NAND type flash memory device configured as described above, the threshold voltage is shifted as shown in FIG. 2 by a program. In the conventional program method, all word lines WL0 to WLx are shown in FIG. As described above, all cells M0 to Mx are programmed by applying a program voltage under the same condition of applying the same voltage for the same time, thereby obtaining the threshold voltage distribution of FIG. However, the threshold voltage distribution sensed by the sensing node SEN is slightly different depending on the position of the cell in each string. That is, the threshold voltage of the cell far from the sensing node SEN is always detected lower than the threshold voltage of the cell close to the sensing node SEN. Therefore, it is difficult to sense the exact state of the cell according to the position of the cell from the sensing node SEN.

 An object of the present invention is to provide a method of programming a NAND type flash memory device capable of accurately sensing the state of a cell by varying the threshold voltage of the program cell according to the position from the sensing node.

It is another object of the present invention to reduce the program voltage application time as the cell located closer to the sensing node based on the program voltage application time of the cell located farthest from the sensing node, thereby to distribute the threshold voltage of the program cell to a position from the sensing node. The present invention provides a method of programming a NAND type flash memory device.

According to an exemplary embodiment of the present invention, a program method of a NAND type flash memory device includes a plurality of memory cells connected in series, and memory cells connected in series share a drain and a source through a drain select transistor and a source select transistor. A method of programming a NAND type flash memory device comprising a string configured to form one string and connected to the drain select transistor to sense a state of the cell, wherein a cell located farther from the page buffer is a word of a cell. The program is executed by lengthening the application time of the program voltage applied through the line.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

4 (a) and 4 (b) are program bias timing diagrams and threshold voltage distribution diagrams of the NAND type flash memory device according to an exemplary embodiment of the present invention.

As shown in FIG. 4 (a), the same program voltage is applied for different times to program a cell. The program is executed for t2-t1 = ΔtR0 at the word line WLx of the sensing node, that is, the cell located farthest from the page buffer. If a voltage is applied, a program voltage is applied to the word line WLx-1 of the cell closer to the sensing node than the word line WLx of the cell for t2'-t1 = ΔtR1, and the word line WLx-1 of the cell. The program voltage is applied to the word line WLx-2 of the cell closer to the sensing node for t2 "-t1 = ΔtR2, and the program voltage is applied to the word line WL0 of the cell closest to the sensing node for ΔtRx. At this time, ΔtR0> ΔtR1> ΔtR2>…> ΔtRx, that is, the shorter the program voltage application time of the cell is, the closer it is located from the sensing node based on the program voltage application time of the cell located farthest from the sensing node. Doing so the threshold voltage of each cell detected by the sensing node is visible to a closer distribution as shown in Figure 4 (b).

On the other hand, in order to apply the program bias of different times according to the word line as described above, it can be easily implemented using a timing decoder that outputs a variable time according to the word line number.

 As described above, according to the present invention, the closer the distance from the sensing node to the program voltage application time of the cell located farthest from the sensing node, the shorter the program voltage application time of the cell can sense the correct state of the cell, and the flash By securing the threshold voltage margin of the memory cell, it can be used to improve sensing speed or develop multilevel cells.

Claims (2)

A plurality of memory cells are connected in series, the memory cells connected in series share a drain and a source through a drain select transistor and a source select transistor to form a string, and are connected to the drain select transistor to form a string. In the method of programming a NAND-type flash memory device including a page buffer for sensing a state, A program method of a NAND flash memory device for performing a program by varying the program voltage application time applied through a word line according to the position of the cell. The method of claim 1, wherein the program is performed by increasing an application time of a program voltage applied through a word line of a cell as the cell is located farther from the page buffer.

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