KR20060063217A - Semiconductor memory device - Google Patents

Abstract

SUMMARY OF THE INVENTION The present invention provides a semiconductor memory device capable of shortening the precharge time while having a small area. The present invention provides a plurality of unit memory cells that store data and are accessed through word lines and bit lines. A unit memory cell array block; A bit line detection amplifier block comprising a plurality of bit line detection amplifiers for sensing and amplifying data of the unit memory cells, and shared by neighboring unit memory cell array blocks; Bit line separation signal generating means for generating a bit line separation signal in response to a unit memory cell selection signal activated upon access; Bit line separation means for allowing only one unit memory cell array block to occupy the bit line sense amplifier block in response to the bit line separation signal; And precharge auxiliary means for connecting the lines to which the bit line separation signal is applied in the bit line separation unit positioned above and below the bit line sense amplifier block.

Charge, sharing, size, precharge, tRP

Description

Semiconductor Memory Device {SEMICONDUCTOR MEMORY DEVICE}             

1 is a block diagram of a semiconductor memory device according to the prior art.

FIG. 2 is an internal circuit diagram of a bit line separation signal generator of FIG. 1. FIG.

3 is a block diagram illustrating a semiconductor memory device in accordance with an embodiment of the present invention.

FIG. 4 is an internal circuit diagram of the precharge control signal generator of FIG. 3. FIG.

5 is an operational waveform diagram of FIG. 3 according to unit memory cell access.

FIG. 6 is another operational waveform diagram of FIG. 3 in accordance with unit memory cell access. FIG.

* Explanation of symbols for the main parts of the drawings

100: precharge auxiliary unit

120: switching unit

140: precharge control signal generation unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor design technology, and more particularly, to a semiconductor memory device having a short precharge time and a driving method thereof.

As the operation speed of semiconductor memory devices is increased, the demand for speeding up data input / output increases.

Various methods have been developed to speed up data input and output, and one of them is to rapidly develop and precharge data pairs.

In other words, the data input / output speed is determined by the sum of the time for developing the data input / output line pair and the time for precharging the data input / output line pair.

Therefore, reducing the precharge time for the data input / output line pairs improves the data input / output speed.

1 is a block diagram of a semiconductor memory device according to the prior art.

As shown in the drawing, a semiconductor memory device according to the related art stores data and includes a plurality of unit memory cells array blocks 10 and 20 that store data and are accessed through word lines WL and bit lines BL. , 30, 40) and a plurality of bit line sense amplifiers (S / A, Sense Amplifier) for sensing and amplifying data of the unit memory cells, which are shared by neighboring unit memory cell array blocks. And sense amplifier blocks 50, 60, 70.

As described above, since the semiconductor memory device shares the bit line sense amplifier blocks 50, 60, and 70 by the unit memory cell array blocks 10, 20, 30, and 40 located above and below each other, Bit line separators 52, 54, 62, 64, 72, and 74 are provided for each bit line sense amplifier block 50, 60, 70 and unit so that only the unit memory cell array block occupies the bit line sense amplifier block. It is disposed between the memory cell array blocks 10, 20, 30, and 40.

Since the first to third bit line sense amplifier blocks 50, 60 and 70 have the same circuit implementation, the first bit line sense amplifier block 50 will be described in detail as an example.

The first bit line sense amplifier block 50 includes a pair of bit lines BL0 / BL0b, BL2 / BL2b, connected to each unit memory cell in odd-numbered positions of the first and second unit memory cell array blocks 10 and 20. And a plurality of bit line sense amplifiers 50a and 50b, which are all connected to ...).

The bit line separators 52 and 54 determine whether the bit line sense amplifiers are connected to each other through the switches implemented as NMOS transistors above and below each of the bit line sense amplifiers 50a and 50b.

That is, the gates of the NMOS transistors in the same bit line separation sections 52, 54, 62, 64, 72, and 74 are connected to the same line, so that the common bit line separation signals BISH0, BISL0, BISH1, BISL1, BISH2, and BISL2 are connected. Are driven at the same time.

Since the bit line separation signals BISH0, BISL0, BISH1, BISL1, BISH2, and BISL2 are generated by the bit line separation signal generators 52a, 54a, 62a, 64a, 72a, and 74a, the following description will be made with reference to the drawings. Let's take a look.                         

FIG. 2 is an internal circuit diagram of the bit line separation signal generators 52a, 54a, 62a, 64a, 72a, and 74a of FIG. 1.

As shown in the figure, since the first bit line separation signal generator 52a includes three inverters connected in series, the first bit line separation signal generator 52a inverts the logic level of the input unit memory cell selection signal cell_mat_slt0 and outputs the bit line separation signal BISH0. .

 The second to sixth bit line split signal generators 54a, 62a, 64a, 72a, and 74a also have the same circuit implementation as the first bit line split signal generator 52a as described above, and each of the corresponding unit memories. The point of receiving the cell selection signals cell_mat_slt1, cell_mat_slt0, cell_mat_slt2, and cell_mat_slt3 is different.

Briefly referring to the operation, the bit line separation signal generators 52a, 54a, 62a, 64a, 72a, and 74a may use the corresponding bit line separation signal BISH when the unit memory cell selection signal cell_mat_slt is deactivated to a logic level 'L'. , BISL is activated at the power supply voltage VPP level, and is output when the unit memory cell selection signal cell_mat_slt is activated, and deactivates the corresponding bit line separation signals BISH and BISL to the power supply voltage VSS level.

Accordingly, since all unit memory cell selection signals cell_mat_slt are deactivated in the standby state in which there is no substantial operation in the semiconductor memory device, the bit line separation signal generators 52a, 54a, 62a, 64a, 72a, and 74a respond in response thereto. Activate all bit line separation signals (BISH, BISL). That is, in the standby state, the bit line sense amplifier blocks 50, 60, and 70 are shared by adjacent unit memory cell array blocks 10, 20, 30, and 40.                         

In addition, in the active state where the command is applied, the bit line separation signal generators 52a, 54a, 62a, 64a, 72a, and 74a deactivate the corresponding bit line separation signal in response to the activation of the activated unit memory cell selection signal. .

In this case, the first and fourth bit line separation signal generators 52a and 64a and the third and sixth bit line separation signal generators 62a and 74a receive the same unit memory cell selection signals cell_mat_slt1 and cell_mat_slt2, respectively. Therefore, the bit line separation signal has the same logic level depending on whether the unit memory cell selection signal is applied together.

Thus, only the selected unit memory cell array block monopolizes the bit line sense amplifier blocks located above and below it.

For example, when the selected word line WL is located in the second unit memory cell array block 20, the bit line separation signal generators 52a and 64a respond to the bit line selection signal cell_mat_slt1. By deactivating the separation signals BISH0 and BISL1, only the second unit memory cell array block 20 occupies the first and second bit line sense amplifier blocks 50 and 60 located above and below it.

Meanwhile, the inverter in the bit line separation signal generator as described above is supplied with the power supply voltage VPP and the power supply voltage VSS as driving power, and supplies an amount of current required according to the loading of the line to which the bit line separation signal is applied.

However, since the time required to apply the precharge command to precharge the bit line separation signal from the logic level 'L' to 'H' has a decisive effect on satisfying the tRP (low precharge time) of the semiconductor memory device, Efforts have been made to reduce the precharge time of the bit line isolation signal to reduce the tRP of the device.

That is, by increasing the area of the inverter to increase the driving force of the inverter, the precharge time of the bit line separation signal is reduced.

Therefore, the semiconductor memory device according to the prior art takes an increase in the area of the device in order to satisfy the precharge time according to the specification.

In addition, the semiconductor memory device has an additional problem of increased power consumption due to an increase in area.

The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a semiconductor memory device capable of shortening the precharge time while having a small area.

In the semiconductor memory device according to an aspect of the present invention for achieving the above technical problem is a semiconductor memory device having a form in which adjacent unit memory cell array blocks share a bit line detection amplifier block located between them, First and second bit line separators to allow only one of the adjacent unit memory cell array blocks to occupy the bit line sense amplifier block when active; And a precharge auxiliary unit for connecting the metal lines to which the control signals for controlling the first and second bit line separation units are applied to each other when precharging.

According to another aspect of the present invention, a semiconductor memory device may include: a unit memory cell array block configured to include a plurality of unit memory cells that store data and are accessed through word lines and bit lines; A bit line detection amplifier block comprising a plurality of bit line detection amplifiers for sensing and amplifying data of the unit memory cells, and shared by neighboring unit memory cell array blocks; Bit line separation signal generating means for generating a bit line separation signal in response to a unit memory cell selection signal activated upon access; Bit line separation means for allowing only one unit memory cell array block to occupy the bit line sense amplifier block in response to the bit line separation signal; And precharge auxiliary means for connecting the lines to which the bit line separation signal is applied in the bit line separation unit located above and below the bit line detection amplifier block.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

3 is a block diagram illustrating a semiconductor memory device in accordance with an embodiment of the present invention.

Referring to FIG. 3, a semiconductor memory device according to an embodiment of the inventive concept may include a unit memory cell array block configured to store data and include a plurality of unit memory cells accessed through a word line WL and a bit line BL. (10, 20, 30, 40) and a plurality of bit line detection amplifiers (S / A) for sensing and amplifying data of the unit memory cells, which are shared by neighboring unit memory cell array blocks. The bit line separation signal generator 52a for generating the bit line separation signals BISH and BISL in response to the line sense amplifier blocks 50, 60, and 70 and the unit memory cell selection signal cell_mat_slt activated upon access. 54a, 62a, 64a, 72a, and 74a and the bit line separation unit 52 so that only one unit memory cell array block occupies the bit line detection amplifier block in response to the bit line separation signals BISH and BISL. 54, 62, 64, 72, 74), and pricha When the bit line sense amplifier block because of a bit line separation unit in the bit line to which the separate signal line located at the upper and lower connection to each other, and a precharge auxiliary (100) for sharing to take.

The precharge auxiliary unit 100 may include a precharge control signal generator 140 for generating a precharge control signal pcg_ctr activated in the precharge period, and a bit line detection amplifier in response to the precharge control signal pcg_ctr. And a switching unit 120 for connecting the lines to which the bit line separation signals are applied in the bit line separation units located above and below the block, respectively.

In addition, the switching unit 120 has a precharge control signal pcg_ctr as a gate input and is located above and below one bit line detection amplifier block to drain between each line receiving the bit line separation signals BISH and BISL. A plurality of NMOS transistors having a source path are provided.                     

As described above, the semiconductor memory device according to the present invention connects lines to which adjacent bit line separation signals are applied during precharging, thereby shortening the precharge time through charge sharing generated between the lines.

In addition, since the voltage level of the line deactivated by the charge sharing rises quickly, the area of the bit line separation signal generators 52a, 54a, 62a, 64a, 72a, and 74a for driving the same may be reduced. .

On the other hand, since the semiconductor memory device according to the present invention has the same block configuration except for the precharge auxiliary unit 100, the same reference numerals will be given, and detailed description thereof will be omitted.

4 is an internal circuit diagram of the precharge control signal generation unit 140 of FIG. 3.

Referring to FIG. 4, the precharge control signal generation unit 140 deactivates an output signal in response to the activation of the active command ACT and a signal for deactivating the output call in response to the activation of the precharge command PCG. Delay for outputting the generation unit 142, the latch unit 144 for latching the output signal of the signal generation unit 142, and the output signal of the latch unit 144 to output the precharge control signal pcg_ctr The unit 146 is provided.

FIG. 5 is an operation waveform diagram of FIG. 3 according to unit memory cell access. Referring to this, the operation of the semiconductor memory device according to the present invention will be described.

First, since all unit memory cell selection signals cell_mat_slt are inactivated in the standby state to which the active command ACT is not applied, the bit line separation signal generators 52a, 54a, 62a, 64a, 72a, and 74a are bit lines. Outputs the separated signal (BISH) by activating the power supply voltage VPP level. Therefore, all the unit memory cell array blocks 10, 20, 30, and 40 and the bit line sense amplifier blocks 50, 60, and 70 in the device are connected to each other.

Subsequently, when the active command ACT is applied, the precharge control signal generation unit 140 deactivates the precharge control signal pcg_ctr in response thereto, so that all of the switching units 120 are turned off to thereby remove the bit line separation signal. Ensure that all lines receiving (BISH) are separated from each other.

The bit line sense amplifier blocks positioned above and below the unit memory cell array block including the selected word line WL sense and amplify data of the unit memory cell connected to the selected word line.

For example, when the selected word line WL is located in the second unit memory cell array block 20, the first and fourth bit line separation signal generators 52a and 64a may select the corresponding unit memory cell selection signal. Detecting the first and second bit lines in which only the second unit memory cell array block 20 is located above and below the bit line separation signals BISH0 and BISL1 in response to (cell_mat_slt1), by deactivating the bit line separation signals BISH0 and BISL1 to the power supply voltage VSS level. Occupies the amplifier blocks 50 and 60.

Thereafter, when the precharge command PCG is applied, the unit memory cell selection signal cell_mat_slt1 is deactivated in response to the precharge command PCG, and thus the corresponding bit line separation signals BISH0 and BISL 1 are activated to the power supply voltage VPP level.

At this time, the precharge control signal generator 140 outputs the precharge control signal pcg_ctr at a logic level 'H' in response to the precharge signal PCG, and thus the bit line separation signals BISH0 and BISLO, BISH1, and BISL1. Charge-sharing (A and A ') is generated by connecting the lines to which are applied to each other.

That is, the line having the power supply voltage VSS level is applied to the bit line separation signal BISH0 and the level is increased, and the line having the power supply voltage VPP level is applied to the line with the BISL0 and BISH1 levels. Charge sharing is similarly performed on the lines to which the bit line separation signals BISH1 and BISL1 are applied.

In this way, charge sharing occurs between the inactivated line and the adjacently arranged and activated line according to the unit memory cell selection signal, so that these lines have intermediate levels of the power supply voltage VSS and the power supply voltage VPP, respectively.

Therefore, since the time required for each line to return to the power supply voltage VPP level to be maintained in the standby state is reduced, the bit line separation signal generator 52a, 54a, for generating the bit line separation signal applied to the line, is reduced. The size of the inverter in 62a, 64a, 72a, 74a) can be reduced.

Meanwhile, in the semiconductor memory device as described above, when the voltage levels of the bit line separation signals BISH and BISL have three voltage levels, respectively, depending on the activation of the standby state, the active state, and the deactivation of the active state, The effect of shortening the precharge time and reducing the area is increased. This will be described in detail with reference to the following operation waveform diagram.

As shown in FIG. 6, when the voltage levels of the bit line separation signals BISH and BISL are active, the power supply voltage VPP or the power supply voltage VSS is maintained, and when the precharge is performed, the power supply voltage VDD is maintained.

Therefore, during precharging, the precharge auxiliary unit 100 connects the lines having the level of the power supply voltage VPP and the power supply voltage VSS by the unit memory cell selection signal, respectively, to charge sharing (B, B 'in the drawing). Expressed part).

At this time, since the level of the power supply voltage VDD is lower than that of the power supply voltage VPP, charge sharing occurs between the lines having the power supply voltages VPP and VSS to easily maintain the level of the power supply voltage VDD in the standby state.

That is, as described above, the effect of shortening the precharge time and the area of the device due to charge sharing can be obtained more.

That is, the bit line separation signals BISH0 and BISL1, which are inactivated because the selected word line is positioned in the second unit memory cell array block, are reactivated to the power supply voltage VPP.

Therefore, the semiconductor memory device according to the present invention connects the lines driven by the power supply voltage VPP and the power supply voltage VSS to each other through the precharge auxiliary unit when the precharge command is applied, so that charge sharing occurs between the two lines. By reverting to the standby voltage level in time, the device's tRP is reduced, shortening the precharge time.

Therefore, the size of the inverter having a large area can be reduced to shorten the precharge time in the related art, thereby reducing the area of the device and reducing the amount of current consumed, thereby reducing power noise.                     

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

In the above-described invention, since lines having different voltage levels are connected to each other during precharging during operation, charge sharing occurs between the lines, so that restoration to a voltage level in the standby state occurs more quickly, thereby reducing the tRP of the device. Therefore, the precharge time is shortened.

In addition, due to the charge sharing, the area of a block having a large area for shortening of tRP can be reduced, thereby reducing the area of the device and reducing power noise since the amount of current consumed is reduced.

Claims (4)

A semiconductor memory device having a form in which adjacent unit memory cell array blocks share bit line detection amplifier blocks located between themselves, First and second bit line separators to allow only one of the adjacent unit memory cell array blocks to occupy the bit line sense amplifier block when active; And Precharge auxiliary unit for connecting metal lines to which the control signal for controlling the first and second bit line separation units are connected to each other when precharging A semiconductor memory device having a. A unit memory cell array block for storing data and having a plurality of unit memory cells accessed through word lines and bit lines; A bit line detection amplifier block comprising a plurality of bit line detection amplifiers for sensing and amplifying data of the unit memory cells, and shared by neighboring unit memory cell array blocks; Bit line separation signal generating means for generating a bit line separation signal in response to a unit memory cell selection signal activated upon access; Bit line separation means for allowing only one unit memory cell array block to occupy the bit line sense amplifier block in response to the bit line separation signal; And Precharge auxiliary means for connecting the lines to which the bit line separation signal is applied in the bit line separation unit located above and below the bit line detection amplifier block when precharging A semiconductor memory device having a. The method according to claim 1 or 2, The precharge auxiliary unit, A precharge control signal generation unit for generating a precharge control signal activated when the precharge is performed; A switching unit for connecting lines to which the bit line separation signal is applied in the bit line separation unit located above and below the bit line detection amplifier block in response to the precharge control signal; A semiconductor memory device comprising: a. The method of claim 3, The switching unit, And a plurality of NMOS transistors having the precharge control signal as a gate input and positioned above and below the bit line sense amplifier block and having drain-source paths between the lines receiving the bit line separation signal. A semiconductor memory device.

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