KR100894103B1 - Bit line isolation control circuit - Google Patents

Bit line isolation control circuit Download PDF

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KR100894103B1
KR100894103B1 KR1020070133636A KR20070133636A KR100894103B1 KR 100894103 B1 KR100894103 B1 KR 100894103B1 KR 1020070133636 A KR1020070133636 A KR 1020070133636A KR 20070133636 A KR20070133636 A KR 20070133636A KR 100894103 B1 KR100894103 B1 KR 100894103B1
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signal
bit line
sense amplifier
response
control circuit
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KR1020070133636A
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Korean (ko)
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이병철
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주식회사 하이닉스반도체
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4087—Address decoders, e.g. bit - or word line decoders; Multiple line decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4094—Bit-line management or control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/002—Isolation gates, i.e. gates coupling bit lines to the sense amplifier

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Dram (AREA)

Abstract

A bit line isolation control circuit is provided to perform charging and discharging rapidly by isolating a bit lien and complementary line according to a word decoding signal. A first switch(21) is connected between a bit line and a sense amplifier, and a second switch(22) is connected between a complementary bit line and the sense amplifier. A control signal generation unit receives a selection signal of a sense amplifier and a word line decoding signal and generates a first and a second isolation signal. The first isolation signal is used in order to have the first switch the turn off, and the second isolation signal is used in order to turn the second switch off.

Description

비트라인 격리 제어 회로{BIT LINE ISOLATION CONTROL CIRCUIT}Bit line isolation control circuit {BIT LINE ISOLATION CONTROL CIRCUIT}

본 발명은 반도체 메모리 장치에 관한 것으로, 더 상세하게는 비트라인 격리 제어 회로에 관한 것이다.The present invention relates to a semiconductor memory device, and more particularly to a bit line isolation control circuit.

도 1 은 일반적인 디램의 블럭도이고, 도 2 는 일반적인 디램 셀의 회로도이며, 도 3 은 종래 기술에 의한 비트라인 격리 제어 회로도이고, 도 4 는 도 3 에 의한 센스앰프의 동작 파형도이다.1 is a block diagram of a general DRAM, FIG. 2 is a circuit diagram of a general DRAM cell, FIG. 3 is a bit line isolation control circuit diagram according to the prior art, and FIG. 4 is an operation waveform diagram of the sense amplifier according to FIG.

도 1 내지 도 4 에 도시한 바와 같이, 일반적으로 디램은 액티브 되었을 때 워드라인이 뜨고, 셀 트랜지스터가 열리면서 비트라인에 데이터가 실려 차지 쉐어링(charge sharing)이 되고, 이를 센스앰프에서 증폭하여 출력한다.As shown in FIGS. 1 to 4, in general, a DRAM has a word line when activated, a cell transistor opens, data is loaded on a bit line, and is charged sharing, which is amplified by a sense amplifier and output. .

이때, 상기 센스앰프가 데이터를 증폭하여 출력하기에 앞서, 센스앰프와 연결되어 있는 비트라인 중 데이터가 실리지 않는 비트라인은 격리시키는데 이 신호가 비트라인 격리 신호(BLSH/BLSL)이다.At this time, before the sense amplifier amplifies and outputs the data, the bit line without data is isolated among the bit lines connected to the sense amplifier, which is a bit line isolation signal BLSH / BLSL.

도 2 의 참조하면, 디램 셀은 홀수번째와 짝수번째의 워드라인에 비트라 인(BL)이나 상보 비트라인(/BL)이 일정하게 연결되어 구성된다. 그런데, 만약 워드라인(WL0)이 떠서 상보 비트라인에 데이터가 실린다면 비트라인은 필요없게 된다.Referring to FIG. 2, a DRAM cell includes a bit line BL or a complementary bit line / BL connected to odd and even word lines. However, if the word line WL0 is floating and data is loaded on the complementary bit line, the bit line is not necessary.

그럼에도 불구하고, 종래 기술에 의한 비트라인 격리 제어 회로는 센스앰프와 연결되어 있는 비트라인 중 데이터가 실리지 않는 비트라인을 격리시킬 때 상위 비트라인쌍과 하위 비트라인쌍을 격리시키는 격리신호(BISH,BISL)만을 출력할 뿐 비트라인쌍 중 데이터가 실리지 않는 비트라인은 격리시키지 않는다. 이는 디램의 tRCD 특성을 나쁘게 하는 원인이 된다.Nevertheless, the conventional bit line isolation control circuit isolates an upper bit line pair and a lower bit line pair when the bit line without data is loaded among the bit lines connected to the sense amplifier. It only outputs BISL) and does not isolate the bit line where no data is loaded among the pair of bit lines. This causes the tRCD characteristics of the DRAM to deteriorate.

따라서, 본 발명은 센스앰프를 공유하는 상위 셀블럭과 하위 셀블럭을 격리시킴에 있어서 상위 셀블럭의 비트라인쌍과 하위 셀블럭의 비트라인쌍뿐만 아니라 비트라인쌍 중 데이터가 실리지 않는 비트라인 또는 상보 비트라인을 센스앰프와 격리시키는 비트라인 격리 제어 회로를 개시한다.Accordingly, in the present invention, in isolation of an upper cell block and a lower cell block sharing a sense amplifier, not only the bit line pair of the upper cell block and the bit line pair of the lower cell block, but also the bit line in which no data is loaded among the bit line pairs or A bit line isolation control circuit is disclosed that isolates a complementary bit line from a sense amplifier.

상기 기술적 과제를 이루기 위한 본 발명은 비트라인과 센스앰프 사이에 연결된 제1스위치, 상보 비트라인과 상기 센스앰프 사이에 연결된 제2스위치, 및 센스앰프 블럭 선택 신호와 워드라인 디코딩 신호를 입력받아 상기 제1스위치를 턴-오프시키기 위한 제1격리신호와 상기 제2스위치를 턴-오프시키기 위한 제2격리신호를 생성하는 제어신호 생성부를 포함한다.According to an aspect of the present invention, a first switch connected between a bit line and a sense amplifier, a second switch connected between a complementary bit line and the sense amplifier, and a sense amplifier block selection signal and a word line decoding signal are received. And a control signal generator configured to generate a first isolation signal for turning off the first switch and a second isolation signal for turning off the second switch.

그리고, 본 발명은 비트라인과 센스앰프 사이에 연결된 제1스위치, 상보 비트라인과 상기 센스앰프 사이에 연결된 제2스위치, 블럭 어드레스 신호에 응답하여 센스앰프 블럭 선택 신호를 출력하는 블럭 선택부, 로우 어드레스 신호에 응답하여 워드라인 디코딩 신호를 출력하는 로우 디코더, 및 상기 센스앰프 블럭 선택 신호와 상기 워드라인 디코딩 신호를 입력받아 상기 제1스위치를 턴-오프시키기 위한 제1격리신호와 상기 제2스위치를 턴-오프시키기 위한 제2격리신호를 생성하는 제어신호 생성부를 포함한다.In addition, the present invention provides a first switch connected between a bit line and a sense amplifier, a second switch connected between a complementary bit line and the sense amplifier, a block selector for outputting a sense amplifier block selection signal in response to a block address signal, and a row. A row decoder for outputting a wordline decoding signal in response to an address signal, and a first isolation signal and the second switch for turning off the first switch by receiving the sense amplifier block selection signal and the wordline decoding signal; And a control signal generator for generating a second isolation signal for turning off the signal.

이와 같이, 본 발명은 워드라인 디코딩 신호에 따라 센스앰프와 연결된 비트라인 또는 상보 비트라인을 격리시킴으로써 센스앰프에 의해 비트라인쌍이 디벨롭될 때 커패시터를 센스앰프 길이 만큼만 보게 되므로 빠르게 차지나 디스차지 되어 디램의 tRCD 특성을 향상시킨다.As described above, the present invention isolates the bit line or the complementary bit line connected to the sense amplifier according to the word line decoding signal, so that when the pair of bit lines is developed by the sense amplifier, the capacitor is only charged or discharged quickly. Improve the tRCD characteristics of DRAM.

이하, 본 발명의 바람직한 실시예를 첨부한 도면을 참고하여 상세히 설명한다.Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention will be described in detail.

도 5 는 본 발명에 의한 비트라인 격리 제어 회로의 블럭도이고, 도 6 은 도 5 의 제어신호 생성부의 회로도이며, 도 7 은 도 5 의 스위칭부의 회로도이다. 도 8 은 도 5 에 의한 센스앰프의 동작 파형도이다.5 is a block diagram of a bit line isolation control circuit according to the present invention, FIG. 6 is a circuit diagram of the control signal generator of FIG. 5, and FIG. 7 is a circuit diagram of the switching unit of FIG. 5. 8 is an operational waveform diagram of the sense amplifier of FIG. 5.

도 5 내지 도 7 에 도시한 바와 같이, 본 실시예에 의한 비트라인 격리 제어 회로는 비트라인(BL)과 센스앰프(BLSA) 사이에 연결된 제1스위치(21), 상보 비트라인(BLB)과 상기 센스앰프(BLSA) 사이에 연결된 제2스위치(22), 블럭 어드레스 신호에 응답하여 센스앰프 블럭 선택 신호(BXI,BXJ)를 출력하는 블럭 선택부(30), 로우 어드레스 신호에 응답하여 워드라인 디코딩 신호(AT)를 출력하는 로우 디코더(40), 및 센스앰프 블럭 선택 신호(BXI,BXJ)와 워드라인 디코딩 신호(AT)를 입력받아 상기 제1스위치(21)를 턴-오프시키기 위한 제1격리신호(BISHE,BISLE)와 상기 제2스위치(22)를 턴-오프시키기 위한 제2격리신호(BISHO,BISLO)를 생성하는 제어신호 생성부(10)를 포함한다.5 to 7, the bit line isolation control circuit according to the present embodiment includes a first switch 21 and a complementary bit line BLB connected between the bit line BL and the sense amplifier BLSA. A second switch 22 connected between the sense amplifiers BLSA, a block selector 30 outputting sense amplifier block selection signals BXI and BXJ in response to a block address signal, and a word line in response to a row address signal A row decoder 40 for outputting a decoding signal AT, a sense amplifier block selection signal BXI, BXJ, and a word line decoding signal AT to turn off the first switch 21; The control signal generator 10 generates a first isolation signal BISHE, BISLE and a second isolation signal BISHO, BISLO for turning off the second switch 22.

상기 제어신호 생성부(10)는 상기 센스앰프 블럭 선택 신호와 상기 워드라인 디코딩 신호에 응답하여 논리 연산하는 연산부(11)와, 상기 연산부의 출력신호에 응답하여 구동하는 구동부(12)를 포함한다.The control signal generation unit 10 includes an operation unit 11 for performing a logical operation in response to the sense amplifier block selection signal and the word line decoding signal, and a driving unit 12 for driving in response to an output signal of the operation unit. .

상기 연산부(11)는 상기 센스앰프 블럭 선택 신호(BXI,BXJ)와 상기 워드라인 디코딩 신호(AT)에 응답하여 논리합 연산하는 논리소자를 포함한다.The calculation unit 11 includes a logic element that performs an OR operation in response to the sense amplifier block selection signals BXI and BXJ and the wordline decoding signal AT.

상기 구동부(12)는 상기 연산부의 출력신호에 응답하여 풀-업 구동하는 풀-업 구동부(P1)와, 상기 연산부의 출력신호에 응답하여 풀-다운 구동하는 풀-다운 구동부(N1)를 포함한다.;The driver 12 includes a pull-up driver P1 for pull-up driving in response to an output signal of the calculator, and a pull-down driver N1 for pull-down driving in response to an output signal of the calculator. do.;

그리고, 상기 제어신호 생성부(10)는 상기 구동부(12)의 출력신호를 래치하는 래치부(13)와, 상기 래치부의 출력신호를 버퍼링하는 버퍼부(14)를 더 포함한다.The control signal generator 10 further includes a latch unit 13 for latching an output signal of the driver 12, and a buffer unit 14 for buffering the output signal of the latch unit.

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이와 같이 구성된 본 발명의 동작을 도면을 참조하여 상세히 설명하면 다음과 같다.The operation of the present invention configured as described above will be described in detail with reference to the accompanying drawings.

먼저, 본 발명의 제어신호는 생성부(10)는 센스앰프 블럭 선택 신호(BXI,BXJ)와 워드라인 디코딩 신호(AT)에 응답하여 상기 워드라인 디코딩 신호(AT)에 따라 센스앰프(BLSA)과 비트라인(BL)을 격리시키는 제1격리신호(BISHE,BISLE)와 센스앰프(BLSA)과 상보 비트라인(BLB)을 격리시키는 제2제어신호(BISHO,BISLO)를 출력한다.First, the control signal generator 10 of the present invention responds to the sense amplifier block selection signals BXI and BXJ and the word line decoding signal AT according to the word line decoding signal AT. And the first isolation signals BISHE and BISLE to isolate the bit line BL and the second control signals BISHO and BISLO to isolate the sense amplifier BLSA and the complementary bit line BLB.

그러면, 센스앰프 블럭 선택 신호(BXI,BXJ)와 워드라인 디코딩 신호(AT)에 따라 제1격리신호(BISHE,BISLE) 또는 제2제어신호(BISHO,BISLO)가 활성화된다.Then, the first isolation signals BISHE and BISLE or the second control signals BISHO and BISLO are activated according to the sense amplifier block selection signals BXI and BXJ and the word line decoding signals AT.

즉, 워드라인이 짝수번째냐 홀수번째냐에 따라 다시 설명하면 데이터가 비트라인(BL)에 실리는지 상보 비트라인(BLB)에 실리는지에 따라 제1격리신호(BISHE,BISLE) 또는 제2제어신호(BISHO,BISLO)가 활성화된다.That is, if the word line is described again according to the even or odd number, the first isolation signal BISHE or BISLE or the second control signal depends on whether the data is loaded on the bit line BL or the complementary bit line BLB. (BISHO, BISLO) is activated.

그러면, 제1스위치(21)는 제1격리신호(BISHE,BISLE)에 따라 턴-오프되고, 제2스위치(22)는 제2격리신호(BISHO,BISLO)에 따라 턴-오프된다.Then, the first switch 21 is turned off according to the first isolation signals BISHE and BISLE, and the second switch 22 is turned off according to the second isolation signals BISHO and BISLO.

이와 같이 본 발명은 워드라인 디코딩 신호에 따라 즉 데이터가 비트라인(BL)에 실리는지 상보 비트라인(BLB)에 실리는지에 따라 제1격리신호(BISHE,BISLE) 또는 제2제어신호(BISHO,BISLO)가 활성화된다.As described above, according to the present invention, the first isolation signal BISHE, BISLE, or the second control signal BISHO, depending on the word line decoding signal, that is, whether the data is loaded on the bit line BL or the complementary bit line BLB. BISLO) is activated.

그러면, 비트라인에 데이터가 실려 차지 쉐어링(charge sharing)이 되고, 이를 센스앰프에서 증폭하여 출력한다. 이러한 본 발명은 센스앰프가 하나의 비트라인의 캡만 보는 상태이므로 기존 장치보다 비트라인의 디벨롭이 빠르게 된다. 이의 시뮬레이션 결과는 도 6 에 도시하였다.Then, the data is loaded on the bit line for charge sharing, which is amplified by the sense amplifier and output. In the present invention, since the sense amplifier only sees the cap of one bit line, the development of the bit line is faster than that of the conventional apparatus. The simulation result thereof is shown in FIG. 6.

이와 같이, 본 발명은 워드라인 디코딩 신호에 따라 센스앰프와 연결된 비트라인쌍 중 비트라인 또는 상보 비트라인을 격리시킴으로써 센스앰프에 의해 비트라인이 디벨롭될 때 커패시터를 센스앰프 길이 만큼만 보게 되므로 빠르게 차지나 디스차지 되어 디램의 tRCD 특성을 향상시킨다.As described above, the present invention isolates the bit line or the complementary bit line among the pair of bit lines connected to the sense amplifier according to the word line decoding signal, so that when the bit line is developed by the sense amplifier, the capacitor is viewed only as long as the sense amplifier length. Discharged to improve the tRCD characteristics of the DRAM.

도 1 은 일반적인 디램의 블럭도이다.1 is a block diagram of a general DRAM.

도 2 는 일반적인 디램 셀의 회로도이다.2 is a circuit diagram of a general DRAM cell.

도 3 은 종래 기술에 의한 비트라인 격리 제어 회로도이다.3 is a bit line isolation control circuit diagram according to the prior art.

도 4 는 도 3 에 의한 센스앰프의 동작 파형도이다.4 is an operational waveform diagram of the sense amplifier of FIG. 3.

도 5 는 본 발명에 의한 비트라인 격리 제어 회로의 블럭도이다.5 is a block diagram of a bit line isolation control circuit in accordance with the present invention.

도 6 은 도 5 의 제어신호 생성부의 회로도이다.6 is a circuit diagram of a control signal generator of FIG. 5.

도 7 은 도 5 의 스위칭부의 회로도이다.7 is a circuit diagram of the switching unit of FIG. 5.

도 8 은 도 5 에 의한 센스앰프의 동작 파형도이다.8 is an operational waveform diagram of the sense amplifier of FIG. 5.

Claims (14)

비트라인과 센스앰프 사이에 연결된 제1스위치;A first switch connected between the bit line and the sense amplifier; 상보 비트라인과 상기 센스앰프 사이에 연결된 제2스위치; 및A second switch connected between a complementary bit line and the sense amplifier; And 센스앰프 블럭 선택 신호와 워드라인 디코딩 신호를 입력받아 상기 제1스위치를 턴-오프시키기 위한 제1격리신호와 상기 제2스위치를 턴-오프시키기 위한 제2격리신호를 생성하는 제어신호 생성부를 포함하는 비트라인 격리 제어 회로.A control signal generator configured to receive a sense amplifier block selection signal and a word line decoding signal to generate a first isolation signal for turning off the first switch and a second isolation signal for turning off the second switch; Bit line isolation control circuit. 삭제delete 삭제delete 제 1 항에 있어서,The method of claim 1, 상기 제어신호 생성부는The control signal generator 상기 센스앰프 블럭 선택 신호와 상기 워드라인 디코딩 신호에 응답하여 논리 연산하는 연산부와;An operation unit configured to perform a logical operation in response to the sense amplifier block selection signal and the word line decoding signal; 상기 연산부의 출력신호에 응답하여 구동하는 구동부;A driving unit driving in response to an output signal of the calculating unit; 를 포함하는 비트라인 격리 제어 회로.Bit line isolation control circuit comprising a. 제 4 항에 있어서,The method of claim 4, wherein 상기 연산부는 상기 센스앰프 블럭 선택 신호와 상기 워드라인 디코딩 신호에 응답하여 논리합 연산하는 논리소자;The operation unit comprises a logic element for performing an OR operation in response to the sense amplifier block selection signal and the word line decoding signal; 를 포함하는 비트라인 격리 제어 회로.Bit line isolation control circuit comprising a. 제 4 항에 있어서,The method of claim 4, wherein 상기 구동부는 상기 연산부의 출력신호에 응답하여 풀-업 구동하는 풀-업 구동부와;The driving unit includes a pull-up driving unit for pull-up driving in response to the output signal of the operation unit; 상기 연산부의 출력신호에 응답하여 풀-다운 구동하는 풀-다운 구동부;A pull-down driving unit for pull-down driving in response to an output signal of the calculator; 를 포함하는 비트라인 격리 제어 회로.Bit line isolation control circuit comprising a. 제 4 항에 있어서,The method of claim 4, wherein 상기 제어신호 생성부는 상기 구동부의 출력신호를 래치하는 래치부와;The control signal generator comprises a latch unit for latching an output signal of the driver; 상기 래치부의 출력신호를 버퍼링하는 버퍼부;A buffer unit for buffering an output signal of the latch unit; 를 더 포함하는 비트라인 격리 제어 회로.Bit line isolation control circuit further comprising. 삭제delete 비트라인과 센스앰프 사이에 연결된 제1스위치;A first switch connected between the bit line and the sense amplifier; 상보 비트라인과 상기 센스앰프 사이에 연결된 제2스위치; A second switch connected between a complementary bit line and the sense amplifier; 블럭 어드레스 신호에 응답하여 센스앰프 블럭 선택 신호를 출력하는 블럭 선택부;A block selector configured to output a sense amplifier block select signal in response to the block address signal; 로우 어드레스 신호에 응답하여 워드라인 디코딩 신호를 출력하는 로우 디코더; 및A row decoder for outputting a wordline decoding signal in response to the row address signal; And 상기 센스앰프 블럭 선택 신호와 상기 워드라인 디코딩 신호를 입력받아 상기 제1스위치를 턴-오프시키기 위한 제1격리신호와 상기 제2스위치를 턴-오프시키기 위한 제2격리신호를 생성하는 제어신호 생성부를 포함하는 비트라인 격리 제어 회로.Generates a control signal for receiving the sense amplifier block selection signal and the word line decoding signal and generating a first isolation signal for turning off the first switch and a second isolation signal for turning off the second switch. Bit line isolation control circuit comprising a. 제 9 항에 있어서,The method of claim 9, 상기 제어신호 생성부는The control signal generator 상기 센스앰프 블럭 선택 신호와 상기 워드라인 디코딩 신호에 응답하여 논리 연산하는 연산부와;An operation unit configured to perform a logical operation in response to the sense amplifier block selection signal and the word line decoding signal; 상기 연산부의 출력신호에 응답하여 구동하는 구동부;A driving unit driving in response to an output signal of the calculating unit; 를 포함하는 비트라인 격리 제어 회로.Bit line isolation control circuit comprising a. 제 10 항에 있어서,The method of claim 10, 상기 연산부는 상기 센스앰프 블럭 선택 신호와 상기 워드라인 디코딩 신호에 응답하여 논리합 연산하는 논리소자;The operation unit comprises a logic element for performing an OR operation in response to the sense amplifier block selection signal and the word line decoding signal; 를 포함하는 비트라인 격리 제어 회로.Bit line isolation control circuit comprising a. 제 10 항에 있어서,The method of claim 10, 상기 구동부는 상기 연산부의 출력신호에 응답하여 풀-업 구동하는 풀-업 구동부와;The driving unit includes a pull-up driving unit for pull-up driving in response to the output signal of the operation unit; 상기 연산부의 출력신호에 응답하여 풀-다운 구동하는 풀-다운 구동부;A pull-down driving unit for pull-down driving in response to an output signal of the calculator; 를 포함하는 비트라인 격리 제어 회로.Bit line isolation control circuit comprising a. 제 10 항에 있어서,The method of claim 10, 상기 제어신호 생성부는 상기 구동부의 출력신호를 래치하는 래치부와;The control signal generator comprises a latch unit for latching an output signal of the driver; 상기 래치부의 출력신호를 버퍼링하는 버퍼부;A buffer unit for buffering an output signal of the latch unit; 를 더 포함하는 비트라인 격리 제어 회로.Bit line isolation control circuit further comprising. 삭제delete
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020002014A (en) * 2000-06-29 2002-01-09 박종섭 Semiconductor memory device
KR20060063217A (en) * 2004-12-07 2006-06-12 주식회사 하이닉스반도체 Semiconductor memory device
KR20060087372A (en) * 2005-01-28 2006-08-02 삼성전자주식회사 Semiconductor memory device and method for controlling sub word line driver thereof
KR100757936B1 (en) 2006-09-25 2007-09-11 주식회사 하이닉스반도체 Circuit for controlling bit-line of semiconductor memory apparatus

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020002014A (en) * 2000-06-29 2002-01-09 박종섭 Semiconductor memory device
KR20060063217A (en) * 2004-12-07 2006-06-12 주식회사 하이닉스반도체 Semiconductor memory device
KR20060087372A (en) * 2005-01-28 2006-08-02 삼성전자주식회사 Semiconductor memory device and method for controlling sub word line driver thereof
KR100757936B1 (en) 2006-09-25 2007-09-11 주식회사 하이닉스반도체 Circuit for controlling bit-line of semiconductor memory apparatus

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