KR20060061088A - Flash memory device and method for supplying program voltage thereof - Google Patents

Abstract

In the flash memory device and a program method thereof disclosed herein, after precharging the word lines to a predetermined level by applying a pass voltage Vpass to all word lines of a block to be programmed, the word lines of the cell to be programmed. The program voltage Vpgm_ramp is applied, and the program voltage Vpgm_ramp and the pass voltage Vpass are divided at predetermined resistance ratios, respectively, and the timing of applying the program voltage Vpgm_ramp is controlled by comparing the magnitudes of the divided voltage results. As a result, the program voltage Vpgm_ramp applied to the selected word line always has a higher value than the pass voltage Vpass, thereby increasing the boosting efficiency and increasing the program reliability.

Description

Flash memory device and its program voltage application method {FLASH MEMORY DEVICE AND METHOD FOR SUPPLYING PROGRAM VOLTAGE THEREOF}

1 is a diagram illustrating a word line voltage change according to a general program method;

2 is a view illustrating a change of a word line voltage according to a level of a target word line voltage during programming;

3 is a block diagram of a flash memory device according to a preferred embodiment of the present invention;

4 is a circuit diagram of the memory cell array shown in FIG. 3;

5 is a detailed block diagram of the wordline drive circuit shown in FIG. 3;

6 is a timing diagram of each control signal and a high voltage during programming according to the present invention; And

7 is a view illustrating a change in voltage applied to a word line during programming according to the present invention.

* Description of the symbols for the main parts of the drawings *

10: memory cell array 20: Y-gate

30: page buffer circuit 40: Y-decoder

50: X-decoder 60: word line drive circuit

70: high voltage lamp circuit 80: high voltage generating circuit

90: program controller 100: flash semiconductor memory

The present invention relates to a nonvolatile semiconductor memory device, and more particularly, to a NAND flash memory device and a method of applying a program voltage thereof.

In a nonvolatile memory device, data written in a cell remains undeleted even when power is not supplied. Among nonvolatile memories, flash memory has a function of electrically erasing data of cells collectively, and thus is widely used in computers and memory cards.

Flash memory is divided into NOR type and NAND type according to the connection state of cells and bit lines. In general, NOR flash memory is disadvantageous for high integration because of the large current consumption, but there is an advantage that can easily cope with high speed. In addition, since the NAND flash memory uses less cell current than the NOR flash memory, there is an advantage in that it is advantageous for high integration.

The NAND flash memory includes a memory cell array as a storage area for storing information. The memory cell array is composed of a plurality of blocks, and each block is composed of a plurality of cell strings (or called NAND strings). The flash memory is provided with a page buffer circuit to store data in or read data from the memory cell array. As is well known, memory cells of a NAND flash memory are erased and programmed using F-Nordheim tunneling current. Methods for erasing and programming NAND flash EEPROMs are entitled "Nonvolatile Semiconductor Memory" in U.S. Patent No. 5,473,563 and "Nonvolatile Integrated Circuit Memory Devices Having Adjustable Erase / Program Threshold Voltage Verification Capability" in U.S. Patent No. 5,696,717. Each is published.

1 is a diagram illustrating a change in a word line voltage of a flash memory device.

Referring to FIG. 1, in order to accurately control threshold voltage distribution of flash memory cells, flash memory cells are programmed by an incremental step pulse programming (ISPP) scheme. A circuit for generating a program voltage according to the ISPP method is disclosed in US Patent Publication No. 5,642,309 entitled "AUTO-PROGRAM CIRCUIT IN A NONVOLATILE SEMICONDUCTOR MEMORY DEVICE".

The program voltage Vpgm according to the ISPP programming scheme is increased step by step as the program loops of the program cycle are repeated as shown in FIG. 1. Each program loop, as is well known, consists of a program interval and a program verification interval. The program voltage Vpgm increases by a predetermined increment DELTA Vpgm, and the program time is kept constant for each program loop.

However, when a vertically increased program voltage Vpgm occurs for each program step, coupling noise increases. Coupling noise may be caused by increasing the degree of integration of the memory device and decreasing the spacing between adjacent signal lines, such as adjacent word lines (eg, adjacent word lines, string select lines SSL, or ground select transistors GST). This occurs as the capacitance coupling between the capacitors increases. In order to solve this problem, instead of generating a vertically increased program voltage Vpgm, a flash memory device generates a sequentially increased program voltage Vpgm_ramp using a high voltage ramping circuit. .

2 is a diagram illustrating a change in a word line voltage according to a level of a target word line voltage during programming. 2 illustrates a change in the word line voltage when a program inhibit technique using a self-boosting scheme is applied.

Referring to FIG. 2, according to a program protection scheme using a self-boosting scheme, first, a block to be programmed is selected, and a pass voltage Vpass is applied to all word lines of the selected block. The memory cells included in the block are all precharged to a predetermined level by the pass voltage Vpass applied to the word lines. Then, a stepped-up program voltage Vpgm_ramp is applied to the word line of the cell to be programmed. The program voltage Vpgm_ramp applied at this time is generated step by step according to the ISPP scheme as shown in FIG. 1. Then, the target program voltage Target Vpgm in each step of the ISPP is sequentially raised in a stepped form by the high voltage ramp circuit.

In FIG. 2, the target program voltage Target Vpgm has a level of 14V and a case of 20V, respectively. The target program voltages (Target Vpgm) are generated through a ramping process in five steps, respectively. Preferably, the level of the ramped program voltage Vpgm_ramp should be higher than the pass voltage Vpass applied to the word lines. However, as illustrated in FIG. 2, as the level of the target program voltage Target Vpgm is lowered, a problem arises in that the ramped program voltage Vpgm_ramp becomes lower than the level of the pass voltage Vpass. (See the dotted line in Fig. 2). This problem occurs because the step of ramping in the high voltage ramp circuit is set to a predetermined level despite the low level of the target program voltage Target Vpgm. When the ramped program voltage Vpgm_ramp is lower than the level of the pass voltage Vpass, the boosting efficiency is lowered, thereby lowering the reliability of the program.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and to provide a NAND flash memory device having a high program reliability and a program method thereof.

According to a feature of the present invention for achieving the above object, a method of applying a program voltage of a flash memory device, the method comprising: applying a pass voltage to all the word lines of the memory block to be programmed; Monitoring the level of the pass voltage and the level of the program voltage while the pass voltage is applied; And if the program voltage is higher than the pass voltage, applying the program voltage to a selected word line.

In example embodiments, when the program voltage is lower than the pass voltage, the pass voltage is applied to the selected word line.

In a preferred embodiment, monitoring the program voltage comprises: dividing the pass voltage and the program voltage; Comparing the magnitudes of the partial pressure results; And in response to the comparison result, applying one of the program voltage and the pass voltage to the selected word line.

In example embodiments, the pass voltage may be applied to the selected word line if the divided voltage result of the program voltage is lower than the divided voltage result of the pass voltage.

In a preferred embodiment, the program voltage is generated by an incremental step pulse programming (ISPP) scheme that is incremented step by step for each program loop, and the program voltage for each program loop includes a plurality of ramping operations. Step by step up to a predetermined voltage level is characterized in that.

According to another aspect of the present invention for achieving the above object, a program voltage application method of a flash memory device, the memory cell array consisting of a plurality of memory cells; A program controller for controlling a program for the memory cells; A high voltage generator configured to generate a pass voltage and a program voltage under control of the program controller; And a word line driver circuit for monitoring the level of the program voltage and outputting any one of the pass voltage and the program voltage to a selected word line according to the monitoring result.

In an exemplary embodiment, the high voltage generation unit may include: a high voltage generation circuit configured to generate the pass voltage and the program voltage under control of the program controller; And a high voltage ramping circuit for gradually raising the program voltage generated from the high voltage generating circuit.

The word line driver circuit may include: a first switch configured to output the pass voltage in response to a pass voltage activation signal input from the program controller; A high voltage monitoring unit for monitoring a level of the program voltage and generating a program voltage activation signal according to the monitoring result; And a second switch configured to output the program voltage to the word line in response to the program voltage activation signal generated from the high voltage monitoring unit.

The high voltage monitoring unit may deactivate the program voltage activation signal when the program voltage is lower than the pass voltage as a result of the monitoring.

In a preferred embodiment, the high voltage monitoring unit, a voltage divider for dividing the program voltage and the pass voltage; A comparator for comparing the magnitudes of the partial pressure results; A first signal output unit configured to generate the program voltage enable signal based on the comparison result; And a second signal output unit configured to generate the pass voltage enable signal based on the comparison result.

In a preferred embodiment, the program voltage enable signal and the pass voltage enable signal generated from the first signal output unit and the second signal output unit have complementary values.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In the novel flash memory device and its programming method of the present invention, after precharging the word lines to a predetermined level by applying a pass voltage Vpass to all word lines of the block to be programmed, the word of the cell to be programmed. The program voltage Vpgm_ramp is applied to the line. The program voltage Vpgm_ramp is not applied to the corresponding word line immediately when the activated program voltage enable signal Vpgm_EN is input, and is not selected until the program voltage Vpgm_ramp is higher than the pass voltage Vpass. The program voltage Vpgm_ramp is applied to the word line. As a result, the program voltage Vpgm_ramp applied to the selected word line always has a higher value than the pass voltage Vpass, thereby increasing the boosting efficiency and increasing the program reliability.

3 is a block diagram of a flash memory device 100 according to a preferred embodiment of the present invention. The flash memory device 100 is a NAND flash memory device, and in FIG. 3, one of the plurality of array blocks included in the flash memory device 100 and peripheral circuits related thereto (particularly, related to a program) are illustrated. Only peripheral circuits are shown.

Referring to FIG. 3, a flash memory device 100 according to the present invention may include a memory cell array 10, a Y-gate circuit 20, a page buffer circuit; 30), the Y-decoder 40, the X-decoder 50, the word line drive circuit 60, the high voltage ramp circuit 70, the high voltage generating circuit 80 and the program controller 90 Include.

The memory cell array 10 is composed of a plurality of memory blocks. A plurality of bit lines BL1 -BLm are arranged in parallel in the plurality of memory blocks. Each memory block includes a plurality of strings corresponding to the bit lines BL1 to BLm, respectively. The configuration of each string included in each memory block will be described in detail with reference to FIG. 4.

The page buffer circuit 30 is connected to the memory cell array 10 through a plurality of bit lines. The page buffer circuit 30 includes a plurality of page buffers. The Y-gate 20 and the Y-decoder 40 select some of the plurality of buffers included in the page buffer circuit 30 in response to the Y-address Y_Add input from the outside. The data to be programmed is stored in the selected page buffer. The data DQi is transferred to the corresponding page buffer through the Y-gate 20.

Meanwhile, the high voltage generation circuit 80 is a high voltage pumping circuit composed of transistors (not shown) and a pumping capacitor (not shown). The high voltage generation circuit 80 generates a high voltage Vpgm to be used for the program and a pass voltage Vpass in response to the program activation signal PGM_EN generated from the program control unit 90. The high voltage Vpgm generated from the high voltage generation circuit 80 is applied to the high voltage ramp circuit 70, and the pass voltage Vpass is applied to the word line drive circuit 60.

The high voltage lamp circuit 70 sequentially increases the program voltage Vpgm_ramp in the form of a step in response to the lamp activation signal Ramp_EN generated from the controller 90 and the high voltage Vpgm generated from the high voltage generator circuit 80. Will occur). The high voltage lamp circuit 70 sequentially distributes the high voltage Vpgm by using a plurality of diodes connected in series, for example. As a result, the high voltage ramp circuit 70 may generate a program voltage Vpgm_ramp having a voltage level sequentially increased by the threshold voltage Vth of the diode. This sequential generation of high voltage is called ramping. The program voltage Vpgm_ramp generated from the high voltage ramp circuit 70 is applied to the word line of the cell to be programmed through the word line drive circuit 60.

The word line drive circuit 60 receives the program voltage Vpgm_ramp from the high voltage ramp circuit 70 and the pass voltage Vpass from the high voltage generation circuit 80 so that the voltages Vpgm_ramp and Vpass are word lines. Switch so that it can be applied. The word line drive circuit 60 includes a high voltage monitoring circuit 65 to monitor the level of the pass voltage Vpass and the program voltage Vpgm_ramp. The high voltage monitoring circuit 65 allows the pass voltage Vpass to be applied to all word lines of the block to be programmed in response to an activated pass voltage enable signal Vpass_EN initially generated from the program controller 90. . Then, when the program voltage Vpgm_ramp is generated from the high voltage ramp circuit 70, the program voltage Vpgm_ramp or the pass voltage (based on the monitoring result is not applied immediately without applying the program voltage Vpgm_ramp to the corresponding word line). Vpass) is applied to the corresponding word line. For example, when the activated program voltage enable signal Vpgm_EN is input from the program controller 90 and the program voltage Vpgm_ramp is found to be higher than the pass voltage Vpass, the monitoring circuit 65 does not start the program voltage. Control to apply (Vpgm_ramp) to the selected word line. As a result, the program voltage Vpgm_ramp applied to the selected word line always has a higher value than the pass voltage Vpass, thereby increasing the boosting efficiency and increasing the program reliability. The application method of such a program voltage will be described in detail below.

The X-decoder 50 selects a word line of a cell to be programmed in response to an X-address X_Add input from the outside. The X-decoder 50 applies the program voltage Vpgm_ramp or the pass voltage Vpass transferred from the word line driver circuit 60 to the selected word line.

This series of operations is performed by the control of the program control unit 90. The program controller 90 controls a program operation on the flash memory device 100 in response to a program command PGM_CMD and address information X_Add and Y_Add input from the outside. The program controller 90 controls the high voltage generation operation of the high voltage generation circuit 80 to generate a program voltage (Target Vpgm) for each program loop according to the ISPP programming method. In order to prevent coupling between adjacent signal lines, a rising slop of a program voltage (Target Vpgm) for each program loop is controlled. To this end, the program controller 90 controls the ramping operation of the high voltage lamp circuit 70. The high voltage ramp circuit 70 generates a program voltage Vpgm_ramp that increases in a step form in response to the ramping activation signal Ramp_EN generated from the program controller 90.

In addition, the program controller 90 applies a voltage to the word line according to a self-boosting scheme in order to prevent unwanted cells among the memory cells connected to the same word line during programming. To this end, the program controller 90 first applies a pass voltage Vpass to all word lines of the block selected for the program to precharge the word lines, and then applies the program voltage Vpgm_ramp to the selected word lines. . The time point at which the program voltage Vpgm_ramp is applied to the selected word line is determined according to the monitoring result of the program voltage Vpgm_ramp of the word line drive circuit 60. The structure of the memory cell array to be programmed is as follows.

4 is a circuit diagram of the memory cell array 10 shown in FIG. 3.

Referring to FIG. 4, the memory cell array 10 is composed of a plurality of memory blocks. A plurality of bit lines BL1 -BLm are arranged in parallel in each memory block. In addition, each memory block includes a plurality of strings corresponding to the plurality of bit lines BL1 -BLm, respectively.

As shown in FIG. 4, each string is connected in series between a string select transistor SST, a ground select transistor GST, and a source of the string select transistor SST and a drain of the ground select transistor GST. It is composed of a plurality of flash EEPROM cell transistors (eg, 16 flash EEPROM cell transistors M15-M0). 4 illustrates a case where each string is composed of 16 flash EEPROM cell transistors M15-M0, but this is only an example, and the number of flash EEPROM cell transistors constituting the string is adjustable.

The drain of the string select transistor GST of each string is connected to the corresponding bit line. The source of the ground select transistor GST of each string is connected to a common source line CSL. Gates of the string select transistors SST in each string are commonly connected to the string select line SSL, and gates of the ground select transistors GST are commonly connected to the ground select line GSL. The control gates of the flash EEPROM cell transistors of each string are commonly connected to the corresponding word line of the word lines WL0-WL15. Each bit line BL1-BLm is electrically connected to a corresponding page buffer (not shown) included in the page buffer circuit 30 shown in FIG. 3.

The ground select line GSL, the word lines WL0-WL15, and the string select line SSL may be connected to the corresponding select signal lines GS, through the corresponding block select transistors BS0-BS17. Si0-Si15, SS) respectively. The block select transistors BS0-BS17 are included in the X-decoder 50 of FIG. 3, and are connected to be commonly controlled by the block select control signal BS.

The selection signal lines GS, Si0-Si15, SS are driven at voltages required by corresponding selection circuits (or driving circuits), respectively, when a program operation is performed. Here, the selected block selection control signal BS may sufficiently transfer the program voltage Vpgm_ramp or the pass voltage Vpass transmitted through the selection signal lines Si0-Si15 to the corresponding word lines WL0-WL15. So that it has a high voltage level. The configuration of the word line driver circuit 60 that outputs a signal (that is, a program voltage Vpgm_ramp or a pass voltage Vpass) transmitted to the word lines WL0-WL15 to the signal lines Si0-Si15 is as follows. Same as

FIG. 5 is a detailed block diagram of the wordline drive circuit 60 shown in FIG.

Referring to FIG. 5, the word line driver circuit 60 selectively applies a program voltage Vpgm_ramp or a pass voltage Vpass to the selection signal lines Sii-Sij corresponding to each word line of the selected block. Word line drivers 60i-60j. Each word line driver 60i to 60j includes first switches 61i and 61j for controlling the output of the pass voltage Vpass and second switches 63i and 63j for controlling the output of the program voltage Vpgm_ramp. And high voltage monitoring units 65i and 65j for monitoring the pass voltage Vpass and the program voltage Vpgm_ramp to control an application time point of the program voltage Vpgm_ramp.

When the pass voltage enable signals Vpass_ENi and Vpass_ENj are activated from the program controller 90, the high voltage monitoring units 65i and 65j may apply the pass voltage Vpass to all word lines of the block to be programmed. In order to generate the pass voltage enable signals Vpass_ENi 'and Vpass_ENj', the first switches 61i and 61j are activated.

Then, when the program voltage Vpgm_ramp is generated from the high voltage ramp circuit 70, the pass voltage Vpass and the program voltage Vpgm_ramp are divided to predetermined levels through the first and second voltage dividing circuits 651 and 652, respectively. do. The divided voltage results Vdvd_pgm and Vdvd_pass generated from the first and second voltage dividing circuits 651 and 652 are input to the comparator 653. The comparator 653 compares the partial pressure results Vdvd_pgm and Vdvd_pass, and generates a comparison result Level_Detect of a high or low level. The comparison result Level_Detect generated from the comparator 653 is input to the first and second signal output units 654 and 657. The first and second signal output units 654 and 657, in response to the comparison result Level_Detect generated from the comparator 653, pass voltage enable signals Vpass_ENi 'and Vpass_ENj' and a program voltage enable signal ( Vpgm_ENi ', Vpgm_ENj') respectively occur. To this end, the first and second signal output units 654 and 657 include NAND gates 655 and 658 and inverters 656 and 659, respectively. The first signal output unit 654 performs a logical NAND operation of the comparison result Level_Detect and the pass voltage enable signal Vpass_EN through the NAND gate 655. The logic NAND calculation result is output as a pass voltage enable signal Vpass_ENi 'and Vpass_ENj' through the inverter 656. The output signal of the NAND gate 655 is input to the NAND gate 658 of the second signal output unit 657. The NAND gate 658 included in the second signal output unit 657 performs a logical NAND operation between the NAND operation result input from the first signal output unit 654 and the program voltage enable signal Vpgm_EN. The logical NAND operation result is output to the inverter 659 included in the second signal output unit 657. The inverter 659 inverts the output of the NAND gate 658 and outputs the program voltage enable signals Vpgm_ENi 'and Vpgm_ENj'. At this time, the pass voltage enable signals Vpass_ENi 'and Vpass_ENj' and the program voltage enable signals Vpgm_ENi 'and Vpgm_ENj' output through the first and second signal output units 654 and 657 are complementary to each other. Has

For example, when the activated program voltage enable signal Vpgm_ENi is input from the program controller 90 and the comparison result confirms that the program voltage Vpgm_ramp is lower than the pass voltage Vpass, the monitoring circuit 65 Outputs the activated pass voltage enable signal Vpass_ENi 'to the first switch 61i. As a result, despite the input of the activated program voltage enable signal Vpgm_EN, a pass voltage Vpass is applied to the selected word line. As a result, the problem that the program voltage Vpgm_ramp becomes lower than the pass voltage Vpass is prevented.

When the activated program voltage enable signal Vpgm_ENi is input from the program controller 90, when the comparison result confirms that the program voltage Vpgm_ramp is higher than the pass voltage Vpass, the monitoring circuit 65 is activated. The programmed voltage enable signal Vpgm_ENi 'is outputted to the second switch 63i. As a result, the program voltage Vpgn_ramp may be applied to the selected word line. According to the method of applying the program voltage, the program voltage Vpgm_ramp applied to the selected word line is always higher than the pass voltage Vpass, so that the boosting efficiency can be increased and the program reliability can be increased. do.

In the above description, the flash memory device divides the program voltage Vpgm_ramp and the pass voltage Vpass into predetermined resistance ratios, respectively, and divides the divided voltage result of the program voltage Vpgm_ramp and the divided voltage result of the pass voltage Vpass. In comparison, it has been described as controlling the application time of the program voltage Vpgm_ramp, but this is only an example, and various changes and modifications can be made without departing from the technical spirit of the present invention. It is self-evident for those with.

For example, the flash memory device according to the present invention may be configured to control the application timing of the program voltage Vpgm_ramp by comparing the level of the program voltage Vpgm_ramp and the pass voltage Vpass itself. Alternatively, the timing of applying the program voltage Vpgm_ramp may be controlled by comparing the result of dividing the level of the program voltage Vpgm_ramp with a predetermined reference voltage.

6 is a timing diagram of each control signal and a high voltage during programming according to the present invention. 7 is a view showing a change in voltage applied to a word line during programming according to the present invention.

6 and 7, a pass voltage Vpass is applied to all word lines of a block to be programmed in response to an activated pass voltage enable signal Vpass_EN. After all the word lines of the selected block are precharged by the pass voltage Vpass provided during the predetermined period, the high voltage ramp circuit 70 generates the ramp activation signals Ramp_EN <0> -Ramp_EN <generated from the controller 90. 4>), the ramped program voltage Vpgm_ramp is generated in stages. The ramped program voltage Vpgm_ramp generated at this time is monitored by the high voltage monitoring unit 65 provided in the word line drive circuit 60. As a result of the monitoring, when the level of the program voltage Vpgm_ramp is determined to be lower than the pass voltage Vpass, the word line drive circuit 60 passes the pass instead of the program voltage Vpgm_ramp, even when the program voltage Vpgm_ramp is applied. A voltage Vpass is applied to the selected word line. When it is determined that the level of the program voltage Vpgm_ramp is higher than the pass voltage Vpass, the word line drive circuit 60 applies the program voltage Vpgm_ramp to the selected word line. As can be seen in FIG. 6, the pass voltage Vpass is always maintained at a constant level even while the program voltage Vpgm_ramp is applied. Therefore, even when the program voltage Vpgm_ramp is applied, if the level of the program voltage Vpgm_ramp is lowered below a certain level for some reason, the pass voltage Vpass is transferred to the selected word line instead of the lowered program voltage Vpgm_ramp. Will be authorized. As a result, the program voltage Vpgm_ramp applied to the selected word line always has a predetermined level or more, thereby increasing the boosting efficiency and increasing the reliability of the program.

As described above, optimal embodiments have been disclosed in the drawings and the specification. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not intended to limit the scope of the invention as defined in the claims or the claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible from this. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

According to the present invention as described above, the program voltage applied to the selected word line always has a value of a predetermined level or more, so that the boosting efficiency can be increased and the reliability of the program can be increased.

Claims (13)

Applying a pass voltage to all word lines of the memory block to be programmed; Monitoring the level of the pass voltage and the level of the program voltage while the pass voltage is applied; And And applying the program voltage to a selected word line if the program voltage is higher than the pass voltage as a result of the monitoring. The method of claim 1, If the program voltage is lower than the pass voltage, applying the pass voltage to the selected word line. The method of claim 1, wherein monitoring the program voltage comprises: Dividing the pass voltage and the program voltage; Comparing the magnitudes of the partial pressure results; And And in response to the comparison result, applying one of the program voltage and the pass voltage to the selected word line. The method of claim 3, wherein And applying the pass voltage to the selected word line if the divided voltage result of the program voltage is lower than the divided voltage result of the pass voltage. The method of claim 1, The program voltage is a program voltage application method of the flash memory device, characterized in that generated by the incremental step pulse programming (ISPP) method that increases step by step for each program loop. The method of claim 5, And a program voltage for each program loop is gradually increased to a predetermined voltage level through a plurality of ramping operations. A memory cell array consisting of a plurality of memory cells; A program controller for controlling a program for the memory cells; A high voltage generator configured to generate a pass voltage and a program voltage under control of the program controller; And And a word line driver circuit for monitoring the level of the program voltage and outputting any one of the pass voltage and the program voltage to a selected word line according to the monitoring result. The method of claim 7, wherein the high voltage generating unit A high voltage generation circuit configured to generate the pass voltage and the program voltage under control of the program controller; And And a high voltage ramping circuit for gradually raising the program voltage generated from the high voltage generating circuit. The method of claim 7, wherein The program voltage is flash memory device, characterized in that generated by the incremental step pulse programming (ISPP) method that is incremented step by step. 8. The circuit of claim 7, wherein the wordline drive circuit is A first switch configured to output the pass voltage in response to a pass voltage activation signal input from the program controller; A high voltage monitoring unit for monitoring a level of the program voltage and generating a program voltage activation signal according to the monitoring result; And And a second switch configured to output the program voltage to the word line in response to the program voltage activation signal generated from the high voltage monitoring unit. The method of claim 10, And the high voltage monitoring unit deactivates the program voltage activation signal when the program voltage is lower than the pass voltage as a result of the monitoring. The method of claim 10, wherein the high voltage monitoring unit A voltage divider configured to divide the program voltage and the pass voltage; A comparator for comparing the magnitudes of the partial pressure results; A first signal output unit configured to generate the program voltage enable signal based on the comparison result; And And a second signal output unit configured to generate the pass voltage enable signal based on the comparison result. The method of claim 12, And the program voltage enable signal and the pass voltage enable signal generated from the first signal output unit and the second signal output unit have complementary values.

Images