KR20060060969A - Lcd driver, and conductive pattern on lcd pannel - Google Patents

Abstract

The present invention improves the circuit of the power input terminal for inputting a driving signal in a device for driving an LCD panel, and also improves the coupling pattern of the device and the LCD panel to suit the use of such a device. The block dim that occurs at the same time can be eliminated. In the present invention, the LCD driving device 100 is electrically coupled with a conductive pattern 400 formed on the lower glass 1 of the LCD, and is based on a driving signal input from the conductive pattern 400. An LCD driving device for outputting a driving signal for driving a light source, the device comprising: a plurality of first input bumps 110 for inputting a driving signal, and a plurality of second input bumps electrically coupled to the first input bumps, respectively; And 120, wherein at least two of the first input bumps are coupled through resistors R1 to R4 having different resistance values.

LCD, block dim, resistor

Description

Device for driving LCD and conductive pattern of LCD panel for combining the same {LCD driver, and conductive pattern on LCD pannel}

1 is a configuration diagram showing a general module configuration of a TFT LCD.

FIG. 2 is a view showing a part of a combination of a base film 5 and a lower glass 1 each having a gate driving device 51 in FIG.

3 is a configuration diagram showing a coupling relationship between an active matrix circuit and a driving circuit constituting an LCD panel;

4 and 5 are circuit diagrams showing an example of the configuration of an output circuit for outputting a gate driving signal from the gate driving device 51;

6 is a block diagram showing the configuration of a drive signal input circuit of the LCD driving device according to an embodiment of the present invention.

FIG. 7 is a configuration diagram showing a main part structure in the case of configuring an LCD panel using the gate driving device 100 shown in FIG. 6; FIG.

FIG. 8 is a diagram showing the principal parts of another structural example in the case of configuring an LCD panel using the gate driving device 100 shown in FIG. 6; FIG.

*** Brief description of the main parts of the drawing ***

1: lower glass, 100: LCD driving device,

200: base film, 300: conductive pattern,

400: challenge pattern.

The present invention relates to a driving circuit for driving a liquid crystal display (LCD) panel. In particular, the present invention improves the circuit of the power input terminal for inputting a driving signal in the driving device of the LCD panel, and also improves the coupling pattern of the driving device and the LCD panel to be suitable for use of such driving device. It is to solve the block dim phenomenon that occurs during the driving of.

In general, LCDs, especially TFT (Thin Film Transistor) LCDs, are widely used due to their advantages such as large size, thin thickness, light weight, and low power consumption. 1 is a configuration diagram showing a module configuration of a TFT LCD which is currently commonly used. In the drawings, reference numerals 1 and 2 denote lower and upper glasses constituting a liquid crystal panel, respectively, and reference numeral 3 denotes a driving power source, a gate driving signal, a data driving signal, and the like with respect to the liquid crystal panel, specifically, the lower glass 1. It is a printed circuit board for supply. On this printed circuit board 3, a plurality of driving devices for driving the liquid crystal panel, including the DC-DC converter 301 and the controller 302, are provided.

The printed circuit board 3 and the lower glass 1 are electrically and physically coupled to each other through a predetermined connection member. The connecting member 4 is made of a flexible film. On the connecting member 4, the data driving device 401 for the liquid crystal panel is mounted by, for example, a flip chip method. Many conductive patterns are formed. These conductive patterns electrically couple data applied from the printed circuit board 3 to the data driving device 401, and output data driving signals output from the data driving device 401 onto the lower glass 1. As shown in FIG. Electrically coupled to a data line (not shown) formed therein.

Meanwhile, the gate driving signal applied from the printed circuit board 3 is applied to the lower glass 1 through at least one of the plurality of connection members 4, and the conductive pattern for the gate signal formed on the lower glass. It is electrically coupled to the base film 5 via 11.

The base film 5 is made of a flexible material like the connection member 4 described above, and the device for driving the gate of the liquid crystal panel is mounted in a flip chip method, for example, and the conductive pattern 11 on the lower glass 1 is provided. And a conductive pattern 52 for electrically coupling the gate driving device 51 with each other.

Examples of driving signals for gate driving of the liquid crystal panel include power supplies such as VDD (2.5 to 5 V), VSS (0 V), VGH (+15 to +30 V), VGL (-4 to-10 V), and CLK, DIO1, and DIO2. , OE, DIR, etc., these gate driving signals are commonly used in each gate driving device 51, so that the gate driving device 51 outputs the input gate driving signals again. The structure applied to the gate drive device 51 of the subsequent stage is employ | adopted.

FIG. 2 is a view illustrating a part of a coupling configuration of the base film 5 and the lower glass 1 each having the gate driving device 51 in FIG. 1. As described above, the driving signals for driving the gate are formed on the first base film 5-1 through the conductive pattern 11-1 formed on the lower glass 1. These driving signals are then supplied to the internal circuit of the gate driving device 51-1 through the first input bump 511-1 of the first gate driving device 51-1. In addition, the driving signals input to the first input bump 511-1 are again output through the second input bump 511-2 to form a second conductive pattern 52 formed on the first base film 5-1. It is coupled to the conductive pattern 11-2 on the lower glass 1 through -2).

Subsequently, the driving signals coupled to the conductive pattern 11-2 are connected to the first conductive pattern 52-3 on the second base film 5-2 in the same manner as in the first base film 5-1. ) Is coupled to the first input bump 511-1 of the second gate driving device 51-2. Subsequently, the driving signals input to the first input bump 511-1 are supplied to the internal circuit of the second gate driving device 51-2 and are again output through the second input bump 511-2. The second conductive pattern 52-4 on the second base film 5-2 and the conductive pattern 11-3 on the lower glass 1 are supplied to the later gate driving device.

However, in the method of sequentially connecting the gate driving device 51 to the drive signal in series as described above, the conductive pattern 511 formed on the base film 5 and the conductive formed on the lower glass 1 are provided. The sheet resistance of the pattern 11 causes the potential of the driving signal to gradually decrease as it passes through the gate driving device 51. That is, a difference occurs in the level of the drive signal applied to each drive device 51. Then, this results in a difference between the driving voltages supplied from the driving device 51 to the LCD panel, so that parts A, B, and C driven by the respective gate driving devices 51 in the LCD panel of FIG. The difference in luminance, so-called block dim phenomenon, occurs.

Accordingly, an object of the present invention is to provide an LCD driving device capable of eliminating the block dim phenomenon generated in an LCD panel by a simple method.

In addition, another object of the present invention is to provide a conductive pattern of the LCD panel to efficiently combine the LCD driving device having the above-described driving signal combining circuit with the lower glass of the LCD panel.

The LCD driving device according to the first aspect of the present invention for realizing the above object is electrically coupled with a conductive pattern formed on the lower glass of the LCD, and drives the LCD panel based on a driving signal input from the conductive pattern. An LCD driving device for outputting a driving signal for a device, comprising: a plurality of first input bumps for inputting a driving signal, and a plurality of second input bumps electrically coupled to the first input bumps, respectively, The first input bumps may be coupled through at least two resistors having different resistance values.

In addition, the LCD driving device according to the second aspect of the present invention for realizing the above object is electrically coupled with a conductive pattern formed on the lower glass of the LCD, the LCD panel based on the driving signal input from the conductive pattern An LCD driving device for outputting a driving signal for driving a light source, comprising: a plurality of first input bumps for inputting a driving signal, and a plurality of second input bumps electrically coupled to the first input bumps, respectively; At least two first input bumps may be allocated for a single driving signal input, and input bumps allocated for the same driving signal input may be coupled in parallel through resistors having different resistance values. .

The resistance value of the resistor coupled to the first input bump may be set to an integer multiple of the resistance value of the conductive pattern of the lower glass.

The first input bump coupled to the resistor may be an input bump for driving signals for driving the gate of the LCD panel.

In addition, the device for driving the LCD is mounted on the base film, characterized in that coupled to the conductive pattern of the lower glass through a conductive pattern formed on the base film.

In addition, the conductive pattern of the LCD panel for coupling the device for driving the LCD according to the third aspect of the present invention for realizing the above object is to combine a plurality of devices for driving the LCD on the lower glass, formed on the lower glass In the LCD module to supply a drive signal to the device through a conductive pattern, the conductive pattern is characterized in that the at least one drive signal is configured to be coupled to different signal input terminals of the device.

The conductive pattern may further include a dummy pattern coupled in parallel with the conductive pattern.

Hereinafter, an embodiment according to the present invention will be described with reference to the drawings.

First, the basic concept of the present invention will be described.

3 is a configuration diagram showing a coupling relationship between an active matrix circuit and a driving circuit constituting an LCD panel. The same reference numerals are attached to the same parts as those of FIGS. 1 and 2 described above with reference to FIG. 3. In FIG. 3, a plurality of data lines S: S1, S2,... And gate lines G: G1, G2,... Are arranged in a matrix shape on the lower glass of the LCD panel, in particular, the LCD panel. The FET 30 and the capacitor 31 for driving each pixel of the panel are coupled.

In addition, a gate driving device 51 (51-1, 51-2) for driving the gate line is coupled to the gate line G, and a data driving device 401 for outputting a gray level signal to the data line S. : 401-1, 401-2) are combined. That is, the gate lines G1, G2, ..., Gn are coupled to the first gate driving device 51-1, and the gate lines G (n + 1), G (n + 2), ..., G2n Is coupled to the second gate driving device 51-2, and the data lines S1, S2, ..., Sn are coupled to the first data driving device 401-1, and the data line S (n + 1), S (n + 2), ..., S2n are coupled to the second data driving device 401-2. In the drawing, only two gate driving devices 51 and data driving devices 401 are shown, but the number of these devices 51 and 401 will vary depending on the size of the LCD panel.

In the above configuration, the gate driving device 51 selects and drives the gate lines sequentially, and the data driving device 401 outputs a gray level signal corresponding to the selected pixel.

4 shows an example of the configuration of an output circuit for outputting a gate driving signal from the gate driving device 51, which for example drives the output circuit 514 for driving the nth gate line and the (n + 1) th gate line. The output circuit 515 is selectively shown.

In the gate driving signal output circuit of FIG. 4, for example, an N-channel FET T1 and a P-channel FET T2 are connected in series, and a VGH power of +20 V is coupled to the drain of the N-channel FET T1, for example. For example, a -5V VGL power supply is coupled to the drain of the P-channel FET T2. These VGH and VGL power supplies are sequentially applied from the printed circuit board 3 to the gate driving device 51 as described in FIG. In addition, the FETs T1 and T2 are electrically coupled to the gate line G while the sources are interconnected, while the gates are coupled to the internal circuit of the gate driving device 51 while the gates are interconnected.

The gate driving signal output circuits 514 and 515 turn on the N-channel FET T1 when high-level driving data is input from the internal circuit and turn off the P-channel FET T2 to turn off the + 20V VGH power supply. When the low level driving data is input from the internal circuit as the gate driving signal, the N-channel FET T1 is turned off, and the P-channel FET T2 is turned on, and the -5V VGL power supply is gate driven. It is coupled to the gate line as a signal.

When a gate driving signal of + 20V is output from the gate driving device 51, the FET 30 coupled to the gate line G corresponding to the driving signal is set to an on state, and the data is driven from the data driving device 401. The gray level signal output through the data line is stored in the capacitor 31. One end of the capacitor 31 is coupled to the source end of the FET 30, and the other end thereof is coupled to the gate line G. In this case, the gate line to which the gate of the FET 30 is coupled and the gate line to which the capacitor 31 is coupled are not the same. That is, if the gate line to which the FET 30 is coupled is the n-th gate line, the capacitor 31 is coupled to the (n-1) th gate line. Therefore, if the gate line to which the gate of the FET 30 is coupled is driven with a driving signal of VGH, that is, + 20V, the gate line to which the capacitor 31 is coupled is driven to VGL, that is, -5V. Therefore, the level of the gradation signal charged in the capacitor 31 is set to VGL, that is, a relative potential with -5V as the reference potential.

In FIG. 3, since the gate lines G1, G2,..., Gn are all driven by the first gate driving device 51-1, VGH supplied to each gate line G1, G2,..., Gn is provided. And VGL are set to the same voltage level. In addition, since the gate lines G (n + 2), G (n + 3), and G2n are all driven by the second gate driving device 51-2, each gate line G (n + 1), VGH and VGL supplied to G (n + 2), ..., G2n are set to the same voltage level.

However, as described with reference to FIGS. 1 and 2, the driving power input to the second gate driving device 51-2 is applied from the first gate driving device 51-1. The driving power output from the first gate driving device 51-1 to the second gate driving device 51-2 is different from the second conductive pattern 52-2 on the base film 5-1 in FIG. 2. The input is input to the second gate driving device 51-2 via the conductive pattern 11-2 on the lower glass 1 and the first conductive pattern 52-3 on the base film 5-2. Here, the conductive pattern 52 on the base film 5 is negligible as about 0.5 mW with respect to the line width of 25 micrometers. However, the conductive pattern 11 formed on the lower glass 1 is about 50 mV and cannot be ignored.

FIG. 5 is an equivalent view of the output circuit of the gate driving device 51 when the sheet resistance caused by the conductive pattern 11 is considered. In FIG. 5, the same reference numerals are added to the same parts as in FIG. 4 described above.

In FIG. 5, the output circuit 514 driven by the first gate driving device 51-1 is substantially the same as the configuration of FIG. 4. However, in the case of the output circuit 515 driven by the second gate driving device 51-2, a predetermined resistor R is coupled to the drain terminals of the FETs T1 and T2. This resistance R corresponds to the sheet resistance of the conductive pattern 11 formed on the lower glass 1 mentioned above.

In the output circuit 515, the VGH power supply is used to drive the FET 30 formed in each pixel, and thus does not significantly affect the image quality of the LCD panel. However, since the VGL power supply is used as the reference potential of the capacitor 31 formed in each pixel, the addition of the resistor R described above causes the reference potential of the capacitor 31 to fluctuate. By the addition of the resistor R, the potentials of the VGL output from the first gate driving device 51-1 and the second gate driving device 51-2 are set to be different from each other. That is, gate lines G1, G2,..., Gn driven by the first gate driving device 51-1 and gate lines G (n) driven by the second gate driving device 51-2. The reference potentials of +1), G (n + 2), ..., G2n) are set differently. Therefore, the screen gradation on the LCD panel output by the same gradation signal is divided into the gate lines G1, G2, ..., Gn and the gate lines G (n + 1), G (n + 2), ..., G2n. Block dim occurs differently.

This problem is not limited between the first and second gate driving devices 51-1 and 51-2 described above, and all LCD driving devices cascaded through the conductive pattern 11 on the lower glass 1. The same occurs for.

In the present invention, the above-mentioned block dim phenomenon is eliminated by setting the drive power input to all LCD driving devices cascaded to the same level. The present invention can be equally applied to all driving power sources used for driving an LCD, but the following description will be given by taking the case of applying the present invention to a VGL power supply for the sake of simplicity.

6 illustrates a main configuration of a gate driving device 100 according to an embodiment of the present invention. In FIG. 6, the gate driving device includes a first input bump 110 for inputting driving signals applied from the lower glass 1 and a driving signal input to the first input bump 110 as in the prior art. A second input bump 120 is provided for outputting a rear gate driving device. The first input bump 110 and the second input bump 120 are electrically coupled to each other through, for example, the metal line 130. In addition, the first and second input bumps 110 and 120 may be electrically coupled with a conductive pattern on the base film on which the gate driving device is mounted.

On the other hand, in this embodiment, a plurality of input bumps 110-1 to 110-4 are allocated for one drive signal, for example, a VGL signal, and in this embodiment. These input bumps 110-1 to 110-4 are coupled in parallel through resistors R1 to R4, respectively, and the signal of the coupling node is input to the internal circuit as a VGL signal.

Here, the resistances R1 to R4 are set by the sheet resistance value of the conductive pattern formed on the lower glass. For example, when the sheet resistance value is "R", the resistors R1 to R4 are each The value is set to an integer multiple of the sheet resistance value, such as "R", "2R", "3R", and "4R", respectively.

FIG. 7 is a configuration diagram showing a main part structure in the case of configuring an LCD panel using the gate driving device 100 described above. In FIG. 7, the case where three gate drive devices 100 are used is shown. At this time, the number of the gate driving device 100 will vary depending on the size of the LCD panel. In Fig. 7, the same reference numerals are added to the same parts as in Fig. 6 described above.

In FIG. 7, the gate driving devices 100: 100-1, 100-2, and 100-3 are mounted on a base film 200: 200-1, 200-2, and 200-3 in a flip chip manner. Predetermined conductive patterns 300-1, 300-2, and 300-3 are formed on the base film 200. One end of the conductive pattern 300 is electrically connected to the input bumps 110 and 120 of the gate driving device 100, and the other end thereof is extended to an end portion in contact with the lower glass 1. In FIG. 7, only one driving signal, for example, a VGL signal is input, and a conductive pattern for inputting another driving signal is omitted for simplicity. Here, the first to third gate driving devices 100-1 to 100-3 and the first to third base films 200-1 to 200-3 have substantially the same configuration.

Meanwhile, conductive patterns 400 (400-1 to 400-3) electrically coupled to the conductive patterns 300 on the base film 200 are formed on the lower glass 1. Here, the resistance R displayed on the conductive pattern 400 is equivalent to the sheet resistance of the conductive pattern 400. The first conductive pattern 400-1 on the lower glass 10 is to couple a driving signal, eg, a VGL signal, applied to the printed circuit board 30 to the first base film 200-1 in FIG. 1. The second conductive pattern 400-2 is for coupling the driving signal output from the first base film 200-1 to the second base film 200-2, and the third conductive pattern 400-3. Is for coupling the driving signal output from the second base film 200-2 to the third base film 200-3.

The conductive pattern 400 formed on the lower glass 1 is selectively coupled to a specific conductive pattern of a plurality of conductive patterns 300 provided on the base film 200. At this time, the coupling between the conductive pattern 400 on the lower glass 1 and the conductive pattern installed on the base film 200 will vary depending on the installation position of the base film 200.

The driving signal applied to the base film 200 through the conductive pattern 400 on the lower glass 1 is coupled to the first input bump 110 of the gate driving device 100 through the specific conductive pattern 300. In addition, the combined driving signal is outputted through the second input bump 120 and input to the internal circuit through the resistors R1 to R4 coupled to the corresponding input bump 110. As described above, the resistances R1 to R4 are set differently from each other and are set to an integer multiple of the resistance value R of the conductive pattern 400 on the lower glass 1. That is, the resistors R1 to R4 are set to an integer multiple of the sheet resistance value R, such as "R", "2R", "3R", and "4R", respectively.

In the above structure, the conductive pattern 400 on the lower glass 1 is set differently from the conductive pattern 300 on the base film 200 and their bonding positions. In other words, the driving signal input to the gate driving device 100 is input to the internal circuit through the resistors R1 to R4 having different resistance values. Therefore, in consideration of the resistance value R on the lower glass 1 that couples the base films 200, the base signal 300 is located closer to the drive signal applied from the printed circuit board. The conductive pattern 400 is formed at a predetermined position on the lower glass 1 so as to be input through the resistors R1 to R4 having a large resistance value.

Considering the third gate driving device 100-3 in FIG. 7, the driving signals applied to the third gate driving device 100-3 are first and second base films 100-1, 100-2 and the second and third conductive patterns 400-2 and 400-3 on the lower glass 1. Therefore, when ignoring the resistance values of the conductive patterns 300-1 and 300-2 formed on the first and second base films 100-1 and 100-2, the third gate driving device 100- On the signal path of the driving signal applied to 3), a resistance component of "2R" in which resistance values of the conductive patterns 300-1 and 300-2 are added is present. Since the driving signal input to the third gate driving device 100-3 is input to the internal circuit through the resistor R 2 having a resistance value of “2R”, the third gate driving device 100-3 is provided. In the signal path of the drive signal input to the internal circuit of the circuit, a total of "4R" resistance components exist.

Subsequently, the driving signal applied to the second gate driving device 100-2 is applied through the second conductive pattern 400-2 on the first base film 200-2 and the lower glass 1. A resistance component of "R" due to the second conductive pattern 400-2 is present on the signal path of the signal. Since the driving signal input to the second gate driving device 100-2 is input to the internal circuit through the resistor R3 having a resistance value of “3R”, the driving signal of the second gate driving device 100-2 is reduced. A total of "4R" resistance components exist on the signal path of the drive signal input to the internal circuit.

The driving signal applied to the first gate driving device 100-1 is directly input through the first conductive pattern 400-1 on the lower glass 1. Since the driving signal input to the first gate driving device 100-1 is input to the internal circuit through the resistor R4 having a resistance value of “4R”, the driving signal of the first gate driving device 100-1 is increased. A total of "4R" resistance components exist on the signal path of the drive signal input to the internal circuit.

That is, resistance components of "4R" are all present on the signal paths of the drive signals input to the internal circuits of the first to third gate driving devices 100-1 to 100-3. Accordingly, since the levels of the driving signals input to the first to third gate driving devices 100-1 to 100-3 are set to be the same, the block dim phenomenon on the LCD panel caused by the level difference of the driving signals is eliminated. Will be removed.

Meanwhile, FIG. 8 illustrates a configuration according to another embodiment of the present invention. In FIG. 8, the same reference numerals are assigned to parts substantially the same as in FIG. 7, and detailed description thereof will be omitted.

In FIG. 8, a predetermined dummy pattern 500 is formed on the conductive pattern 400 formed on the lower glass 1. As described above, the resistors R1 to R4 coupled to the driving signal input terminal of the gate driving device 100 preferably have a resistance value ("R") of the conductive pattern 400 formed on the lower glass 1. It is set to an integer multiple of). Since the resistors R1 to R4 are fixedly set when the device is manufactured, it is difficult to change the resistance values thereafter. In contrast, the conductive pattern 400 formed on the lower glass 1 may have a change in resistance due to problems in design and manufacturing.

In the embodiment shown in FIG. 8, a dummy pattern 500 is formed in parallel with the conductive pattern 400, and a wiring portion 500-1 of the conductive pattern 400 coupled in parallel with the dummy pattern 500 as necessary. ) By using a laser trimming technique to change the length of the conductive pattern 400 coupled between the base films 200 so that the resistance value of the conductive pattern 400 can be varied.

In the above, the Example of this invention was described. However, the present invention is not limited to the above-described embodiments and can be carried out in various modifications without departing from the technical gist of the present invention.

For example, in the above-described embodiment, the case where the present invention is applied to a VGL signal for a gate driving device has been described. However, the present invention can be applied in the same manner to any other drive signal whose fluctuation in signal level may be a problem. In addition, the present invention can be applied and implemented in the same manner to a plurality of data driving devices coupled in a cascade manner.

In addition, the shape and number of the dummy pattern 500 in the above-described embodiment of FIG. 8 is not limited to a specific example, and may be implemented in various forms.

As described above, according to the present invention, the LCD panel block dim is changed by a simple method of partially changing the configuration of the drive signal input terminal of the driving device for driving the LCD, and also changing the coupling method of the device and the lower glass of the LCD. The phenomenon can be effectively removed.

Claims (7)

An LCD driving device which is electrically coupled with a conductive pattern formed on a lower glass of an LCD and outputs a driving signal for driving an LCD panel based on a driving signal input from the conductive pattern. A plurality of first input bumps for inputting a drive signal; A plurality of second input bumps each electrically coupled with the first input bumps, And at least two first input bumps are coupled through a resistor having a different resistance value. The method of claim 1, And the resistance value of the resistor coupled to the first input bump is set to an integer multiple of the resistance value of the conductive pattern of the lower glass. The method of claim 1, And a first input bump coupled to the resistor is an input bump for a drive signal for driving a gate of the LCD panel. The method of claim 1, And the LCD driving device is mounted on the base film, and coupled to the conductive pattern of the lower glass through a conductive pattern formed on the base film. An LCD driving device which is electrically coupled with a conductive pattern formed on a lower glass of an LCD and outputs a driving signal for driving an LCD panel based on a driving signal input from the conductive pattern. A plurality of first input bumps for inputting a drive signal; A plurality of second input bumps each electrically coupled with the first input bumps, At least two first input bumps are allocated for a single drive signal input, and the input bumps allocated for the same drive signal input are coupled in parallel through resistors having different resistance values. Driving device. In the LCD module for coupling a plurality of devices for driving the LCD on the lower glass, and supplying a drive signal to the device through a conductive pattern formed on the lower glass, The conductive pattern is a conductive pattern of the LCD panel for coupling the LCD driving device, characterized in that the at least one driving signal is formed to be coupled to different signal input terminals of the device. The method of claim 6, The conductive pattern is a conductive pattern of the LCD panel for coupling the LCD driving device, characterized in that further comprising a dummy pattern coupled in parallel with the conductive pattern.

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