KR20060055595A - Simplification apparatus of test access port for chip test - Google Patents

Abstract

The present invention provides a device for simplifying a test access port for chip testing to reduce the number of terminal pins of a test access point (TAP) applied to a boundary scan device to secure reliability in chip test operation. To this end, the present invention is provided with a test clock of a basic bit for serial communication through a TCK (Test Clock) terminal pin in a test access port (TAP) applied to a boundary scan device for chip testing. Through the Test Mode Select (TMS) terminal pin, the TDI (Test Data Input) function, which receives command code and test data serially for chip test, can be performed in parallel. According to the TMS value for state transition, a data register or instruction is used. Determining register (Instruction Register), selecting A (TMS_1) for TMS function or B (TDI_1) for TDI function, and outputting test result data through TDO (Test Data Out) terminal pin. Characterized in that made to.

Chip Test, Boundary Scan, TAP, TMS, TDI, TDO

Description

SIMPLIFICATION APPARATUS OF TEST ACCESS PORT FOR CHIP TEST}             

1 is a view showing the configuration of a conventional boundary scan (Boundary Scan) apparatus of the conventional IEEE Std 1149.1-1990 standard,

2 is a diagram illustrating a control state of a TAP controller of a test access port;

FIG. 3 is a diagram illustrating a pin configuration of a test access port (TAP) applied to the boundary scan device shown in FIG. 1;

4 is a view showing a simplified pin configuration in the apparatus for simplifying a test access port for chip test according to the present invention;

5 is a diagram illustrating an internal configuration of a test access port illustrated in FIG. 4;

FIG. 6 is a diagram illustrating a detailed configuration of a select logic unit shown in FIG. 5;

7 is a flowchart illustrating an operation state of a JTAG logic, a TAP controller, and a selection logic unit according to an exemplary embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>                 

10: test access port controller, 20: select logic section,

30: JTAG logic, 40, 50, 60: first to third blocks,

42: demux, 52: instruction register counter,

62: counter part, 64: mux.

The present invention relates to a device for simplifying a test access port for chip test, and more particularly, a pin of a test access port applied to a boundary scan device of the IEEE Std 1149.1-1990 standard for chip test of various core logic or peripheral devices. A device for simplifying a test access port for chip testing to simplify configuration.

As is well known, the boundary scan device (ie, JTAG; Joint Test Access Group) of the IEEE Std 1149.1-1990 standard is for chip testing of various core logic or peripheral devices, and is used for needle test as shown in FIG. Place a test data register in the form of shift registers with a number of boundary scan cells around the core logic, and a test access port (TAP), a TAP controller, and an instruction register. In addition, by analyzing the output value of the TDO (Test Data Out) output in series through the TMS (Test Mode Select) of the serial input and the TDI (Test Data In) input, By verifying the interconnection status with other circuit elements, various codes and data can be loaded into the flash memory around the chip.

The instruction register and test data register constituting the boundary scan device are composed of cells of different paths, and commonly, the desired instruction code (Instrution) is transmitted through the TDI terminal in the TAP controller's Shift-IR or Shift-DR state. Code or data can be input, and after the code or data is input as long as the length of the register, the instruction code and data just input can be applied in the updated state out of the shift state.

In Fig. 1, the instruction register is composed of at least two bits (Bit), so that the instruction code is loaded in the Shift-IR state of the TAP controller, and the mode (that is, the test mode or the normal mode) corresponding to the loaded instruction code is selected. The decoder decodes one of a plurality of test data registers between the TDI and the TDO. The test data register refers to all registers except the instruction register, among which a boundary scan register and a bypass register ( Bypass registers are necessary and optional identification registers are required.

The boundary scan register constituting the test data register is a register existing between the external I / O pin and the internal core logic. The length of the register may vary according to the number of external I / O pins of the chip, and one I / O The pin usually consists of one to three boundary scan cells. The signal of the external pin of the chip may be brought into the boundary scan cell and checked through the TDO terminal, and a specific pattern or data may be input to the desired method scan cell through the TDI terminal and sent to the outside of the chip. It is used to check open / short of chip external pin or to upload code or data to adjacent flash memory.It is applicable to EXTEST, INTEST, SAMPLE / PRELOAD among the instruction codes loaded in instruction register. When code is loaded, it is chosen between TDI and TDO.

The identification register constituting the test data register has 32 bits, and is used to check chip manufacturer, part number, and version information, and to check whether the correct chip is mounted while mounting the chip on the PCB. It is possible to select between TDI and TDO when the code corresponding to the IDCODE among the instruction codes loaded in the instruction register is loaded.

In FIG. 1, the bypass register is composed of 1 bit, which directly connects the TDI and the TDO by providing the shortest serial path between the chip's TDI and the TDO at the time of register selection. It is used to reduce the test execution time when the chip is to be bypassed. When the code corresponding to the bypass is loaded among the instruction codes loaded in the instruction register, it is selected between TDI and TDO.

The TAP controller transitions to each state according to a TMS value (that is, at each rising edge of the TCK) serially input to 16 finite state machines (FSMs) to determine a corresponding data register (DR) or an instruction register (IR). In addition, nine control signals are generated to perform the actions for each state in the selected register.

That is, FIG. 2 is a diagram illustrating a control state of a TAP controller of a test access port. According to FIG. 2, an initial state of IEEE 1149.1 logic is created in a test-logic reset, and in any of 16 states, FIG. If TMS remains high while five TCKs are input, it enters this state, and the select signal is placed between TDI and TDO at the moment it enters the state of Select-DR-Scan. Make sure that the test data register is selected.

The Shift-DR register allows the serial input of a signal to the data register selected from the test data registers via the TDI terminal, and creates a state in which the signal can move from each cell in the register to the next neighboring cell. At the same time, a signal may be output to the outside through the TDO terminal. While the TMS remains low, it stays in this state, which is typically the length of the selected register among the test data registers.

Update-DR is a meaningful signal from the actual boundary scan register among the test data registers, which allows the pattern / data inputted serially to the boundary scan register through the TDI terminal to be applied to the chip's external pin or internal core. Select-IR-Scan allows the select signal to select an instruction register between TDI and TDO upon entering that state.

Shift-Instruction Register (Shift-IR) allows the serial input of instruction code through the TDI terminal into the instruction register, creating a state where a signal can be passed from each cell in the register to the next neighboring cell, while the TDO Allow the signal to come out through the terminal. It stays in this state while the TMS remains "low" and usually stays in this state for the length of the instruction register.

Update-Instruction Register (Update-IR) is a meaningful signal in the instruction register.Instruction code inputted serially into the instruction register through the TDI terminal is applied to select the test mode or normal mode, and the test data register is applied by the decoder logic. Have them choose one.

In the shift-instruction register or shift-data register state, serial input through a TDI terminal is possible, a signal can be moved from a current cell to a neighboring next cell, and a result can be output to a TDO terminal by an enable signal. do.

Here, the test access port (TAP) is, as shown in Figure 3, TMS (Test Mode Select), TDI (Test Data In), TCK (Test Clock), TRST (Test Reset), TDO (Test Data Out) The TCK is applied as a basic bit clock for serial communication, the TMS notifies the TAP controller of the transition to the next state, and the TDI is a serial input of command and test data. The TDO allows the result data of the serial output returned after the test to be output, and the TRST is configured to input an active low signal as an initialization signal and is installed as an optional terminal pin.

However, the test access port of this boundary scan device has a total of five terminal pins of TDI, TDO, TCK, and TMS, including the TRST pin.However, the boundary scan test of the target PCB can be used to check for open or short fault conditions. In order to check the soldering status or to upload codes or data to the flash memory through the on-board program method, the test access port of the chip meeting the IEEE Std 1149.1 standard must be connected to the test device. In order to connect to a terminal using a connector or a test point (TP), it is generally attempted to connect a terminal pin using a connector or a test point. If any one of the two terminal pins causes a connection problem, IEEE Std 1149.1 There is a disadvantage that yonghan test becomes impossible.

Therefore, at present, efforts to secure reliability in a test operation by reducing terminal pins of a test access point (TAP) are required.

Accordingly, the present invention has been made in view of the above-described conventional situation, and an object thereof is to reduce the number of terminal pins of a test access point (TAP) applied to a boundary scan device and to perform a chip test to secure reliability in chip test operation. It is to provide a device for simplifying the test access port.

Another object of the present invention is to provide a conventional test data input (TDI) terminal pin with a test mode select (TMS) terminal pin in a test access port, thereby reducing the number of terminal pins. It is to provide a simplified device.

In order to achieve the above object, according to the present invention, in the test access port applied to the boundary scan device for chip testing, the test access port is operated by a test clock from the TCK terminal pin, and according to the TMS value through the TMS terminal pin. A test access port controller which transitions to each state during the state to determine a data register or instruction register, and controls to perform an operation according to each state in a selected register; and a command code or test data through the TMS terminal pin. In response to the state transition of the shift-instruction register (Shift-IR) or the shift-data register (Shift-DR) under the control of the test access port controller, the instruction is executed by a TDI function parallel to the TMS terminal pin. The instruction code and the length of the register or data register A chip comprising a selection logic unit for inputting data and a JTAG logic unit for inputting test data through a TDI function parallel to the TMS terminal pin and outputting the result data according to a test result through the TDO terminal pin. Provides a simplified device for test access ports for testing.

Hereinafter, the present invention configured as described above will be described in detail with reference to the accompanying drawings.

That is, FIG. 4 is a diagram illustrating a simplified pin configuration in the apparatus for simplifying a test access port for chip test according to the present invention.

As shown in FIG. 4, the apparatus for simplifying a test access port includes four terminal pins of TMS (Test Mode Select), TCK (Test Clock), TRST (Test Reset), and TDO (Test Data Out). When the TRST terminal pin used as an optional terminal pin is excluded, a total of three terminal pins are configured, and the TMS terminal pin performs a function performed by a conventional TDI terminal pin in parallel.

Next, FIG. 5 is a diagram showing an internal configuration of the test access port shown in FIG. 4, wherein the test access port has a magnetic state therein according to a value from a TMS terminal pin input in series and a rising edge clock of the TCK. TAP controller 10 that transitions to each state to determine data registers or instruction registers, and generates nine control signals that can perform operations for each state in the selected register, and supports TMS signals and conventional TDI According to a function selected by the selection logic unit 20 and the TDI_1 from the selection logic unit 20 to selectively generate a TMS_1 signal or TDI_1 to provide to the TAP controller 10 and the JTAG logic 30 It consists of a JTAG logic section 30 for serially outputting a TDO value.

As shown in FIG. 6, the selection logic unit 20 may include a first block 40 for selectively outputting signals through the TMS terminal pins to A (TMS_1) and B (TDI_1), and the TMS terminal. A second block 50 which generates an A or B signal when the TAP controller 10 moves in a portion related to the instruction register IR among the portions that internally select the signal from the pin as A (TMS_1) or B (TDI_1). ), A third block 60 for generating an A or B selection signal when the TAP controller 10 moves in a portion related to the test data register DR.                     

Here, the instruction register (IR) and the data register (DR) to distinguish between the second block 50 and the third block 60 is basically the TAP controller 10 the instruction register (IR) and the test data register This is because the output signal is generated by separating (DR).

The first block 40 transmits an input signal from the TMS terminal pin to TMS_1 or A according to a signal for selecting A (TMS_1) or B (TDI_1) from the second block 50 and the third block 60. And a demux 42 for changing the function to TDI_1.

Here, enabling the single TMS terminal to be selectively used as a TDI is used by the TMS to change the modes of the 16 states of the TAP controller, and the TDI is shift-instruction register (Shift-IR) and shift-data during that mode. Since the TMS can be used only in the register (Shift-DR) state, the TMS can be changed from the 16 states to the shift-instruction register (Shift-IR) or the shift-data register (Shift-DR). After that, you can change the TDI function, input the desired register length serially, and then use TMS again.

That is, in the first block 40, the state is changed to the shift-instruction register (Shift-IR) or the shift-data register (Shift-DR) in the state of operating in TMS as the default (Operation). After that, the pattern / data is input as much as the register length, and then TMS is operated.

When the TAP controller 10 enters the shift-instruction register (Shift-IR) state and the " TMS2TDI_IR " signal is generated, the second block 50 selects B (TDI_1) and simultaneously starts the counter start ( Counter Start) signal is generated to operate the counter (CNT_IR) 52 for the instruction register to operate as B (TDI_1), input the instruction code as long as the desired instruction register length, and then input the counter by the preset number. Generates a signal to select A (TMS_1) by generating a counter end signal.

Herein, the instruction register counter CNT_IR is configured to generate a signal for selecting A after counting the length of the instruction register, and the "TMS2TDI_IR" signal is a shift-instruction among the output signals of the TAP controller 10. A register (Shift-IR) signal can also be used.

When the "TMS2TDI_DR" signal is generated according to the shift-data register (Shift-DR) state of the TAP controller 10, the third block 60 selects B (TDI_1) to generate a counter start signal. A plurality of counters (CNT_DR) for the data registers constituting the section 62 are operated to input patterns / data as long as the desired data register length, and then any one of the plurality of counters is selected in the mux 64 and the counter is After a predetermined number of inputs, a counter end signal is generated to generate a signal for selecting A (TMS_1) again.

Here, the data register counter CNT_DR is configured to generate a signal for selecting A after counting the length of the corresponding data register, and the "TMS2TDI_DR" signal is shifted out of the output signal of the TAP controller 10. Data register (Shift-DR) signals can also be used.

Since the counter 62 has a different counting length for each data register, the counter 62 has a plurality of counters CNT_DR. As a counter for a boundary scan register constituting the test data register, a bypass register, a recognition register, etc. Each of them is configured to be driven by the counter start signal and counted by a desired length, and then a counter end signal is generated to generate a signal for selecting A (TMS_1) again.

The mux 64 selects a counter select signal CNT_Select that selects one of a plurality of counter CNT_DR signals, such that one data register among a plurality of test data registers is selected by a decoder of an instruction register. It is used as an output signal of a decoder.

Next, the operation of the present invention will be described in detail with reference to the flowchart of FIG. 7.

That is, FIG. 7 is a flowchart illustrating an operation state of JTAG logic, a TAP controller, and a selection logic unit according to an exemplary embodiment of the present invention.

First, the JTAG logic 30 is initialized by generating a clock five or more times through the TCK terminal pin while applying a "low" signal to the TRST terminal pin or a "high" signal to the TMS terminal pin. S1-1), the TAP controller 10 maintains the test logic in the reset state while the TMS terminal pin is the "high" signal or the TRST terminal pin is the "low" state after the initial state (step S2-1), The selection logic unit 20 selects A (TMS_1) while operating as a TMS terminal in an initial state (step S3-1).

In this state, the JTAG logic 30 selects an instruction register and inserts an instruction code related to a test to be performed through the TDI among the prepared instruction codes (step S1-2), and the TAP controller 10 clocks the clock of the TCK. At this moment, from "low" to "high", 0-> 1-> 1-> 0-> 0 is applied to the TMS, which leads to the shift-instruction register (Shift-IR) state. (Step S2-2), TMS2TDI_IR from the TAP controller 10 is generated in the state in the selection logic unit 20 to select B (TDI_1) to operate as a TDI, the counter start signal Is applied to the second block 50 to count the length of the instruction register, and then the counter end signal selects A (TMS_1) again (step S3-2).

On the other hand, the JTAG logic 30 selects one of the test data registers by the normal decoder logic at the moment the input command code is reflected and connects between the TDI and the TDO, and registers the register in a new test mode according to the command. Is activated (step S1-3), and the TAP controller 10 applies 1-> 1 to the TMS at the moment when the clock of the TCK is changed from "low" to "high", thereby updating the update-instruction register (Update-IR). The new instruction code is applied (step S2-3). In the selection logic section 20, the counter select signal CNT_Select for data register selection is performed by the ordinary decoder logic. ) Is selected from among a plurality of counters CNT_DR of the counter unit 62 of the third block 60 (step S3-3).                     

At this time, the JTAG logic 30 inserts a desired test pattern into the selected test data register through the TDI (step S1-4), and in the TAP controller 10, the clock of the TCK goes from "low" to "high". At the moment of change, 1-> 0-> 0 is applied to the TMS to enter the shift-data register (Shift-DR) state, thereby inputting the data register length (step S2-4), and the selection logic section 20 In the third block 60 of the TAP by the TMS2TDI_DR from the TAP controller 10 to select B (TDI_1), the counter start signal is applied to the selected counter (CNT_DR) of the counter unit 62 After counting the data register length, the counter end signal is allowed to select A (TMS_1) again (step S3-4).

Then, the JTAG logic 30 performs the desired operation and test while the input test data is used for the test (step S1-5), and the TAP controller 10 causes the clock of the TCK to be " low " At the moment when it changes to "high", 1-> 1 is applied to the TMS to reach the state of the update-data register (Update-DR) (step S2-5), but the selection logic section 20 operates as a TMS terminal. The specific operation is not performed, so that A (TMS_1) can be selected (step S3-5).

In this state, the JTAG logic 30 stores the test result in a data register (step S1-6), and the TAP controller 10 causes the TMS at the moment when the clock of the TCK changes from "low" to "high". 1-> 0 is applied to the capture-data register (Capture-DR) state (step S2-6), while the selection logic unit 20 operates as a TMS terminal but does not perform a specific operation. (TMS_1) can be selected (step S3-6).

The JTAG logic 10 receives the result value stored in the test data register through the TDO terminal pin and at the same time applies a second test pattern through the TDO terminal pin (steps 1-7). The TAP controller 10 ) Applies a "0" to the TMS at the moment when the clock of the TCK changes from "low" to "high", which leads to the shift-data register (Shift-DR) state and maintains the state by the length of the data register. (Step S2-7), the selection logic unit 20 receives TMS2TDI_DR from the TAP controller 10 to operate as TDI to select B (TDI_1), and the counter start signal is the counter unit 62. After the counter is applied to the selected counter CNT_DR and counted by the data register length, the counter end signal can select A (TMS_1) again (step S3-7).

On the other hand, the present invention is not limited to the above-described typical preferred embodiments, but can be carried out in various ways without departing from the gist of the present invention, various modifications, alterations, substitutions or additions are common in the art Those who have knowledge will easily understand. If such improvement, change, substitution or addition is carried out within the scope of the appended claims, the technical spirit should also be regarded as belonging to the present invention.

As described above, according to the present invention, the TDI terminal pins are removed from the TMS, TCK, TRST, TDI, and TDO five terminal pins of the test access port (TAP) applied to the boundary scan device for chip testing, and the TMS terminal pins. In addition, the terminal can be easily connected to the test access port for chip testing of digital devices, which are being miniaturized, and the space for the terminal connection in the PCB is reduced due to the reduction of terminal pins. It becomes possible, and it becomes effective that the connection to the other terminal which was difficult to connect due to priority was also possible.

In other words, when testing a large-scale device such as an exchange system, several chips are daisy-chained in the form of TDI-> TDO-> TDI-> TDO within one board for testing. Are daisy chained in the form of TDI-> TDO-> TDI-> TDO in one system and when tested, it eliminates hundreds of connections across the system, eliminating one terminal pin connection per chip. The effect is that it is possible to have the advantage of ensuring a more stable test environment.

Claims (6)

In the test access port (TAP) applied to the boundary scan device for chip testing, The TCK (Test Clock) terminal pin provides the test clock with the basic bits for serial communication. Through the Test Mode Select (TMS) terminal pin, the TDI (Test Data Input) function, which receives command code and test data serially for chip test, can be performed in parallel. According to the TMS value for state transition, a data register or instruction is used. Determining a register (Instruction Register), and selects A (TMS_1) for the TMS function or B (TDI_1) for the TDI function, A device for simplifying a test access port for chip testing, which is configured to output data of a test result through a test data out (TDO) terminal pin. In the test access port (TAP) applied to the boundary scan device for chip testing, A register is operated by a test clock from the TCK terminal pin and transitions to each of a plurality of states according to the TMS value through the TMS terminal pin to determine a data register or an instruction register, and selects an operation according to each state. A test access port controller that controls In response to receiving a command code or test data through the TMS terminal pin, the TMS according to the state transition of the shift-instruction register (Shift-IR) or the shift-data register (Shift-DR) under the control of the test access port controller. A selection logic section for inputting command codes and data by the length of the instruction register or data register by a TDI function parallel to the terminal pins; Device for simplifying a test access port for chip testing, characterized in that the JTAG logic unit for inputting test data through the TDI function parallel to the TMS terminal pin, and outputs the result data according to the test result through the TDO terminal pin. . The method of claim 2, The selection logic unit may be configured to select a shift-instruction register or shift-data register according to a TMS function by selecting A (TMS_1) for a TMS function or B (TDI_1) for a TDI function according to a register selection of the test access port controller. A first block for performing state conversion and serially inputting data as long as a desired register length according to the TDI function; A second block for selecting A (TMS_1) after inputting a code of an instruction register by a register length such that B (TDI_1) is selected according to the shift-instruction register selection of the test access port controller, and And a third block configured to select A (TMS_1) after inputting the pattern / data of the data register by the register length such that B (TDI_1) is selected according to the shift-data register selection of the test access controller. A device for simplifying a test access port for chip testing. The method of claim 3, wherein The first block of the selection logic unit changes the function of the input signal from the TMS terminal pin to TMS_1 or TDI_1 according to a signal for selecting A (TMS_1) or B (TDI_1) from the second and third blocks. A device for simplifying a test access port for chip testing, comprising a demux for the test. The method of claim 3, wherein In the second block of the selection logic unit, when the test access port controller is in the shift-instruction register (Shift-IR) state, B (TDI_1) is selected to generate the desired instruction register length by the counter start signal generation. And an instruction register counter which generates a signal for generating a counter end signal and then selecting A (TMS_1) after inputting an instruction code and then inputting a predetermined number of counters. Simplified device for test access port for testing. The method of claim 3, wherein When the third block of the selection logic unit is in the shift-data register (Shift-DR) state in the test access port controller, selects B (TDI_1) to generate the pattern / data by the desired data register length by generating the counter start signal. Inputs a plurality of data register counters for generating a counter end signal and selecting A (TMS_1) again; And a mux (MUX) for selecting and outputting any one of the plurality of counters by a counter selection signal from an instruction register decoder.

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