KR20060054691A - Semiconductor device having solder bump and method of manufacturing the same - Google Patents

Abstract

The present invention relates to a semiconductor device having solder bumps and a method of manufacturing the same. According to the present invention, after preparing a substrate having a plurality of contact pads on an upper surface thereof, a fusion barrier layer is formed on the substrate so as to cover the contact pad, and the fusion barrier layer is patterned to form a fusion barrier and the top of the contact pad. After the surface is exposed, a UBM layer is formed on the entire surface of the substrate, a photoresist pattern having an opening defining the solder bump area is formed on the surface of the UBM layer, and then a bump material is formed in the opening, and then outside the photoresist and the opening area. The UBM layer is removed to form solder bumps. Therefore, the present invention can prevent the bump melt from fusing at the time of connection of a semiconductor device with solder bumps, thereby reducing the defective rate.

Bump, solder, pitch, pad                                                      

Description

Semiconductor device with solder bumps and method for manufacturing same {SEMICONDUCTOR DEVICE HAVING SOLDER BUMP AND METHOD OF MANUFACTURING THE SAME}

1a and 1b are cross-sectional views for explaining the problem of the prior art,

2A and 2B are cross-sectional views of a substrate structure provided for practicing the present invention,

3A to 3D are cross-sectional views illustrating a method for forming a fusion barrier layer during a semiconductor device manufacturing process according to an embodiment of the present invention;

4A through 4G are cross-sectional views and plan views illustrating a method of forming a fusion barrier and exposing a top surface of a contact pad during a semiconductor device fabrication process according to an embodiment of the present invention;

5A through 5F are cross-sectional views illustrating a method of forming solder bumps on exposed contact pads during a semiconductor device manufacturing process according to an embodiment of the present invention;

6a to 6b is a perspective view, a plan view and a cross-sectional view for explaining the structure of the fusion barrier,

7A to 7D are cross-sectional views illustrating an application of a fusion barrier.

<Brief description of the major symbols in the drawings>

100: substrate 110: contact pad

130: fusion barrier layer 132: fusion barrier

150: UBM layer 150 ': UBM pattern

180, 180 ': solder bump

TECHNICAL FIELD The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device having a solder bump and a method for manufacturing the same.

Recently, in order to increase the speed and reduce the noise of an integrated circuit (IC) chip, a larger input output (I / O) bandwidth is required, and for this, a chip, a chip support, or a chip is required. An increase in the number per unit area of the solder bumps used as a connection medium between the chip and the chip, in other words, requires a decrease in the bump pitch. However, as the bump pitch decreases, the defective occurrence rate at the time of connection increases due to the difference in the size of the bumps and the bending of the substrate constituting the semiconductor device.

For example, FIG. 1A is a schematic diagram showing a problem in chip connection due to bump size difference in the prior art. The first substrate 10 having the contact pads 12 and the solder bumps 30 and 40 formed thereon is adjacent to the corresponding second substrate 20 so as to be disposed on the solder bumps 30 and 40 and the second substrate 20. When attempting to contact between the contact pads 22, due to the difference in the bump size as shown, the small solder bumps 40 do not come into contact with the contact pads 22, the space is created between the two S . Subsequently, wetting the contact pads 22 and wetting by melting the solder bumps 30 and 40 by raising the temperature. At this time, the bump height that decreases as the bump melts (collapses) depends on the shape of the bump and the contact pad, but in the case of the spherical bump, the height is generally reduced by about 10% of the bump diameter. Therefore, when the space S between the small bump 40 and the contact pad 22 is larger than the height in which the large solder bumps 30 are melted and collapsed in the drawing, the small solder bumps 30 may be separated from the contact pads. 22) cannot be contacted. Here, as shown in FIG. 1B to wet the small solder bumps 40 and the contact pads 22, an external force F is applied to the melt bumps 40 ′ of the small bumps. The first substrate 10 and the second substrate 20 are brought into close contact with each other. Then, as shown, the bump 40 of the small bump 40 'may also be connected while wetting the contact pad 22. At this time, however, when the two substrates 10 and 20 are brought closer than necessary, fusion occurs between the melts 30 'of the large bumps as shown, thereby forming a bridge 44. Such a bridge 44 causes a short circuit of the circuit and causes a defect.

As discussed above, when the connection is not made due to the uneven spacing between the bump and the corresponding contact pad, a short circuit occurs, or when a forcing of the bump and the corresponding contact pad is in close proximity to overcome the short circuit, fusion occurs between the other bumps. This can happen. This problem becomes larger especially as the bump pitch decreases, which is one of the big constraints in miniaturizing the bump pitch.

An object of the present invention is to solve the problems of the prior art as described above, by forming a fusion barrier on the solder bump forming surface to control the gap with the corresponding substrate when the IC chip is connected, by blocking the fusion of the bump melt The present invention provides a semiconductor device having solder bumps capable of reducing short circuits and short circuit defects.

Another object of the present invention is to provide a method for manufacturing a semiconductor device having the solder bumps.

According to an aspect of the present invention, there is provided a semiconductor device including a plurality of contact pads positioned on a substrate, a UBM pattern positioned on the contact pad, a solder bump positioned on the UBM pattern, and a top surface of the substrate. It is characterized in that it comprises a plurality of fusion barriers protruding between the bumps.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, including preparing a substrate having a plurality of contact pads on an upper surface thereof, and forming a fusion barrier layer on the substrate to cover the contact pads. Forming a fusion barrier and exposing a top surface of the contact pad, forming a UBM layer on the entire surface of the resultant, and solder bumps on the surface of the UBM layer. Forming a photoresist pattern having an opening defining a region, forming a bump material in the opening, removing the photoresist pattern, and removing a portion formed outside the opening region of the UBM layer by soldering Forming a bump, and reflowing the solder bump.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, embodiments of the present invention are provided to more completely explain the present invention to those skilled in the art. Accordingly, the shape and the like of the elements in the drawings are exaggerated to emphasize a more clear description, and the elements denoted by the same reference numerals in the drawings means the same elements. Also, where a layer or member is described as being 'on' another layer or substrate, the layer or member may be in direct contact with the other layer or substrate, or another film or member in between. May be interposed.

2A and 2B are cross-sectional views of a substrate structure provided for practicing the present invention. As shown, the substrates 100 and 102 have a plurality of contact pads 110 and 112 on their upper surfaces. Here, since the upper surface means the upper portion in the drawing, the wafer may be the front surface or the rear surface of the actual wafer. Although not illustrated, the substrates 100 and 102 may include a semiconductor integrated circuit (IC), and the contact pads 110 and 112 may be connected to metal wires of the integrated circuit. The contact pad 110 illustrated in FIG. 2A represents a contact pad made of Al or an Al alloy, and an upper reflection layer may be formed with an anti reflection coating (ARC) such as TiN. The contact pad 112 of FIG. 2B represents a contact pad made of Cu or W and is formed by a damascene process so that most of the pad is present in the substrate 102 and only the top surface thereof is exposed. The pad formed by the damascene process may have a plug shape. In particular, in the case of Cu, an upper portion of the substrate 102 may be formed of a passivation layer 104 such as a silicon nitride film. Next, a method of manufacturing a semiconductor device according to the present disclosure will be described based on the substrate 100 having the shape in which the contact pads 110 of FIG. 2A protrude.

3A to 3D are cross-sectional views illustrating a method of forming a fusion barrier layer during a semiconductor device manufacturing process according to an embodiment of the present invention.

First, referring to FIG. 3A, a fusion barrier layer 130 is formed on the substrate 100 to cover the contact pad 110. The fusion barrier layer 130 is made of an insulating film, preferably made of a passivating insulating material that can prevent metal diffusion and penetration of moisture. Therefore, the fusion barrier layer 130 may be formed of a silicon oxide film, a silicon nitride film, a BCB (BezoCycloButene) film, or a combination thereof. The fusion barrier layer 130 may be formed by chemical vapor deposition (CVD) or spin coating. The fusion barrier layer 130 prevents the solder bumps to be formed later from being fused to each other in a melt state, and also forms the fusion barrier wall necessary to approach the substrate 100 and the corresponding substrate by a controlled distance. The forming thickness is preferably determined according to the predetermined bump size and pitch.

3B and 3C illustrate an example of forming the fusion barrier layer 130. First, as shown in FIG. 3B, a first insulating layer 122 formed of CVD, such as a silicon oxide film or a silicon nitride film, is formed on the substrate 100. To cover the contact pad 110 and expose the upper surface of the contact pad 110 through patterning. Then, a second insulating film 124 such as BCB is formed on the resultant to form a fusion barrier layer 130 formed of the first insulating film pattern 122 ′ and the second insulating film 124, as shown in FIG. 3C. can do.

3D illustrates another example of forming the fusion barrier layer 130. First, a first insulating layer 126, such as a silicon oxide layer or a silicon nitride layer, is formed on the substrate 100 to cover the contact pad 110. Next, after forming the second insulating film 128 such as BCB, the fusion barrier layer 130 formed of the first insulating film 126 and the second insulating film 128 can be formed.

4A to 4G illustrate a method of forming a fusion barrier by exposing the fusion barrier layer 130 and exposing an upper surface of the contact pad 110 during a semiconductor device fabrication process according to an embodiment of the present invention. Cross-sectional views and plan views.

First, referring to FIG. 4A, the fusion barrier layer 130 is patterned to form a fusion barrier 132 and expose the top surface of the contact pad 110. The fusion barrier 132 is a part of the fusion barrier layer 130, but for ease of understanding of the drawings will be given a different reference numerals and will be represented by a brick pattern.

4B to 4D illustrate a case where the formation of the fusion barrier wall 132 and the exposure of the upper surface of the contact pad 110 are performed by separating the first insulating layer 126 and the second insulating layer 128 of FIG. 3D. Figure 1 shows an example applied to the fusion barrier layer 130 is made of. First, referring to FIG. 4B, when the predetermined region of the second insulating layer 128 is removed until the first insulating layer 126 formed on the contact pad 110 is exposed through primary patterning, as shown in FIG. Wall 132 is formed. For this purpose, it is preferable that the first and second insulating layers have a high etching selectivity like the silicon nitride film and BCB. Subsequently, through additional etching, as shown in FIG. 4C, chemistry is preferably changed to quickly etch the first insulating layer 126 to expose the top surface of the contact pad 110. Referring to FIG. 4D, the upper surface of the contact pad 110 is exposed by removing a predetermined region of the first insulating layer 126 through secondary patterning in the structure of FIG. 4B. In this case, as shown, only a part of the contact pad 110 may be exposed without exposing the entire upper surface. As described above, when the formation of the fusion barrier wall 132 and the exposure of the upper surface of the contact pad 110 are performed separately, when the second insulating layer 128 is thick, a contact pad due to over etching accompanying the second insulating film 128 ( 110) Minimize damage to the top surface.

4E illustrates another method of fusion barrier formation and contact pad top surface exposure. After forming the fusion barrier 132 and exposing the top surface of the contact pad 110 through patterning, an additional insulating layer (not shown) is further deposited on the entire surface of the resultant, and then the contact pad 110 is shown as shown. When the upper insulating layer is patterned to expose the upper surface of the substrate, the entire surface of the resultant is covered with the upper insulating layer pattern 134 except for the upper surface. The upper insulating film pattern 134 may be formed of a silicon nitride film, a silicon oxide film, or a combination thereof. By forming the upper insulating film pattern 134 of the inorganic compound system as described above, the adhesion of the metal film can be improved during the subsequent metal film formation, and in the case of the fusion barrier wall 132 composed of the compound, a protective film against organic solvents can be formed. There is an advantage.

4F and 4G are plan views and cross-sectional views illustrating examples of fusion barrier walls formed by the method described above. As shown in the drawing, the fusion barrier walls 132 and 132 'are formed in plural and show an example formed between the closest contact pads 110 and 110'. The structure for the fusion barrier will be described at the stage where solder bumps are formed.

5A through 5F are cross-sectional views illustrating a method of forming solder bumps on the exposed contact pads 110 during a semiconductor device manufacturing process according to an embodiment of the present invention.

Referring to FIG. 5A, an under bump metal (UBM) layer 150 is formed on the entire surface of the substrate structure through which the fusion barrier wall 132 is formed and the upper surface of the contact pad 110 is exposed. The UBM layer 150 may be made of Ti, Ta, Cr, Ni, Cu, Pd, Au, or a combination thereof and may be formed by PVD or plating.

Referring to FIG. 5B, a photoresist pattern 160 having an opening 162 exposing a portion of the UBM layer 150 covering the upper surface of the contact pad 110 is formed on the surface of the UBM layer 150. . The openings 162 define solder bump regions, and the openings 162 may be formed at a predetermined distance (as shown by d) from the side surface of the fusion barrier wall 132 on which the UBM layer 150 is formed.

5C through 5F, first, bump material 170 is formed in the opening 162 formed by the photoresist pattern 160 in FIG. 5C by a predetermined height. As the bump material 170, an alloy of Pb, Sn, Sb, Ni, Ag, Cu, Bi, Zn, In, and metals selected from these may be used. Formation of the bump material 170 in the opening 162 is preferably using a plating method. Subsequently, after the photoresist 160 is removed, a portion of the UBM layer 150 other than the region where the bump material 170 is formed is etched away using the bump material 170 as a mask, that is, outside the region of the opening 162. Removing the formed portion, a solder bump 180 is formed with a gap (shown in g) between the side of the fusion barrier 132 as shown in FIG. 5D. The gap g has a larger value than the above-described gap d due to the etching of the UBM layer 150. Subsequently, as shown in FIG. 5E, when the temperature is increased to reflow the solder bumps 180, spherical solder bumps 180 ′ are formed on the UBM pattern 150 ′. The height is adjusted when the bump material 170 is formed such that a gap (shown as g ') is present between the solder bumps 180'. The size of the gap g 'is preferably in the range of 3% to 60% of the solder bump 180' diameter (shown as w '). FIG. 5F shows the UBM pattern 152 and solder bumps 180 'formed by the method described above in the structure of FIG. 4D with the contact pad 110 partially exposed.

6A to 6B are a perspective view, a plan view, and a cross-sectional view for explaining the structure of a fusion barrier after solder bump formation.

Various modifications can be made to the formation and structure of the fusion barrier. For example, as shown in the drawing, the fusion barrier may not be formed between the solder bumps 180m and 180n which are not a problem even when the bump melt is fused. have. That is, the fusion barrier does not need to be uniformly formed between all the solder bumps. On the other hand, in a region where the fusion of the bump melt is to be more thoroughly blocked, a merged fusion blocking wall 132m may be formed. That is, the size and shape of the fusion barrier need not all be the same and may vary depending on the area.

Since the bump malt does not wet the insulating film constituting the fusion barrier under normal substrate connection conditions, the probability that the bump melt is fused through the gap between the fusion barriers 132 and 132m is not high. Rather, the gap between the fusion barrier walls 132 and 132m is an underfill such as epoxy between the solder bumps 180 ', 180m and 180n after connecting the substrate 100 to a corresponding substrate (not shown). ) Provides a passage through which the air between the solder bumps 180 ', 180m, 180n can be easily released and underfill easily enters.

The height of the fusion barriers 132 and 132m (shown as b) should vary according to the bump pitch and height and the width of the fusion barrier 132, such as the height of the solder bumps 180 '(shown as s). It is preferred to have a value between 20% and 90% of. The smaller the bump pitch and the larger the width of the fusion barrier, the greater the height of the fusion barrier. The heights of the fusion barriers 132 and 132m are mainly determined by the thickness of the fusion barrier layer 130 described above. In addition, the height of the solder bumps 180 'is mainly determined by the shape and width of the lower UBM pattern 150' or contact pad 110 and the amount of bump material formed thereon.

7A to 7D are cross-sectional views illustrating an application of a fusion barrier. First, referring to FIG. 7A, the fusion barrier wall 330 and the solder bumps 380 and 390 are formed on the substrate 300 having the contact pads 310 in the above-described manner, and then the substrate 300 corresponds to the substrate 300. In order to connect to the substrate 400, the solder bumps 380 and 390 of the substrate 300 and the contact pads 410 and 420 of the corresponding substrate 400 are placed to align. Here, as illustrated, the small solder bump 390 may not be in contact with the corresponding contact pad 420. Subsequently, when the solder bumps 380 and 390 are melted by increasing the temperature, the bump melts 380 ′ wet the corresponding contact pads 410 as shown in FIG. 7B. However, the small solder bump 390 may not be in contact with the corresponding contact pad 420 even when the bump melt 390 ′ is used. At this time, as shown in FIG. 7C, a force F is applied to the substrates 300 and 400 until the two substrates 300 and 400 are brought into contact with the surface of the corresponding substrate 400. Get close. Then, the bump melt 380 ', which has already been wetted, is pressed and spreads laterally, and the small bump melt 390' is wetted in contact with the corresponding contact pad 420. Here, the fusion blocking wall 330 prevents the bump melts 380 'and 390' from being fused to each other and prevents the two substrates 300 and 400 from approaching more than necessary. Thereafter, the bump melts 380 'and 390' may be solidified while the force F is applied, or the bump melts 380 'and 390' are retracted by removing the force F as shown in FIG. 7D. You may solidify at.

As described above, the present invention provides a bump size by forming a fusion barrier on a substrate having solder bumps, thereby reducing the distance from the corresponding substrate at a controlled size when the substrate is connected, and blocking the bump melt from fusing. The connection failure of the semiconductor device due to the difference and the bending of the substrate can be reduced, and the semiconductor device having the ultra fine bump pitch can be manufactured and connected using the present invention.

On the other hand, the present invention is not limited to the above-described embodiment, various modifications are possible by those skilled in the art within the spirit and scope of the present invention described in the claims to be described later.

Claims (15)

A plurality of contact pads positioned on the substrate; A UBM pattern positioned on the contact pad; A solder bump positioned on the UBM pattern; And And a plurality of fusion barrier walls protruding from the upper surface of the substrate and positioned between the solder bumps. The method of claim 1, And said substrate is a semiconductor integrated circuit chip. The method of claim 1, And the solder bumps are reflowed. The method of claim 1, And the fusion barrier is made of an insulating film. The method of claim 4, wherein And the insulating film is formed of a silicon oxide film, a silicon nitride film, a BCB (BezoCycloButene) film, or a combination thereof. The method of claim 1, And a gap exists between the solder bumps and the sides of the fusion barrier. The method of claim 6, The gap size is a semiconductor device, characterized in that 3% to 60% of the solder bump diameter. The method of claim 1, The height of the fusion barrier wall is a semiconductor device, characterized in that 20% to 90% of the height of the solder bump. Preparing a substrate having a plurality of contact pads on an upper surface thereof; Forming a fusion barrier layer on the substrate to cover the contact pad; Patterning the fusion barrier layer to form a fusion barrier and exposing an upper surface of the contact pad; Forming a UBM layer on the entire surface of the resultant product; Forming a photoresist pattern on the surface of the UBM layer having openings defining solder bump regions; Forming bump material in the opening; Removing the photoresist pattern; Forming a solder bump by removing a portion of the UBM layer formed outside the opening region; And And reflowing the solder bumps. The method of claim 9, And the fusion barrier layer is made of an insulating film. The method of claim 10, And the insulating film is formed of a silicon oxide film, a silicon nitride film, a BCB film, or a combination thereof. The method of claim 9, The bump material is formed by a plating method. The method of claim 9, And a gap exists between the reflowed solder bumps and a fusion barrier side. The method of claim 13, Wherein said gap size is between 3% and 60% of said reflowed solder bump diameter. The method of claim 9, And the height of the fusion barrier is 20% to 90% of the height of the reflowed solder bumps.

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