KR100713579B1 - Method of aligning semiconductor device and semiconductor structure thereof - Google Patents

Abstract

The present invention relates to a method for aligning semiconductor elements required for lamination of dies (lamination of dies and wafers, lamination of dies and dies, lamination of dies and chip supports), and a semiconductor structure formed thereby. In particular, according to the alignment method of the present invention, a magnetic material is formed on a dyna wafer or a chip support including a semiconductor device to be aligned, and the alignment between the two semiconductor devices or between the chip support and the semiconductor device is caused by the magnetic force between the magnetic materials. Is done. In addition, after alignment, the fixed state of the die required for manufacturing the laminated semiconductor structure is maintained by magnetic force between the magnetic bodies.

Magnetic material, magnetic force, semiconductor element, align, die, wafer, lamination, bump

Description

Method of aligning semiconductor devices and semiconductor structures formed by them TECHNICAL FIELD             

1 is a cross-sectional view showing an alignment method between semiconductor devices according to the prior art;

2 is a cross-sectional view showing an alignment method between semiconductor devices according to another prior art;

3A to 3O are cross-sectional views, plan views, and perspective views illustrating a semiconductor device alignment method using a magnetic material according to an embodiment of the present invention;

4A and 4B are cross-sectional views illustrating another example of a method of forming a magnetic body and a method of aligning semiconductor devices according to the present invention,

5A and 5F are cross-sectional views illustrating still another example of a method of forming a magnetic material used in an embodiment of the present invention, and a method of aligning semiconductor devices accordingly;

6A through 6C are cross-sectional views illustrating a semiconductor device alignment method using a magnetic material according to another embodiment of the present invention;

7 is a cross-sectional view illustrating a semiconductor device alignment method using a magnetic material according to still another embodiment of the present invention;

8A through 8C are cross-sectional views illustrating alignment and attachment of a semiconductor device using an external magnetic field;

9A and 9B are cross-sectional views illustrating an example in which a plurality of semiconductor devices are stacked on one semiconductor device;

10A to 10C are cross-sectional views illustrating examples of electrically connecting semiconductor devices formed on stacked dies and wafers, respectively.

11A to 11E are cross-sectional views illustrating an example of a bump forming method;

12A to 12C are cross-sectional views illustrating another example of a bump forming method;

13A to 13D are cross-sectional views illustrating a method of manufacturing a semiconductor structure using a magnetic material according to still another embodiment of the present invention;

14A to 14C are cross-sectional views illustrating a method for preventing fusion between molten solder in manufacturing a semiconductor structure according to the present invention;

15A to 15C are cross-sectional views illustrating a method of manufacturing a semiconductor structure using a magnetic material according to still another embodiment of the present invention;

16A and 16B are cross-sectional views illustrating a method of manufacturing a semiconductor structure using a magnetic material according to still another embodiment of the present invention;

17A and 17B are sectional views illustrating an example in which the present invention is applied.

<Brief description of the major symbols in the drawings>

100, 200: wafer
250, 252, 254, 256: Die

102: first semiconductor device
202: second semiconductor device

110a, 162a: first magnetic material
210a, 212a, 214a, 216a: second magnetic material

150: first die
260, 262, 264: second die

160: Chip Support
290, 292 coil

500: Substrate
600: die

520, 524: first magnetic material
620, 624: second magnetic material

630, 630 ', 630'': interconnect with solder bumps
518: first bonding pad
618: second bonding pad

delete

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device alignment method and a semiconductor structure formed thereby, and more particularly, to chip support in stacking dies and wafers and stacking dies and dies. And an alignment method between a semiconductor device and a semiconductor device, and a semiconductor structure formed thereby.

Vertical integration of semiconductor devices improves system performance by shortening the wiring length between devices, reducing the area occupied by devices on the system, and also enabling integration after dissociating different devices. By doing so, there is an advantage of reducing the manufacturing cost.

With vertical integration, memory devices such as Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM) and Electrically Programmable Read Only Memory (EPROM), logic devices such as Field Programmable Gate Arrays (FPGAs), and RFICs (Radio) A system on chip (SoC) that integrates a communication device such as a frequency integrated circuit, a sensor device such as a charge coupled device (CCD), an optical device such as a photo diode, and a semiconductor device such as a microprocessor in a single chip can be implemented.

As a method of implementing vertical integration of such semiconductor devices, a wafer and a wafer stacking method, a die-to-wafer stacking method, and a separate die are stacked on a wafer. There are methods of die-to-die stacking.

The method of stacking wafers and wafers can simultaneously stack many dies in one stack, while yielding an exponential decrease in yield as the number of stacked wafers increases.

On the other hand, the die and wafer lamination and die and die lamination methods which can select and separate only good dies through electrical or optical inspection and separate them are not yielded as described above, but have a disadvantage in that the process takes a long time.

In either method, the alignment between the two devices on the substrate is important at the time of stacking because the yield and productivity are determined by the accuracy and speed of the alignment. Especially for interconnects between devices such as vias, bonding pads or solder bumps Smaller pitches require higher alignment accuracy.

1 and 2 are cross-sectional views showing an alignment method according to the prior art. The alignment method according to the prior art will be described with reference to these drawings.

As shown in FIG. 1, alignment marks 3 and 4 are respectively formed on the upper substrate 1 and the lower substrate 2 including semiconductor elements (not shown). The two substrates are placed on an infrared (IR) source (5) to detect the position of the two alignment marks (3, 4) by detecting the transmitted infrared rays through the objective (6). The semiconductor device is aligned by moving the upper substrate 1 or the lower substrate 2 until the two alignment marks 3 and 4 are aligned. Infrared rays have a simple advantage of alignment because they penetrate the semiconductor substrate, but there is a limit in application in the case where the metal wiring is dense due to the inability to penetrate the metal layer. In addition, infrared light has a long wavelength, which has a disadvantage in that resolution is worse than using a visible light or an ultraviolet light source.

Figure 2 is a cross-sectional view showing an alignment process according to another prior art. This will be described in more detail as follows. In the first stage (stage-1), the upper objective 6 and the lower objective 7 are first aligned, and then the alignment mark 3 of the upper substrate 1 is aligned with the center of the lower objective 7. After moving the upper substrate 1, the substrate position at this time is stored. Subsequently, the lower substrate 2 is moved so that the alignment mark 4 of the lower substrate 2 is aligned with the center of the upper objective 6 in two stages. Then, using the data stored in stage-3, the upper substrate 1 is moved to the alignment position of stage-1, so that the upper substrate 1 and the lower substrate 2 are both And it is aligned to the center of the lower objective (5, 6) and eventually the two substrates (1, 2) are aligned. Since the method shown in FIG. 2 does not need to penetrate the substrate, light having a short wavelength may be used, and thus, fine alignment may be achieved, whereas the alignment process is shown in FIG. Is more complicated than the old way

The alignment methods according to the prior art all use the alignment mark, which is a method of manually moving a stage supporting the substrate in moving the substrate so that the alignment mark enters a defined area, and automated through image processing. There is a way to use the stage. The method by the automated stage is fast and free from personal variation, making it suitable for mass production. When the required accuracy of the alignment is within 1 μm, the alignment speed by the automated stage is about 1 minute per alignment. Therefore, when stacking wafers and wafers, the alignment speed does not cause significant problems compared to the production speed of other processes. However, when laminating dies to wafers or laminating dies and dies, the lamination process due to the aligning speed causes severe productivity degradation.

In addition, it is difficult to temporarily fix the wafer or the die so that the alignment can be maintained until the next process after the alignment between the devices is performed in the stack for vertical integration. When stacking wafers and wafers, the two wafers can be temporarily fixed after the alignment by clamping. However, when the die is stacked on the wafer or the die and the die are stacked, there is no way to temporarily fix the die on the wafer or on another die while maintaining alignment until the next process. A bonding method is used. The member of such a temporary fixing method is limited to applying various lamination methods such as lamination by Cu bonding pads or solder bumps.

In the same vein, as the number of bumps per unit area used as a connection medium between a die and a package substrate, such as chip support, increases, the bump pitch decreases in other words. As such, higher alignment accuracy is required. However, the existing method has a limit in increasing the accuracy of alignment without sacrificing productivity.

SUMMARY OF THE INVENTION An object of the present invention is to solve the problems of the prior art as described above. It is to provide a semiconductor device alignment method that can fix the die so that the alignment can be made quickly, and after the alignment to maintain the alignment state to the subsequent process.

Another object of the present invention is to provide a semiconductor structure formed by the above method.

The semiconductor device alignment method between the first semiconductor device on the wafer and the second semiconductor device on the die during stacking of the die and the wafer according to an embodiment of the present invention for achieving the above object, and the first magnetic material formed on the wafer; The first semiconductor device and the second semiconductor device may be aligned by using a magnetic force between the second magnetic bodies formed on the die.

According to another aspect of the present invention, there is provided a method of aligning semiconductor devices between a first semiconductor device on the first die and a second semiconductor device on the second die when the first die and the second die are stacked. The first semiconductor device and the second semiconductor device may be aligned by using a magnetic force between the first magnetic material formed on the first die and the second magnetic material formed on the second die.

According to another aspect of the present invention, there is provided a method of aligning a semiconductor device on a die and a chip support according to another embodiment of the present invention, wherein the first magnetic material formed on the chip support and the die are formed on the die. The semiconductor device and the chip support may be aligned by using a magnetic force between the formed second magnetic bodies.

According to still another aspect of the present invention, there is provided a semiconductor structure including a substrate, a die stacked on the substrate, an interconnect positioned between the substrate and the die, and the substrate for aligning the interconnect. And a first magnetic body formed and a second magnetic body formed on the die.

According to another aspect of the present invention, there is provided a semiconductor structure including a substrate having a first bonding pad thereon, and a second bonding pad stacked on the substrate and connected to the first bonding pad. And a first magnetic body formed on the substrate for aligning the first bonding pad and the second bonding pad, and a second magnetic body formed on the die.

Hereinafter, a semiconductor device alignment method according to the present invention will be described in detail with reference to the accompanying drawings. However, embodiments of the present invention are provided to more completely describe the present invention to those skilled in the art. Therefore, the shape and the like of the elements in the drawings are exaggerated to emphasize a more clear description, and the elements denoted by the same reference numerals in the drawings means the same elements.

3A to 3O are cross-sectional views, plan views, and perspective views illustrating a semiconductor device alignment method using a magnetic material according to an embodiment of the present invention. With reference to these drawings will be described in detail the alignment method according to an embodiment of the present invention.

Referring to FIG. 3A, the magnetic material layer 110 is formed on the wafer 100 having the first semiconductor devices 102. Magnetic materials generally refer to ferromagnetic materials and refer to materials that are easily magnetized, such as Fe, Ni, and Co. In addition to the metal, an alloy of the metals and Al or Mn may be used as the magnetic material layer 110. In addition, the magnetic material layer 110 may be formed of an alloy of rare earth metals such as Nd or Sm to generate high magnetic force. As the magnetic material layer 110, a ceramic material such as ferrite may be used in addition to the metal and the alloy. As the method of forming the magnetic material layer 110, sputtering, chemical vapor deposition, plating, or laser ablation may be used. Ti, TiN, Ta, TaN, or the like may be deposited before the formation of the magnetic material layer 110 as a glue layer for improving adhesion of the magnetic material layer 110 and also as a diffusion barrier layer of the magnetic material. In forming the magnetic material layer through plating, Cu or Ni is formed before the plating process as a seed layer required for the plating process. As another method of forming the magnetic material layer 110, the magnetic powder is dispersed in a resin such as polyimide or benzocyclobutene (BCB), and the resin is then spin-coated in a method such as spin coating. The magnetic material layer 110 may be obtained by coating on 100 and then curing.

Subsequently, as shown in FIG. 3B, a patterned first magnetic body 110a is formed on the first semiconductor device 102 through a photolithography and an etching process. The shape of the magnetic body may be in the form of a disk 110b, a ring 110c, a rod 110d, or the like, as shown in the plan view of FIG. As the size of the magnetic material increases, in particular, the magnetic force increases, but the accuracy of alignment decreases. Therefore, the size of the magnetic material is determined according to the required alignment accuracy. The shape, number, and size of the magnetic material can be variously changed by those skilled in the art, so a detailed description thereof will be omitted.

The position of the first magnetic body 110a may be in the region of the first semiconductor element 102 (inside or above the boundary formed by the broken lines) as shown in FIG. 3B, and as shown in FIG. 3D, the space between the first semiconductor elements 104 is formed. If sufficient, it may be outside the region of the first semiconductor element 104. When the first magnetic body 110a is formed outside the region, as shown in FIG. 3D, it is preferable that the magnetic body 110a is not positioned at the portion 90 removed when the die is separated by sawing or the like. Do. Then, after the separation in the form of a die, the first magnetic body 110a is located outside the region of the first semiconductor device 104 but is present on the die.

Referring to FIG. 3E, the magnetic protective layer 120 is formed around the first magnetic body 110a. The magnetic protective layer 120 is particularly necessary when a material that is easily oxidized such as NdFeB forms a magnetic material. As the magnetic protective layer 120, an inorganic insulating material such as silicon oxide film (SiO ₂ ) or silicon nitride film (SiN), or an organic insulating material such as epoxy or BCB is used. When the inorganic insulating material is formed by the chemical vapor deposition method, when the step height is large on the surface of the insulating material by the first magnetic body 110a, planarization may be performed using chemical mechanical polishing or the like for the subsequent process.

3F to 3H illustrate a method of forming a magnetic body using a damascene process. First, referring to FIG. 3F, an intaglio structure 92 such as a trench defining a magnetic region is formed on the first semiconductor device 102 through photolithography and an etching process. Then, as illustrated in FIG. 3G, the magnetic material layer 112 is formed in the intaglio structure 92 and on the semiconductor device 102. In this case, Ti, TiN, Ta, TaN, or the like may be deposited before the formation of the magnetic material layer 112 as an adhesive layer for improving adhesion of the magnetic material layer 112 and as a diffusion barrier layer of the magnetic material. As shown in FIG. 3H, the first magnetic body 112a is manufactured by removing only the magnetic material in the intaglio structure 92 and removing the remaining magnetic material layer through chemical mechanical polishing or etch back. Here, a magnetic protective layer may be further formed on the upper surface of the first magnetic body 112a to protect it.

3I and 3J illustrate another method of forming a magnetic body, first forming a seed layer 94 on the wafer 100 as shown in FIG. 3I, and exposing a portion of the seed layer 94 corresponding to the magnetic region. A photoresist pattern 96 having openings 98 to be formed is formed on the seed layer 94 surface. Subsequently, a magnetic material is formed in the opening 98 formed by the photoresist pattern 96 through a plating method, and then the photoresist pattern 96 is removed, and then portions of the seed layer 94 formed outside the magnetic region are removed. 3J, a first magnetic body 114a is formed on the first semiconductor device 102.

Among the two semiconductor devices to be stacked, a magnetic material is formed on the first semiconductor device 102, and then a magnetic material is formed on the second semiconductor device to be stacked in alignment with the first semiconductor device 102.

Referring to FIG. 3K, the second magnetic body 210a and the magnetic protective layer 220 are formed on the wafer 200 having the second semiconductor devices 202 through the above-described method. The position of the second magnetic body 210a is that the first magnetic body 110a and the second magnetic body 210a face each other when the first semiconductor element 102 and the second semiconductor element 202 are stacked and aligned. Make it visible. In the manufacturing method of the second magnetic body 210a, the above-described processes may be applied in the same manner, and thus redundant descriptions thereof will be omitted.

After the magnetic material is formed on the two semiconductor devices to be stacked, the magnetic material in the at least one semiconductor device is magnetized before alignment. Magnetization is achieved by applying an external magnetic field to a magnetic body using a magnetizer or the like. The magnetization may simultaneously magnetize all magnetic bodies on the wafer by applying a magnetic field to the entire wafer, or may separate the wafer into dies and then apply a magnetic field to the dies.

Referring to FIG. 3L, when the magnetic bodies formed on the two semiconductor devices are magnetized, the surfaces of the first magnetic body 110a and the second magnetic body 210a which face each other during alignment as shown in FIG. 3L have opposite polarities. Magnetize so that it has an attractive force at the time of alignment.

Next, of the first and second semiconductor devices 102 and 202 to be stacked, for a semiconductor device, it is separated from the wafer in die units. In general, in die and wafer stacking, it is more desirable to separate the smaller die size of the two stacked devices into dies, which means that all of the devices on the wafer that have passed electrical or optical inspection are used for the stacking. It is not restricted. In the present exemplary embodiment, the wafer 200 in which the second semiconductor devices 202 having the smaller size are formed among the two semiconductor devices 102 and 202 is separated into a die.

3M and 3N, the die 250 separated through back grinding and sawing is brought close to the first semiconductor device 102 on the wafer 100 as shown in FIG. 3M. The magnetic force (attractive force) F acts as a magnetic force between the first magnetic body 110a and the second magnetic body 210a. Then, the die 250 is attracted to the force F so that the magnetic bodies 110a and 210a are aligned to face each other as shown in FIG. 3N, and the die 250 is attached to the wafer 100 by magnetic force. The positions where the magnetic bodies 110a and 210a face each other are such that the magnetic bodies 110a and 210a face each other when the first semiconductor element 102 and the second semiconductor element 202 are aligned in design. Therefore, the first semiconductor element 102 and the second semiconductor element 202 are automatically aligned. Here, the proximity of the die 250 is a pick and place (pick and place) equipment (pick and place) equipment, such as pick up and move the mechanical die and then use the equipment having the function to put down in the prescribed position, the current pick and place In the case of equipment, it takes about one second to pick up a die and lower it within a 30 µm error range from a defined location.

3O is a perspective view illustrating another method of bringing the die 250 into close proximity with the wafer 100. First, the dies 250 are aligned in a position where magnetic force may be applied to align the wafers, and then the first magnetic body 110a and the second magnetic body 210a may face each other so as to face the wafer 100. When the dies 250 are close to each other, the dies 250 are attached to the wafer 100 by the magnetic force between the magnetic bodies 110a and 210a and are aligned at the same time. Proximity of the wafer 100 to such aligned dies 250 allows the alignment and attachment of a large number of dies simultaneously.

4A and 4B are cross-sectional views illustrating another example of a method of forming a magnetic body and a method of aligning a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 4A, a thinned wafer 200 ′ is manufactured by thinning a back surface of a wafer (not shown) on which the second semiconductor device 202 is formed through backgrinding or chemical mechanical polishing. Subsequently, a magnetic protective layer 222 and a second magnetic body 212a formed of an insulating layer are formed on the thinned back surface. Then, as shown in FIG. 4B, the thinned wafer 200 ′ is separated into a die 252, and the die 252 is brought into proximity with the first semiconductor device 102 on the wafer 100 to form a wafer ( The first magnetic body 110a formed at 100 and the second magnetic body 212a formed at the die 252 are aligned and attached to each other by the magnetic force F. As such, when the magnetic material 212a is disposed on the rear surface of the die 252, the die 252 may not be flipped when stacked.

5A and 5F are cross-sectional views illustrating still another example of a method of forming a magnetic body used in an embodiment of the present invention and a semiconductor device alignment method according thereto. In the above-described magnetic body forming methods, after the semiconductor device is formed, a magnetic body is formed on the upper or rear surface of the wafer. In this method, the magnetic body is formed during the semiconductor device manufacturing process.

5A illustrates an example of the second magnetic material 213a formed during the manufacturing process of the second semiconductor device 202 on the wafer 200. As shown in FIG. 2, when the second magnetic material 213a is positioned in the device region, when the wafer 200 is thinned and separated into a die, the magnetic force required for alignment may be generated in both directions of the upper and lower surfaces of the die. It can be effectively used when the semiconductor elements are stacked up and down.

It is preferable that the formation of the magnetic body in the semiconductor device manufacturing step is performed after the step of requesting high temperature such as the transistor formation is completed. In addition, even when the magnetic material is formed during the semiconductor device manufacturing process, unlike in FIG. 5A, the magnetic material may be exposed to or close to the lower surface of the die to induce greater magnetic force in the lower surface direction. For example, referring to FIGS. 5B and 5C, the isolation oxide film 50, the sources 52s and 54s, the drains 52d and 54d, the gate electrode 56, the spacer 58, and the like constituting the transistor may be used. And then deposit and planarize the interlayer insulating film 60, and then form a hole or trench-type intaglio structure 70 that penetrates the interlayer insulating film 60 to the inside of the wafer 200 as shown in FIG. 5B. do. Next, the insulating film liner layer 80 is deposited inside the intaglio structure 70 and the upper surface of the interlayer dielectric film 60, and the intaglio structure 70 is embedded with a magnetic material. In order to fill the intaglio structure 70 with a magnetic material, a metal magnetic material plating method followed by forming a diffusion barrier and seed layer or a resin such as spin on glass (SOG) or BenzoCycloButene (BCB) in which magnetic particles are dispersed After coating and filling, a method of curing may be used. Subsequently, the conductive layers such as the magnetic material and the seed layer in the regions other than the inside of the intaglio structure 70 are removed by chemical mechanical polishing or a full surface etching method to penetrate the interlayer insulating film 60 as shown in FIG. 5C. The second magnetic body 214a reaching the inside of the 200 is formed. Although not shown, the semiconductor device is completed by performing a necessary process after transistor formation such as metal wiring.

5D to 5F, the second magnetic material 214a formed according to the above method passes through the region of the second semiconductor element 202 (the area indicated by the broken line) to the inside of the wafer 200 as shown in FIG. 5D. This leads to. Subsequently, the back surface of the wafer 200 is thinned as shown in FIG. 5E to expose the second magnetic material 214a. Then, as shown in FIG. 5F, the die 254 separated from the thinned wafer 200 ″ of FIG. 5E is brought close to the first semiconductor device 102 on the wafer 100 to form a first magnetic material ( The magnetic force between 110a and the second magnetic material 214a causes the first and second semiconductor devices 102 and 202 to be aligned and the die 254 to be attached to the wafer 100. Although not shown, a protective film made of an insulating material may be formed on the rear surface of the thinned wafer 200 ″ after the process of FIG. 5E to protect the surface of the second magnetic material 214a and then separated by the die 254. have.

6A through 6C are cross-sectional views illustrating a semiconductor device alignment method using a magnetic material according to another exemplary embodiment of the present invention, showing die-to-die stacking. In the present embodiment, the magnetic body forming methods of the above-described embodiment are applied in the same manner, and the same reference numerals are given to the same parts as the above-described embodiment, and redundant descriptions are omitted.

Referring to FIG. 6A, the wafer 100 of FIG. 3E, on which the first semiconductor device 102 and the first magnetic body 110a are formed, is separated into a first die 150 through backgrinding and sawing, and then a first magnetic body. The first die 150 is fixed to a support (not shown) so that 110a is at the top. Subsequently, the first and second magnetic materials 110a and 210a may face each other with the second die 260 including the second semiconductor device 202 and the second magnetic material 210a formed on the upper surface thereof. The first semiconductor device 102 and the second semiconductor device 202 are aligned by the magnetic force F between the magnetic bodies 110a and 210a by flipping the first die 150 to be close to the first die 150. 260 is attached to the first die 150.

6B and 6C, the second magnetic body 212a is formed on the rear surface of the second die 262 as shown in FIG. 6B and the second magnetic body 214a is formed as shown in FIG. 6C. 2 When the semiconductor device 202 is formed during the manufacturing process and exposed to the rear surface of the second die 264, the second dies 262 and 264 are brought close to the first die 150 without flipping, respectively, as shown. The magnetic force F causes adhesion between the alignment of the first semiconductor element 102 and the second semiconductor element 202 and the die. In the stacking of dies and dies, the proximity of the dies can be achieved through equipment with the ability to pick up separate dies, mechanically move them and then lower them to defined locations, such as pick and place equipment.

When stacking dies and dies, dies and dies may be directly stacked as in the above embodiment, but when chip support is inserted between dies and dies to form die and chip support, alignment between chip support and semiconductor elements on the die is required. do. In semiconductor device packaging, even when a die is laminated and bonded to a chip support such as flip chip bonding, alignment between the chip support and the semiconductor device is required.

7 is a cross-sectional view illustrating an alignment method between a chip support and a semiconductor device using a magnetic material according to another exemplary embodiment of the present invention. In the present embodiment, the magnetic body forming methods of the above-described embodiments are applied in the same manner, and redundant descriptions are omitted. Referring to FIG. 7, the die 256 formed with the semiconductor device 206 and the second magnetic material 216a is brought close to the chip support 160 having the first magnetic material 162a formed thereon, and the semiconductor device may be formed by the magnetic force F. The alignment of the die 206 and the die 256 and the chip support 160 may be performed. The chip support 160 may be made of glass, a polymer such as BCB, a ceramic such as alumina, or a silicon (Si) substrate, and although not shown, metal wires such as contact pads and vias may be formed on the chip support 160. Formed. In FIG. 7, the second magnetic material 216a is manufactured during the manufacturing process of the semiconductor device 206 and exposed to the back surface of the die 256. However, similarly to FIG. 3K or FIG. The present embodiment can also be applied to the case where the manufacturing process is formed on the top surface of a wafer (not shown) or thinned back surface. The present embodiment also has a function of picking up a separate die, such as pick and place equipment, to mechanically move the die 256 to the chip support 160, and then lowering it to a prescribed position. Equipment is available.

8A through 8C are cross-sectional views illustrating alignment and attachment of a semiconductor device using an external magnetic field. In the above-described embodiments, the increase in the magnetic force between the magnetic materials may increase the range of positions where the die may be brought closer or lowered for alignment, thereby speeding up the movement and placing process of the die. An external magnetic field may be used to increase the magnetic force between the magnetic bodies.

Referring to FIG. 8A, when the coil 290 is installed around the wafer 100 and a current flows, the first magnetic body 110a and the second magnetic body 210a may be aligned with each other by the magnetic field generated by the coil 290. More powerful magnetic force (F) will be working.

In addition, when the external magnetic field is applied immediately before the alignment, the magnetic bodies 110a and 210a may not be magnetized in advance. Referring to FIG. 8B, the die 250 including the second nonmagnetic magnetization 210a is first placed on the wafer 100 including the first nonmagnetic magnetization 110a. Then, when a current is caused to flow through the coil 290 to generate a magnetic field, the magnetic bodies 110a and 210a are magnetized so that the attraction force F acts so that the die 250 placed on the wafer 100 is moved to an alignment position. do.

The coil 290 for inducing an external magnetic field may be installed around the wafer 100 as shown in FIGS. 8A and 8B, and the coil 292 may be installed around the die 250 as shown in FIG. 8C. have.

In the above drawings, the use of an external magnetic field has been described taking the case of stacking the die 250 and the wafer 100 as an example, but the external magnetic field may be used in the same manner as the above principle in the stacking of dies and dies and the stacking of dies and chip supports.

9A and 9B are cross-sectional views illustrating an example in which a plurality of semiconductor devices are stacked on one semiconductor device.

9A, a second semiconductor device 202 and a third semiconductor device 302 to be stacked on the first semiconductor device 106 on the wafer 100 are fabricated on a wafer (not shown), respectively. According to the method, the second magnetic body 214a and the third magnetic body 310a are formed, and then each wafer is separated into dies 264 and 350. Subsequently, the die 264 including the second semiconductor device 202 is referred to as a third die, and the die 350 including the second die and the third semiconductor device 302 is referred to as a third die. In addition, the first magnets 116a and 116b are formed on the wafer 100 to act as the second magnetic material 214a or the third magnetic material 310a formed on the dies 264 and 350, respectively. do. Then, the second die 264 is brought close to the first semiconductor device 106 on the wafer 100, and as shown by the magnetic force between the first magnetic body 116a and the second magnetic body 214a, the first semiconductor device as shown. The second die 264 is attached to the wafer 100 by aligning the 106 with the second semiconductor element 202. Subsequently, the third die 350 is brought close to the first semiconductor element 106, and the alignment and the third die of the third semiconductor element 302 are caused by the magnetic force between the first magnetic body 116b and the third magnetic body 310a. Attachment 350 is made.

FIG. 9B illustrates a method of aligning and attaching a plurality of semiconductor devices to one semiconductor device during die-to-die stacking. The wafer 100 illustrated in FIG. 9A is separated into a first die 154 including the first semiconductor element 106 and fixed to a support stand (not shown), and then the second die 264 is approached. The alignment of the second semiconductor element 202 and the second die 264 are attached by the magnetic force between the first magnetic body 116a and the second magnetic body 214a. Subsequently, the third die 350 is approached to the first die 154 so that the alignment and the third die of the third semiconductor device 302 are caused by the magnetic force between the first magnetic body 116b and the third magnetic body 310a. 350 to be attached. Although not shown, a plurality of dies may be stacked on the chip support through the above-described method, and an external magnetic field may be used to increase the magnetic force between the magnetic bodies. In the above-described examples, two semiconductor devices are stacked on one semiconductor device, but three or more semiconductor devices may be stacked on one semiconductor device in the same manner.

10A to 10C illustrate an example in which a die is stacked on a wafer using the above-described alignment method and then electrically connected to the die and the semiconductor devices formed on the wafer, respectively.

Referring to FIG. 10A, a second semiconductor is coated after an insulating material 360 such as polyimide, BCB, or epoxy is coated on the wafer 100 on which the first semiconductor device 102 and the first magnetic body 110a are formed. The dies 250 in which the element 202 and the second magnetic body 210a are formed are aligned and attached in the above-described manner. The dies 250 are then secured to the wafer 100 by curing the insulating material 360. Subsequently, a via hole 370 is formed from an upper portion of the die 250 to a landing pad 108 formed in the first semiconductor device 102 through the second semiconductor device 202 and the insulating material 360. do. Although not shown, the landing pad 108 is connected to the metal wires of the first semiconductor device 102.

Subsequently, referring to FIG. 10B, a silicon oxide film or a silicon nitride film is deposited on the entire surface of the resultant to form an insulating film liner layer, and then the entire surface is etched to leave the insulating film liner 380 only on the side of the via hole 370. 108) Expose the top. Subsequently, a via hole in which the insulation layer liner 380 is formed is filled with a metal layer to form a first via 382.

Subsequently, as shown in FIG. 10C, a via hole extending to the landing pad 208 of the second semiconductor device 202 is formed by the above-described method, and then an insulating film liner 390 and a second via 392 are formed. Finally, the first semiconductor device 102 and the second semiconductor device 202 are formed by forming a metal wiring 396 connecting the first and second vias 382 and 392 on the second semiconductor device 202. Connect electrically.

11A to 11E illustrate a method of forming a bump as an example of fabricating interconnects that form electrical connections between stacked semiconductor devices or between semiconductor devices and chip support terminals when fabricating a semiconductor structure using the above-described alignment method. Is shown.

Referring to FIGS. 11A and 11B, in FIG. 11A, a magnetic material 420 is formed on the top surface of a wafer 400 having a contact pad 410 by using the aforementioned method. Here, since the upper surface means the upper portion in the drawing, the wafer may be the front surface or the rear surface of the actual wafer. Although not shown, the wafer 400 includes a semiconductor device, and the contact pad 410 is connected to a metal wiring of the semiconductor device. After the magnetic body 420 is formed, when the magnetic protective layer 422 is further formed, the upper surface of the contact pad 410 is exposed through a photo and etching process as shown in FIG. 11B. In the following drawings, for the sake of simplicity, the magnetic protection layer 422 is not formed.

Referring to FIG. 11C, an under bump metal (UBM) layer 430 is formed on the entire surface of the upper surface of the wafer 400 on which the contact pads 410 and the magnetic material 420 are formed, and then bump regions of the UBM layers 430. A photoresist pattern 440 having an opening 442 exposing the photoresist is formed on the surface of the UBM layer 430. The UBM layer 430 may be made of Ti, Ta, Cr, Ni, Cu, Pd, Au, or a combination thereof and is formed through a sputtering or plating method.

11D and 11E, a bump material is formed in the opening 442 formed by the photoresist pattern 440 through a plating method, and then the photoresist pattern 440 is removed, followed by the UBM layer 430. A portion formed outside the bump area of the wafer) is removed to form a bump 450 protruding from the upper surface of the wafer 400 as shown in FIG. 11D. For stud bumps that do not require reflow after the bumps 450 are formed, Cu or Au is preferable as a bump material, and in the case of solder bumps that require shape formation through reflow, bumps are required. As the material, one selected from Pb, Sn, Cu, Ni, Ag, Bi, In and alloys thereof may be used. In the case of solder bumps, the bumps 450 may be reflowed to reshape the bumps 450 'close to a spherical shape as shown in FIG. 11E.

12A to 12C are cross-sectional views illustrating another method for forming solder bumps. Referring first to FIG. 12A, a photoresist pattern 460 having an opening 462 exposing the contact pad 413 is formed on the wafer 400 on which the contact pad 413 and the magnetic body 420 are formed. Subsequently, the solder paste 470 is filled in the opening 462 as shown in FIG. 12B. Finally, if the solder paste 470 is reflowed after the photoresist pattern 460 is removed, the solder bumps 470 ′ close to a sphere illustrated in FIG. 12C may be obtained. The formation of the solder bumps 470 'according to the above method may be performed when the metal capable of wetting the solder, such as Cu, constitutes the contact pad 413, or the upper surface of the contact pad 413 may wet the solder. It is preferable to apply when coated with metal.

On the other hand, another method of forming the Cu or Au stud bump described above is to form a ball at the end of the Cu or Au wire using a ball bonder (bond) to the contact pad of the wafer or die, and then cut the wire portion The bumps are formed on the contact pads.

In the above examples, only the bumps formed on the wafer have been described, but bumps can be formed on the package substrate such as the chip support in the same manner.

13A to 13D illustrate a method of manufacturing a semiconductor structure using a magnetic material according to another embodiment of the present invention. In this embodiment, an interconnect made of solder bumps is used as a connecting means for forming a semiconductor structure.

Referring to FIG. 13A, the interconnect 630 including the magnetic material 620 and the solder bumps is formed on the wafer having the contact pad 610 by the above-described method, and then separated into a die 600. Although not shown here, the contact pad 610 is connected to the metal wiring of the semiconductor device formed on the die 600. After separation into the die 600, the magnetic material 520 formed in the substrate 500 is formed by bringing the die 600 close to the substrate 500 such that the interconnect 630 is aligned with the corresponding contact pad 510 on the substrate 500. The die 600 is moved to the alignment position by the magnetic force F between the (hereinafter referred to as the first magnetic material) and the magnetic material 620 (hereinafter referred to as the second magnetic material) formed in the die 600. The substrate 500 becomes a wafer during die-to-wafer stacking and during die-to-die stacking. It becomes a corresponding die, and chip support in die packaging. Although not shown, the corresponding contact pad 510 is connected to the metal wiring or the chip support wiring of the semiconductor device formed on the substrate 500.

13B and 13C, when the interconnect 630 and the corresponding contact pad 510 are aligned by the magnetic force between the first magnetic body 520 and the second magnetic body 620, as shown in FIG. 13B. Interconnect 630 is positioned directly above the corresponding contact pad 510. Then, when the temperature is increased to reflow interconnect 630, the molten solder causes the corresponding contact pad 510 to wet. At this time, if the balance of the force between the magnetic force F and the surface tension of the molten solder to achieve the excessive proximity of the die 600 and the substrate 500 can be prevented to prevent the fusion between the molten solder. To this end, the magnetic force may be weakened by applying an external magnetic field opposite to the magnetic field formed by the first and second magnetic bodies 520 and 620 before the interconnect 630 is completely melted. Alternatively, when the magnetic material constituting the magnetic material is selected, a material that greatly weakens the magnetic at the melting temperature of the interconnect 630 may be selected. Subsequently, lowering the temperature again forms a semiconductor structure in which the substrate 500 and the die 600 are connected through an interconnect 630 ′ as shown in FIG. 13C.

FIG. 13D shows that an interconnect 530 made of solder bumps is formed on a substrate 500 having contact pads 512 and a die 600 is provided with a corresponding contact pad 612 to be connected to the interconnect 530. The case is illustrated. As such, when the interconnect 530 is formed on the substrate 500, the weight of the die 600 is lightened so that the magnetic force F can move the die 600 more effectively. Even in this case, after the interconnect 530 and the corresponding contact pad 612 are aligned, the semiconductor structure to which the substrate 500 and the die 600 are connected as shown in FIG. 13C may be formed through the reflow of the interconnect 530. Can be.

In the present exemplary embodiment, the interconnect 630 formed of the solder bumps is directly formed on the contact pad 610. However, the present exemplary embodiment may be applied in the case where the UBM is further formed between the interconnect 630 and the contact pad 610. FIG. .

13C, the die 600 stacked on the substrate 500, the interconnect 630 ′ positioned between the substrate 500 and the die 600, and the interconnect ( The semiconductor structure may include a first magnetic body 520 formed on the substrate 500 and a second magnetic body 620 formed on the die 600.

14A to 14C illustrate methods for preventing fusion between molten solder when the die and the substrate are connected by the aforementioned solder bumps.

Referring to FIGS. 14A and 14B, the substrate 500 and the die 600 have the same structure as that of FIG. 13B except that a fusion barrier 640 is formed between interconnects 630 formed of solder bumps. Has The fusion barrier 640 is made of an insulating material such as silicon oxide, silicon nitride, or BCB, and is preferably formed before the interconnect 630 is fabricated. When the die 600 is brought close to the substrate 500 according to the above-described alignment method, the interconnect 630 is connected to the corresponding contact as shown in FIG. 14A by the action of the first magnetic body 520 and the second magnetic body 620. It is aligned with the pad 510. Increasing the temperature then causes the interconnect 630 to melt and the molten solder 630 ″ wets the corresponding contact pad 510 as shown in FIG. 14B. At this time, when the die 600 is close to the substrate 500 by the magnetic force F, the molten solder 630 ″ may be flatly deformed and fused to each other, and the molten solder 630 by the fusion barrier 640. Can block interfusion). Another use of the fusion barrier 640 is to act as a spacer between the substrate 500 and the die 600, whereby the die 600 is close to the substrate 500 by the magnetic force F and then the fusion barrier 640. When contacted with the substrate 500, no further proximity is made. The action of the magnetic force F and the fusion barrier 640 thus brings the die 600 close to the substrate 500 to a controlled distance, such that the molten solder 630 '' contacts the corresponding contact pad 510 more reliably. You can do that. Once the wetting is completed, the external magnetic field is used to weaken the magnetic force to restore the flattened shape of the molten solder 630 '' and then to lower the temperature, or lower the temperature while the magnetic force is applied to the die (600). ) And the substrate 500 are completed.

Referring to FIG. 14C, when the first magnetic body 522 is formed on the substrate 500, and the height thereof is attached to the second magnetic body 620 formed on the die 600, the magnetic bodies 522 and 620 may be attached. Allows you to act as a pacer. Then, as shown, the molten solder 630 ″ is pressed only to a distance between the die 500 and the substrate 500 where the magnetic materials 522 and 620 are attached, thereby avoiding fusion. Although the thickness of the first magnetic material 522 formed on the substrate 500 is changed in the drawing, the thickness of the second magnetic material 620 formed on the die 600 may be changed, and the thicknesses of the two magnetic materials 522 and 620 may be changed. You may change thickness together.

15A to 15C illustrate a method of manufacturing a semiconductor structure using a magnetic material according to another embodiment of the present invention. In this embodiment, bumps made of materials other than solder are used as interconnects to make the connections necessary to form the semiconductor structure.

Referring to FIG. 15A, a magnetic material 620 and a material other than solder are formed on a wafer having a contact pad 614, and a stud bump-type interconnect 650 is formed and then die 600. Separate. Cu or Au may be used as a material other than the solder constituting the interconnect 650. Although not shown, the contact pad 614 is connected to the metal wiring of the semiconductor device formed on the die 600. After separation into the die 600, the first magnetic body formed on the substrate 500 is formed by bringing the die 600 close to the substrate 500 such that the interconnect 650 is aligned with the corresponding contact pad 514 on the substrate 500. The die 600 is moved to the alignment position by the magnetic force F between the second magnetic material 620 formed in the die 600 and 520. The substrate 500 becomes a wafer when the die and the wafer are stacked, and becomes a corresponding die when the die and the die are stacked, and also becomes a chip supporter during die packaging. Although not shown, the corresponding contact pads 514 are connected to the metal wirings or the chip support wirings of the semiconductor device formed on the substrate 500.

Referring to FIG. 15B, when the interconnect 650 and the corresponding contact pad 514 are aligned by a magnetic force between the first magnetic body 520 and the second magnetic body 620, the interconnect 650 may correspond to the corresponding contact pad 514. ), An adhesive material (not shown), such as an anisotropic conductive adhesive, may be sandwiched between the substrate 500 and the die 600 for firm contact. Alternatively, when the temperature is increased while applying pressure to the die 600 in the aligned state, atomic diffusion may occur at the interface between the interconnect 650 and the corresponding contact pad 514 to form a metal junction. Pressure may be applied by mechanically pressing the die 600, or by applying an external magnetic field, the magnetic bodies 520, 620 formed on the substrate 500 and the die 600 generate a magnetic force F more strongly, thereby interconnect 650. ) And a pressure may be applied to the interface between the corresponding contact pad 514. Typically, the bonding temperature is increased to about 350 ℃ to 400 ℃ by applying ultrasonic waves can be lowered the bonding temperature.

15C shows that an interconnect 550 made of a material other than solder is formed on a substrate 500 having a contact pad 516 and a die 600 has a corresponding contact pad 616 to be connected to the interconnect 550. The case is shown. As such, when the interconnect 550 is formed on the substrate 500, the weight of the die 600 is lighter, as in the case of solder bumps, so that the magnetic force F can move the die 600 more effectively.

In this embodiment, the interconnect 650 made of a material other than solder is formed directly on the contact pad 614. However, the above-described embodiment is the same even when the UBM is further formed between the interconnect 650 and the contact pad 614. FIG. Is applied.

According to this embodiment, as shown in FIG. 15B, the die 600 stacked on the substrate 500, the interconnect 650 positioned between the substrate 500 and the die 600, and the interconnect ( A semiconductor structure comprising a first magnetic body 520 formed on the substrate 500 for aligning the 650 and a second magnetic body 620 formed on the die 600 is completed.

16A and 16B illustrate a method of manufacturing a semiconductor structure using a magnetic material according to another embodiment of the present invention. In this embodiment, the connection between the substrate and the die is made by bonding between bonding pads. The bonding pads may be the same as the contact pads used in the embodiments described above and the location at which they are formed, but they may be formed on the pads and dies formed on the substrate without the aid of other mediators, such as bumps, to connect the dies to the substrate. Unlike pads, the pads form a direct bond.

Referring to FIG. 16A, a first bonding pad 518 is formed on the substrate 500 to protrude from the upper surface of the substrate 500. In the drawing, only the first bonding pad 518 on the substrate 500 protrudes, but the second bonding pad 618 formed on the die 600 may protrude. The first and second bonding pads 518 and 618 may be connected to a metal wiring (not shown) of a semiconductor device. The first and second bonding pads 518 and 618 may be made of Cu or Au, or the surface may be coated with a Cu or Au film to facilitate metal bonding. To do that. As shown in the drawing, the first magnetic material 524 formed on the substrate 500 and the second magnetic material 624 formed on the die 600 do not protrude further than the first and second bonding pads 518 and 618. Fabrication is performed to prevent the bonding between the bonding pads 518 and 618 in a subsequent process. Subsequently, when the die 600 is brought close to the substrate 500 as described above, the die 600 is moved to the alignment position by the magnetic force F between the first magnetic body 524 and the second magnetic body 624. . Herein, the substrate 500 becomes a wafer when the die and the wafer are stacked, and becomes a corresponding die when the die and the die are stacked, and becomes a chip support during die packaging.

Then, as shown in FIG. 16B, the second bonding pads 618 formed on the die 600 and the first bonding pads 518 formed on the substrate 500 are aligned and brought into contact with each other. When R is raised, atomic diffusion occurs at the interface between the bonding pads 518 and 618 to form a metal junction. Pressure may be applied by mechanically pressing the die 600, or by applying an external magnetic field, the magnetic bodies 524 and 624 formed on the substrate 500 and the die 600 generate a magnetic force F more strongly, thereby bonding the bonding pads. Pressure may be applied to the interface between the holes 518 and 618. Typically, the bonding temperature is increased to about 350 ℃ to 400 ℃ by applying ultrasonic waves can be lowered the bonding temperature.

According to the present embodiment, as shown in FIG. 16B, the substrate 500 having the first bonding pad 518 thereon and the substrate 500 stacked on the substrate 500 may be connected to the first bonding pad 518. A die 600 having a second bonding pad 618, and a first magnetic body 524 formed on the substrate 500 to align the first bonding pad 518 and the second bonding pad 618. And a second magnetic body 624 formed on the die 600 is completed.

17A and 17B schematically illustrate an example in which the above-described embodiments are applied. Referring to FIG. 17A, a substrate interconnect 14 and a first die magnetic body may include a substrate interconnect 14 formed of a substrate contact pad 12 formed on an upper surface of the substrate 10 and a stud bump formed below the first die 20. It is aligned and connected by the operation of (24). The first die magnetic body 24 is manufactured during an element (not shown) forming process so as to form up to the inside of the first die 20, and is aligned in the upper surface direction as well as the lower surface of the first die 20. Make sure you have the necessary magnetic force. After connecting the first die 20 to the substrate 10, a second die 30 having a second interconnect 36 made of solder bumps and a fusion barrier wall 38 formed thereon is stacked on the first die 20. do. At this time, the alignment between the second interconnect 36 and the first die contact pad 22 is performed by the magnetic force between the first die magnetic body 24 and the second die lower magnetic body 34b. Finally, a third die 40 having a third interconnect 46 made of solder bumps is stacked over the second die 30. At this time, the alignment between the third interconnect 46 and the second die contact pad 32 is performed by the magnetic force between the second die upper magnetic body 34t and the third die magnetic body 44. The third die magnetic body 44 protrudes to act as a spacer. The dies 20, 30, and 40 aligned as described above are maintained in the attached state by the magnetic force by the magnetic bodies 24, 34b, 34t, and 44. Subsequently, when the temperature is increased to reflow the second and third interconnects 36 and 46 formed of the solder bumps, the first die contact pad 22 and the second die contact pad 32 are shown in FIG. 17B. The connection is made while wetting.

As described above, in the present invention, the alignment between semiconductor elements in stacking dies and wafers and the stacking of dies and dies, and the alignment of chip support and semiconductor elements in stacking dies and chip supports, are performed. It is caused by the magnetic force between the magnetic bodies formed in each part to shorten the time required for the alignment. In addition, after alignment of the semiconductor device, the alignment state may be maintained by a magnetic force until the subsequent process, and thus, various semiconductor structures using die stacking may be manufactured.
On the other hand, the present invention is not limited to the above-described embodiment, various modifications are possible by those skilled in the art within the spirit and scope of the present invention described in the claims to be described later.

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Claims (36)

delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete Board; A die stacked on the substrate; Solder bumps connecting the substrate and the die between the substrate and the die; A fusion barrier formed between the solder bumps; And And a first magnetic material formed on the substrate and a second magnetic material formed on the die to align the solder bumps. Board; A die stacked on the substrate; Solder bumps connecting the substrate and the die between the substrate and the die; A first magnetic material formed on the substrate and a second magnetic material formed on the die to align the solder bumps; Including; And the first magnetic body and the second magnetic body serve as spacers for controlling a gap between the substrate and the die. The method of claim 22 or 23, The substrate is a semiconductor structure, characterized in that the wafer on which the semiconductor device is formed. The method of claim 22 or 23, The substrate is a semiconductor structure, characterized in that the die on which the semiconductor element is formed. The method of claim 22 or 23, And the die comprises a semiconductor device. The method of claim 22 or 23, The substrate is a semiconductor structure, characterized in that the chip support. The method of claim 22 or 23, The solder bumps are selected from Pb, Sn, Cu, Ni, Ag, Bi, In and alloys thereof. The method of claim 27, The solder is a semiconductor structure, characterized in that selected from Pb, Sn, Cu, Ni, Ag, Bi, In and alloys thereof. delete delete delete delete delete delete delete

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