KR20060053068A - Multi-bit semiconductor memory device and methods of manufacturing and operating the same - Google Patents

Abstract

A semiconductor layer formed in a line shape having a predetermined length and width on the substrate, and having a first source, a channel region, and a first drain sequentially formed in the longitudinal direction, and a channel region of the semiconductor layer. A second source and a second drain formed on the substrate so as to be symmetrical, a first insulating layer covering the channel region of the semiconductor layer and partially extending onto the second source and the second drain, and on the first insulating layer And a three-dimensional data storage layer having a plurality of storage nodes, a second insulating layer covering the data storage layer, and a gate electrode formed on the second insulating layer. A multi-bit semiconductor memory device is provided.

Description

Multi-bit semiconductor memory device and methods of manufacturing and operating the same

1 is a plan view of a multi-bit semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along the line AA ′ of FIG. 1.

3 is a cross-sectional view taken along the line BB ′ in FIG. 1.

4 is a perspective view of the semiconductor memory device shown in FIG. 1.

5 through 10 are cross-sectional views illustrating a method of manufacturing the semiconductor memory device illustrated in FIG. 4.

FIG. 11 is a plan view of a semiconductor memory device in a step before forming a deep impurity layer on a semiconductor substrate after forming a gate electrode in the semiconductor memory device shown in FIG. 4.

12 is a plan view of the semiconductor memory device after the source and the drain of the LDD structure are formed on the semiconductor substrate in the semiconductor memory device shown in FIG. 4.

13 and 14 are front and back views of the semiconductor memory device shown in FIG. 1 showing a storage node.                 

* Description of the symbols for the main parts of the drawings *

40: semiconductor substrate 42: semiconductor layer

44, 46: First source and first drain formed in semiconductor layer 42

48, 52: first and second insulating layers 50: data storage layer (trap layer)

54 gate electrode 64 second source

66: second drain 64a, 66a: first and second impurity layers

64b, 66b: third and fourth impurity layers M1: mask

A1: arrow pointing to the front of the semiconductor memory element

A2: arrow pointing to the back of the semiconductor memory device

R1: predetermined area of uneven portion P: uneven portion

P1: Convex portion of the uneven portion P2: Concave portion of the uneven portion

S1..S8: First to Eighth Storage Nodes

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a multi-bit semiconductor memory device capable of storing one byte of data in a unit cell, and a method of manufacturing and operating the same.

With the development of semiconductor technology and wafer processing technology, the degree of integration of nonvolatile semiconductor memory devices is approaching the level of DRAM. In addition, as the implementation of nonvolatile memory devices using existing DRAM structures and processes becomes easier, recent issues have been focused on the multi-bitization of memory devices.

Accordingly, a memory device using a gate as a storage node in a structure of a conventional field effect transistor, for example, a sonos memory device, has been introduced.

Sonos memory devices introduced to date are clearly a multi-bit memory device capable of recording two-bit bit data, whereas the conventional memory device is a single-bit memory device that can store only one bit data, that is 1 or 0 Do.

Eight different memory states are required to write three-digit bit data 111, 110 ... 001, 000. Most of the multi-bit memory devices introduced to date have four different memory states. Therefore, it is difficult to write three-digit bit data using the multi-bit memory device introduced to date.

SUMMARY OF THE INVENTION The present invention has been made in an effort to improve the above-described problems of the related art, and provides a multi-bit memory device capable of having eight different memory states and writing three-bit bit data.

Another object of the present invention is to provide a method of manufacturing such a multi-bit memory device.

Another object of the present invention is to provide a method of operating such a multi-bit memory device.

In order to achieve the above technical problem, the present invention is a semiconductor layer formed in a line shape having a predetermined length and width on the substrate, the first source, the channel region and the first drain in the longitudinal direction in order And a first source and a second drain formed on the substrate so as to be symmetrical about the channel region of the semiconductor layer, and a first portion that surrounds the channel region of the semiconductor layer and partially extends onto the second source and the second drain. An insulating layer, a three-dimensional data storage layer formed to surround the channel region on the first insulating layer, and having a plurality of storage nodes; a second insulating layer covering the data storage layer; 2 provides a multi-bit semiconductor memory device comprising a gate electrode formed on the insulating layer.

The data storage layer may be a nitride layer having a predetermined trap density.

The data storage layer may be a trap material layer having eight storage nodes spaced apart.

According to an aspect of the present invention, there is provided a method of forming a semiconductor layer having a line shape having a rectangular cross section on a substrate, and having a predetermined depth in a predetermined region of the substrate that is symmetric about the semiconductor layer. Forming a first and a second impurity layer, and sequentially forming a first insulating layer, a data storage layer, a second insulating layer, and a gate electrode layer covering the semiconductor layer and the first and second impurity layers on the substrate. Exposing a portion other than a portion adjacent to the semiconductor layer in the first and second impurity layers and a portion except a portion between the first and second impurity layers in the semiconductor layer; Third and fourth impurity layers deeper than the first and second impurity layers are formed in the exposed portions of the first and second impurity layers, and a predetermined conductive impurity is formed in the exposed portions of the semiconductor layer. To provide a method of manufacturing a multi-bit semiconductor memory device comprising the steps of: doping.

In such a manufacturing method, the semiconductor layer may be formed of a silicon layer.

In addition, the first and second impurity layers may be formed by ion implanting a predetermined conductive impurity on an upper surface of the substrate on which the semiconductor layer is formed.

The data storage layer may be formed of a nitride layer having a predetermined trap density.

The remainder except for a portion adjacent to the semiconductor layer in the first and second impurity layers and the remainder except for a portion between the first and second impurity layers in the semiconductor layer may be simultaneously exposed.

According to another embodiment of the present invention, the first and second impurity layers are first exposed except for a portion adjacent to the semiconductor layer, and then a portion between the first and second impurity layers in the semiconductor layer is exposed. You can expose the rest, or vice versa.

The formation of the third and fourth impurity layers and the doping of the conductive impurities to the exposed portions of the semiconductor layer may be simultaneously performed, but may be performed in a different order.

In order to achieve the above another technical problem, the present invention is a semiconductor layer formed on the substrate in a line shape having a predetermined length and width, the first source, the channel region and the first drain in the longitudinal direction, and A second source and a second drain formed on the substrate so as to be symmetrical about the channel region of the semiconductor layer, and a first insulating layer covering the channel region of the semiconductor layer and partially extending onto the second source and the second drain And a three-dimensional data storage layer formed to surround the channel region on the first insulating layer, the data storage layer having a plurality of storage nodes, a second insulating layer covering the data storage layer, and the second insulating layer. In the operating method of a multi-bit semiconductor memory device comprising a gate electrode formed on a layer,

A predetermined write voltage is applied to the gate electrode, and a predetermined voltage is applied to the first and second sources and the first and second drains, thereby selecting one of the plurality of storage nodes of the data storage layer. And a first step of writing bit data.

In addition, a voltage different from the predetermined voltage is applied to at least one of the first and second sources and the first and second drains while the write voltage is applied to the gate electrode. The method may further include a second step of writing 1-bit data to any one of the plurality of storage nodes that is not selected.

The second step can be repeated.

In order to achieve the above another technical problem, the present invention is a semiconductor layer formed on the substrate in a line shape having a predetermined length and width, the first source, the channel region and the first drain in the longitudinal direction, and A second source and a second drain formed on the substrate so as to be symmetric about the channel region of the semiconductor layer, and a first insulating layer covering the channel region of the semiconductor layer and partially extending onto the second source and the second drain And a three-dimensional data storage layer formed to surround the channel region on the first insulating layer, the data storage layer having a plurality of storage nodes, a second insulating layer covering the data storage layer, and the second insulating layer. In the operating method of a multi-bit semiconductor memory device comprising a gate electrode formed on a layer,

A first step of applying a predetermined voltage to the first and second sources and the first and second drains while a predetermined read voltage is applied to the gate electrode, between the first source and the first drain A second step of measuring a current flowing through the current flowing between the second source and the second drain, a third step of comparing the current measured in the second step with a reference value, and the measured current reaches the reference value The semiconductor memory device may be configured by comparing the voltage measured in the fourth and fourth steps of measuring the predetermined voltages applied to the first and second sources and the first and second drains with a reference table. And a fifth step of reading data written in the memory.

According to the present invention, since 8-bit data, that is, 1 byte of data, can be written in the unit cell of the memory device, the degree of integration of the memory device can be increased.

Hereinafter, a multi-bit memory device and a method of manufacturing and operating the same according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings. In this process, the thicknesses of layers or regions illustrated in the drawings are exaggerated for clarity.                     

1 is a plan view of a multi-bit semiconductor memory device according to an embodiment of the present invention.

In FIG. 1, reference numeral 40 denotes a semiconductor substrate. The semiconductor substrate p may be, for example, a p-type or n-type silicon substrate. In FIG. 1, it can be seen that a gate electrode 54 having a predetermined length and a narrower width is provided on a predetermined region of the semiconductor substrate 40. Gate electrode 54 may be a common metal such as aluminum, copper, or a silicide electrode such as tungsten silicide. It can be seen that the first source 44 is provided under the gate electrode 54 and the first drain 46 is provided thereon, respectively. Since FIG. 1 is a plan view, it appears that the first source 44 and the first drain 46 are in contact with the gate electrode 54, but in practice, the first source 44 and the first source are shown in FIG. The drain 46 is not in contact with the gate electrode 54. In addition, the width of the first source 44 and the first drain 46 is smaller than the width of the gate electrode 54. 1 also shows that the second source 64 and the second drain 66 are formed in a direction perpendicular to a line (not shown) connecting the centers of the first source 44 and the first drain 46. have. It can be seen that the second source 64 and the second drain 66 extend below the gate electrode 54. However, the second source 64 and the second drain 66 are not in contact with the gate electrode 54 as shown in FIG. 2. In FIG. 1, it can be seen that the second source 64 and the second drain 66 have the same length as the gate electrode 54.

In FIG. 1, the direction indicated by the first arrow A1 is referred to as the front of the multi-bit semiconductor memory device according to the embodiment of the present invention for convenience, and the direction indicated by the second arrow A2 is referred to as the rear.

Next, referring to FIG. 2, which is a cross-sectional view of FIG. 1 taken along the line A-A ', the second source 64 and the second drain 66 are spaced at given intervals, respectively, and have a lightly doped drain (LDD) structure. It can be seen that it is doped with. In addition, it can be seen that the semiconductor layer 42 exists on the semiconductor substrate 40 between the second source 64 and the second drain 66. Referring to FIG. 1 and FIG. 2, it can be seen that the semiconductor layer 42 passes under the gate electrode 54 and is a channel layer connecting the second source 64 and the second drain 66. 3, the semiconductor layer 42 may be formed in a line shape having the same length as the gate electrode 54. In addition, the semiconductor layer 42 may be, for example, a silicon (Si) layer. The channel between the first source 44 and the first drain 46 is formed along the surface of this semiconductor layer 42. 2, it can be seen that the semiconductor layer 42 is covered with the first insulating layer 48. The first insulating layer 48 is used as a tunneling layer through which carriers, such as electrons or holes, which flow into the semiconductor layer 42 can tunnel. The first insulating layer 48 extends over the first source 64 and the first drain 66. The first insulating layer 48 may be a predetermined oxide layer, such as a silicon oxide layer. On the first insulating layer 48 there is a data storage layer 50 to which the carrier which has passed through the first insulating layer 48 is trapped. The data storage layer 50 is provided to cover the semiconductor layer 42 along the surface of the first insulating layer 48. However, the data storage layer 50 is not in contact with the first source 64 and the first drain 66. The data storage layer 50 may be a material film having a trap site of a predetermined density, for example, a nitride film. The data storage layer 50 preferably has the same length as the gate electrode 54. The data storage layer 50 is covered with a second insulating layer 52 having the same length as its own. The second insulating layer 52 passes through the data storage layer 50 to the gate electrode 54 while the carrier tunnels through the first insulating layer 48 and is trapped in the data storage layer 50. It serves to block it from being reached. The second insulating layer 52 is the same material layer as the first insulating layer 48. However, the first and second insulating layers 48 and 52 may be other material layers. The second insulating layer 52 is covered with the gate electrode 54. The gate electrode 54 and the semiconductor substrate 40 are blocked by the first insulating layer 48.

Next, referring to FIG. 3 showing a cross-sectional view of FIG. 1 in the direction B-B ',

It can be seen that the first source 44 and the first drain 46 doped with conductive impurities are present at both ends of the semiconductor layer 42 used as the channel layer. The semiconductor layer 42, the first and second insulating layers 48 and 52, the data storage layer 50, and the gate electrode 54 are sequentially stacked on the semiconductor substrate 40, and all have the same length. It can be seen that it has. Since the conductive impurity is doped in the first source 44 and the first drain 46, the semiconductor layer 42, the first source 44, and the first drain 46 are shown separately for convenience. It is actually formed of the same semiconductor material, for example silicon (Si).

4 is a three-dimensional view of the multi-bit memory device of the present invention shown in FIGS.

Referring to FIG. 4, the positional relationship between the first source 44, the first drain 46, the second source 64, and the second drain 66, the gate electrode 54, and the semiconductor layer 42 are described. The structure of the laminate present between the layers can be seen more clearly.

Next, a method of manufacturing the multi-bit memory device of the present invention shown in FIG. 4 will be described with reference to FIGS.

First, referring to FIG. 5, a mask M1 defining a predetermined region of the semiconductor substrate 40 is formed on the semiconductor substrate 40 having a first thickness t1. The semiconductor substrate 40 may be formed of a p-type or n-type silicon substrate. The mask M1 may be a photoresist pattern. After the mask M1 is formed, the top surface of the semiconductor substrate 40 is anisotropically etched to remove the mask M1. The anisotropic etching is performed until the thickness of the exposed surface of the upper surface of the semiconductor substrate 40 is lowered to the second thickness t2 as shown in FIG. 6. As a result of the anisotropic etching, the uneven portion P is formed on the upper surface of the semiconductor substrate 40. The convex portion P1 of the uneven portion P is a portion covered with the mask M1 of the semiconductor substrate 40, and the concave portion P2 is a portion that has been exposed to the anisotropic etching of the semiconductor substrate 40. The convex portion P1 of the semiconductor substrate 40 becomes the semiconductor layer 42 of the memory element of the present invention shown in FIG. Therefore, the convex part P1 of the uneven part P is shown by 42 from FIG. The term is also described as a semiconductor layer instead of a convex portion. In addition, as shown in FIG. 6, the uneven portion P includes the same patterns that are repeated, and the process for the same patterns in the subsequent process is the same. Therefore, the description of the uneven portion P from the description of FIG. 7 is replaced with the description of the predetermined region R1 of the uneven portion P, which includes one convex portion P1.                     

Referring to FIG. 7, a predetermined conductive impurity I1 is doped on the entire surface of the semiconductor substrate 40 on which the semiconductor layer 42 is formed. In the case where the semiconductor substrate 40 is a p-type semiconductor substrate, the predetermined conductive impurity I1 is preferably an n-type or n + type conductive impurity. Since the doping of the predetermined conductive impurity (I1) is to form a shallow impurity layer in the LDD doping structure, it is preferable to inject with the energy corresponding thereto. First and second impurity regions 64a and 66a are formed in the semiconductor substrate 40 on both sides of the semiconductor layer 42 by the doping of the predetermined conductive impurity I1.

Next, referring to FIG. 8, a first insulating layer 48 covering the first and second impurity regions 64a and 64b is formed on the semiconductor substrate 40. The first insulating layer 48 may be formed of a silicon oxide layer, but may be formed of another insulating layer capable of achieving the tunneling purpose.

Next, referring to FIG. 9, a data storage layer 50 having a trap site having a predetermined density is formed on the first insulating layer 48 to surround the semiconductor layer 42. The data storage layer 50 may be formed of, for example, a silicon nitride film (SiN). Subsequently, a second insulating layer 52 covering the data storage layer 50 is formed on the first insulating layer 48. The second insulating layer 52 may be formed of the same material as the first insulating layer 48, but may be formed of another material.

Next, referring to FIG. 10, the gate electrode 54 is formed on the second insulating layer 52 to surround the data storage layer 50. The gate electrode 54 may be formed of aluminum or copper. Subsequently, predetermined regions of the data storage layer 50, the second insulating layer 52, and the gate electrode 54 sequentially stacked on the first insulating layer 48 and the first insulating layer 48 are sequentially etched. To remove it. The etching is performed until the semiconductor layer 42 and the first and second impurity regions 64a and 64b of the semiconductor substrate 40 are exposed. 11 is a plan view of the result after the etching. Referring to FIG. 11, the gate electrode 54 is removed from the first insulating layer 48 sequentially stacked between the adjacent first impurity regions 64a along the semiconductor layer 42 by the etching. It can be seen that part of 42 is exposed. As a result, the data storage layer 50 and the gate electrode 54 are separated in units of cells by the etching.

Subsequently, predetermined conductive impurities I2 are implanted into the first and second impurity regions 64a and 66a exposed by the etching. At this time, the predetermined conductive impurity (I2) is preferably a conductive impurity of the same type as the conductive impurity (I1) doped in the first and second impurity regions (64a, 66a). The ion implantation energy of the conductive impurity (I2) is higher than that of the ion implantation of the conductive impurity (I1). By the ion implantation, the exposed regions of the semiconductor layer 42 are doped to form first and second sources (see 44 and 46 of FIG. 12). In addition, third and fourth impurity regions 64b and 66b deeper than the first and second impurity regions 64a and 66a are formed in the exposed regions of the first and second impurity regions 64a and 66a, respectively. In this way, the second source 64 made of the first impurity region 64a and the deeper third impurity region 64b is formed in the semiconductor substrate 40 on both sides of the semiconductor layer 42. In addition, a second drain 66 including the second impurity region 66a and the fourth impurity region 66b is formed. 12 is a plan view of the resultant after ion implantation of conductive impurity (I2). By comparing FIG. 11 and FIG. 12, the formation of the first source 44 and the first drain 46 and the position at which the second source 64 and the second drain 66 are formed can be clearly seen. FIG. 10 is a cross-sectional view of FIG. 12 taken along the 10-10 'direction.

After doping the conductive impurity (I2), annealing is performed to diffuse the doped impurity. Subsequently, a metal silicide layer for contact may be formed on a predetermined region of the second source 64 and the second drain 66.

Next, a method of operating a multi-bit memory device according to an exemplary embodiment of the present invention described above will be described with reference to FIGS. 13 and 14.

13 and 14 show the front and back sides of the memory device of the present invention shown in FIG. 1, respectively. Reference numerals S1 to S4 of FIG. 13 denote first to fourth storage nodes, respectively, and reference numerals S5 to S8 of FIG. 14 denote fifth to eighth storage nodes, respectively. The carriers (electrons or holes) passing through the first insulating layer 48 may be selectively trapped in the first to eighth storage nodes S1 S8 according to the applied voltage distribution, and the trapped carriers may be removed.

<Write>

12, 13, and 14, a predetermined write voltage is applied to the gate electrode 54, and the first and second sources 44 and 64 and the first and second drains 46 and 66 are applied. A predetermined voltage is applied to concentrate the electric field on the lower right corner of the semiconductor layer 44 and the lower right corner of the data storage layer 50 corresponding thereto. As a result, carriers, for example, electrons flowing along the surface of the semiconductor layer 44 pass through the first insulating layer 48 and are trapped in the first storage node S1 of the data storage layer 50. At this time, since the memory element of the present invention is in the first state, it is assumed that 8-bit bit data, for example, 00000001 is written in the memory element of the present invention.

In this state, the same write voltage is applied to the gate electrode 54, and then a predetermined voltage different from the above is applied to the first and second sources 44 and 64 and the first and second drains 46 and 66. The carrier may be trapped in the second storage node S2 of the data storage layer 50. Since the memory element of the present invention at this time is in a second state different from the first state, it is assumed that 8-bit bit data, for example, 00000001 is written in the memory element of the present invention.

In the same manner, the memory device of the present invention can have any one of two different powers of eight states, and at this time, it can be regarded that arbitrary one byte of data is recorded in the memory device of the present invention.

<Read>

As described above, when a carrier is trapped in the first to eighth storage nodes S1 S8 of the memory device of the present invention, and when any one byte of data is written to the memory device of the present invention, Current values output through the second drains 46 and 66 may vary.

Accordingly, the predetermined voltage is applied to the first and second sources 44 and 64 and the first and second drains 46 and 66 while the read voltage is applied to the gate electrode 54. The current flowing through 44 and the first drain 46 and the current flowing between the second source 64 and the second drain 66 are measured, and the measured current is compared with a reference value. At this time, when the measured current reaches the reference value, the voltage applied to the first and second sources 44 and 64 and the first and second drains 46 and 66 is measured. The measured voltage is compared with the voltage of the reference table to read one byte of data written in the memory device.

In order to erase the data written to the memory device of the present invention, a voltage having a polarity opposite to a carrier trapped in the data storage layer 50, for example, a negative voltage when an electron is trapped in the data storage layer 50 is gated. Applied to electrode 54;

While many details are set forth in the foregoing description, they should be construed as illustrative of preferred embodiments, rather than to limit the scope of the invention. For example, one of ordinary skill in the art may include the data storage layer 50 in a divided form. In addition, the structure of the first and second sources 44 and 64 and the first and second drains 46 and 66 may be modified while maintaining the overall structure. Therefore, the scope of the present invention should not be defined by the described embodiments, but should be determined by the technical spirit described in the claims.

As described above, the multi-bit semiconductor memory device of the present invention includes a three-dimensional data storage layer having eight storage nodes. Therefore, the memory device of the present invention can write one byte of data per unit cell. Accordingly, in the conventional case, eight 1-bit memory elements or four 2-bit elements are required to write one byte of data, whereas the present invention requires only one memory element, and thus, using the memory element of the present invention, The degree of integration can be significantly higher than before.

Claims (17)

Board; A semiconductor layer formed on the substrate in a line shape having a predetermined length and width, and having a first source, a channel region, and a first drain sequentially formed in a length direction; A second source and a second drain formed on the substrate to be symmetrical about a channel region of the semiconductor layer; A first insulating layer covering the channel region of the semiconductor layer and partially extending onto the second source and the second drain; A three-dimensional data storage layer formed to surround the channel region on the first insulating layer and having a plurality of storage nodes; A second insulating layer covering the data storage layer; And And a gate electrode formed on the second insulating layer. The multi-bit semiconductor memory device of claim 1, wherein the semiconductor layer is a silicon layer. The multi-bit semiconductor memory device of claim 1, wherein each of the second source and the second drain has an LDD structure. The multi-bit semiconductor memory device of claim 1, wherein the data storage layer is a nitride layer. The multi-bit semiconductor memory device of claim 1, wherein the data storage layer is a trap material layer having eight storage nodes spaced apart. Forming a line-shaped semiconductor layer having a rectangular cross section on the substrate; Forming first and second impurity layers having a predetermined depth in a predetermined region of the substrate which is symmetric about the semiconductor layer; Sequentially forming a first insulating layer, a data storage layer, a second insulating layer, and a gate electrode layer covering the semiconductor layer and the first and second impurity layers on the substrate; Exposing a portion of the first and second impurity layers except a portion adjacent to the semiconductor layer and a portion of the semiconductor layer except a portion between the first and second impurity layers; And Forming third and fourth impurity layers deeper than the first and second impurity layers in the exposed portions of the first and second impurity layers, and doping predetermined conductive impurities in the exposed portions of the semiconductor layer. Method of manufacturing a multi-bit semiconductor memory device comprising a. The method of claim 6, wherein the semiconductor layer is formed of a silicon layer. The method of claim 6, wherein the first and second impurity layers are formed by ion implanting predetermined conductive impurities into an upper surface of the substrate on which the semiconductor layer is formed. The method of claim 6, wherein the data storage layer is formed of a nitride layer having a predetermined trap density. 7. The method of claim 6, wherein the remaining portions of the first and second impurity layers except for the portion adjacent to the semiconductor layer and the portions of the semiconductor layer except for the portion between the first and second impurity layers are simultaneously exposed. The manufacturing method of the multi-bit semiconductor memory element. The semiconductor device of claim 6, wherein the first and second impurity layers are first exposed except for a portion adjacent to the semiconductor layer, and then the remainder except for a portion between the first and second impurity layers in the semiconductor layer. Exposing or vice versa, the method of manufacturing a multi-bit semiconductor memory device. 7. The method of claim 6, wherein the formation of the third and fourth impurity layers and the doping of the conductive impurities to the exposed portions of the semiconductor layer are performed simultaneously. 7. The method of claim 6, wherein the formation of the third and fourth impurity layers and the doping of the conductive impurities to the exposed portions of the semiconductor layer are performed in a different order. A semiconductor layer formed in a line shape having a predetermined length and width on the substrate, and having a first source, a channel region, and a first drain sequentially formed in the length direction; A second source and a second drain formed on the substrate to be symmetrical about a channel region of the semiconductor layer; A first insulating layer covering the channel region of the semiconductor layer and partially extending onto the second source and the second drain; A three-dimensional data storage layer formed to surround the channel region on the first insulating layer and having a plurality of storage nodes; A second insulating layer covering the data storage layer; And a gate electrode formed on the second insulating layer. A predetermined write voltage is applied to the gate electrode, and a predetermined voltage is applied to the first and second sources and the first and second drains, thereby selecting one of the plurality of storage nodes of the data storage layer. And a first step of writing the bit data. The data of claim 14, wherein a voltage different from the predetermined voltage is applied to at least one of the first and second sources and the first and second drains while the write voltage is applied to the gate electrode. And a second step of writing 1-bit data into any one of the plurality of storage nodes of the storage layer that is not selected. 16. The method of claim 15, wherein said second step is repeated. A semiconductor layer formed in a line shape having a predetermined length and width on the substrate, and having a first source, a channel region, and a first drain sequentially formed in the length direction; A second source and a second drain formed on the substrate to be symmetrical about a channel region of the semiconductor layer; A first insulating layer covering the channel region of the semiconductor layer and partially extending onto the second source and the second drain; A three-dimensional data storage layer formed to surround the channel region on the first insulating layer and having a plurality of storage nodes; A second insulating layer covering the data storage layer; And a gate electrode formed on the second insulating layer. A first step of applying a predetermined voltage to the first and second sources and the first and second drains while applying a predetermined read voltage to the gate electrode; Measuring a current flowing between the first source and the first drain and a current flowing between the second source and the second drain; A third step of comparing the current measured in the second step with a reference value; A fourth step of measuring the predetermined voltage applied to the first and second sources and the first and second drains when the measured current reaches the reference value; And And a fifth step of reading data written in the semiconductor memory device by comparing the voltage measured in the fourth step with a reference table.

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