KR20060030720A - Method for forming of semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a semiconductor device, wherein a three-step CMP process such as an ILD oxide CMP, a metal layer CMP, and a nitride film CMP for a SAC process is performed to form a damascene gate according to the prior art. Should be. At this time, in order to solve the problem that an appropriate slurry exists in the ILD oxide film and the metal layer CMP, but an appropriate slurry does not exist in the case of the nitride film CMP, the slurry used in the above step may be an acid slurry using a silica abrasive or another additive to the silica abrasive. By performing the CMP of all the steps using the above, it is possible to solve the inconvenience of using a different slurry of the prior art, in particular in the case of the nitride film CMP is a technology that provides a commercially available slurry.

Description

Method of forming a semiconductor device {METHOD FOR FORMING OF SEMICONDUCTOR DEVICE}

1A to 1I are cross-sectional views illustrating a method of forming a semiconductor device in accordance with the present invention.

2 is a graph showing the polishing rate for the oxide film and the nitride film according to the change of the abrasive content.

3 is a graph showing the change in the etching selectivity of the oxide film to the nitride film according to the change of the abrasive content.

4 is a graph showing the change in slurry pH according to the dilution ratio of DI water.

5 is a graph showing the reverse selectivity ratio of the slurry according to chemical addition.

<Explanation of Signs of Major Parts of Drawings>

10 semiconductor substrate 20 gate oxide film

30 polysilicon layer 40 spacer

50: ILD oxide layer 60: damascene gate region

70 gate dielectric layer 80 metal layer

90: nitride film

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a semiconductor device, and in order to form a damascene gate, all the slurries used in the CMP process are made of acidic slurry or functional chemicals are added to the acidic slurry to prevent dishing. And it relates to a method for manufacturing a semiconductor device easy to implement reverse selectivity.

Although not shown, a method of manufacturing a semiconductor device according to the related art is as follows.

A gate structure including a source / drain region having an LDD structure and having a gate oxide layer and a polysilicon layer is formed on the semiconductor substrate, and an ILD oxide layer is formed over the semiconductor substrate.

Next, the ILD oxide layer is planarized and etched by a CMP process using a first slurry to expose the polysilicon layer, and the polysilicon layer and the gate oxide layer are removed to form a damascene gate region.

Subsequently, a gate dielectric material layer and a metal layer filling the damascene gate region are sequentially formed, and the ILD oxide layer is exposed by planarization etching of the metal layer and the gate dielectric material layer by a CMP process using a second slurry.

Finally, the gate dielectric material layer and the metal layer of the damascene gate region are etched to a predetermined depth, a nitride film is formed to fill the damascene gate region, and the nitride film is subjected to a CMP process using a third slurry, thereby performing ILD oxide film and Allow the gate to be exposed.                         

In this case, the first, second and third slurry is used by adopting a slurry for each process, but there is a problem that the dishing and corrosion action occurs because there is no perfect slurry for each process. . In addition, in the final step of the nitride film CMP process, the third slurry needs to implement a reverse selectivity, but there is a problem that the commercialized nitride film CMP slurry does not exist.

In order to solve the above problems, the present invention, by using the same acid slurry for each of the first, second and third slurry, not different kinds, it is possible to prevent dishing of the oxide film and to easily etch the metal layer, and also to improve the polishing rate. It is an object of the present invention to provide a method for forming a semiconductor device which can be increased and which can facilitate the reverse selection ratio in the nitride film CMP process.

Method for forming a semiconductor device according to the present invention for achieving the above object,

(a) forming an ILD oxide film on a semiconductor substrate on which a gate structure including a gate oxide film, a polysilicon layer, and a spacer is formed;

(b) exposing the polysilicon layer by planarizing etching the ILD oxide layer by a CMP process using a slurry containing silica abrasive;

(c) removing the polysilicon layer and the gate oxide layer to form a damascene gate region;

(d) sequentially forming a gate dielectric material layer over the entire surface, and a metal layer filling the damascene gate region;

(e) planarizing etching the metal layer and the gate dielectric material layer by a CMP process using a slurry containing silica abrasive to expose the ILD oxide layer;

(f) etching the gate dielectric material layer and the metal layer of the damascene gate region to a predetermined depth;

(g) forming a nitride film filling the damascene gate region over the entire surface; And

(h) subjecting the nitride film to a CMP process using a slurry containing a silica abrasive to expose the ILD oxide film.

In addition, the step (b) may be a second feature according to the present invention by exposing the polysilicon layer by planarizing etching the ILD oxide film by a CMP process using a slurry containing a ceria abrasive.

Hereinafter, with reference to the accompanying drawings an embodiment of the present invention will be described in detail.

1A to 1I are cross-sectional views illustrating a method of forming a semiconductor device in accordance with the present invention.

Referring to FIG. 1A, an ILD oxide film 50 is formed on a semiconductor substrate 10 on which a gate structure including a gate oxide film 20, a polysilicon layer 30, and a spacer 40 is formed. At this time, a source / drain (not shown) of the LDD structure is formed under the gate structure. In addition, the ILD oxide film 50 is formed of a PE-TEOS oxide film, an O ₃ -TEOS oxide film, a BPSG oxide film, a PSG oxide film, an APL oxide film, an ALD oxide film, an SOG oxide film, or a combination thereof, and preferably has a thickness of 1000 kPa to 10000 kPa. .

Referring to FIG. 1B, the polysilicon layer 30 is exposed by planarizing etching of the ILD oxide layer 50 by a CMP process using a slurry. In this case, the slurry includes 1 to 30 wt% of the abrasive of the colloidal silica base, and more preferably 15 to 30 wt% of the abrasive of the colloidal silica base. The slurry containing the silica abrasive can minimize the dishing phenomenon of the oxide film.

In addition, in this step, as another embodiment, a selectivity ratio of 10: 1 or more (Oxide: Nitride Selectivity> 10: 1) for the oxide film and the nitride film may be used. At this time, it is preferable to add and dilute 1 to 200 times the DI water to the ceria highly selective slurry.

Referring to FIG. 1C, the polysilicon layer 30 and the gate oxide film 20 are removed to form a damascene gate region. In this case, the damascene gate region 60 is defined by the ILD oxide layer 50 embedded between the spacer 40 and the gate structure.

Referring to FIG. 1D, the gate dielectric material layer 70 and the metal layer 80 filling the damascene gate region 60 are sequentially formed on the entire surface of the semiconductor substrate 10.

Referring to FIG. 1E, the metal layer 80 on the ILD oxide layer 50 is etched using a gate CMP mask (not shown) to protrude the metal layer 80 of the damascene gate region 60. This is a pretreatment process for planarizing the etching selectivity of the gate dielectric material layer 70 and the metal layer 80 in the subsequent etching process.

Referring to FIG. 1F, the ILD oxide layer 50 is exposed by planarization etching of the metal layer 80 and the gate dielectric material layer 70 by a CMP process using a slurry. At this time, the slurry is the same slurry used in the CMP process shown in Figure 1b, 0.1 to 1 wt% of organic molecules containing 1 to 6 vol% oxidizing agent H ₂ O ₂ and -NH ₂ group as a stabilizer It may further include.

In addition, the slurry contains 0.5 to 30 wt% of an abrasive having a particle size of 50 to 500 nm, 0.01 to 30 wt% of a nitride film polishing rate improving agent, 0.01 to 30 wt% of an oxidizing agent and 0.01 to 10 wt% of pH control. It is preferable that it is a slurry of pH 2-12 containing it.

Here, the abrasive may be any one of colloidal silica (Colloidal Silica), fumed silica (Fumed Silica), alumina (Al ₂ O ₃ ), ceria (CeO ₂ ), zirconia (ZrO ₂ ) and combinations thereof, but most Preferably, a slurry containing from 15 to 30 wt% of a colloidal silica based abrasive according to a feature of the present invention is used.

Referring to FIG. 1G, the gate dielectric material layer 70 and the metal layer 80 of the damascene gate region 60 are etched to a predetermined depth. In this case, before the subsequent formation of the nitride film 90, anionic, cationic or nonionic surfactant may be further formed to be selectively adsorbed only to the ILD oxide film 50.                     

Referring to FIG. 1H, a nitride layer 90 is formed on the entire surface of the semiconductor substrate 10 to etch the metal layer 80 to fill the damascene gate region 60 exposed to a predetermined depth. In this case, the process of forming the nitride film 90 is performed by using a LP-CVD method using DCS (Dichlorosilance; SiH ₂ Cl ₂ ) and NH ₃ as a source, or using a PE-CVD method using SiH ₄ or NH ₃ as a source. It is preferable to form in thickness of-2000 kPa.

Referring to FIG. 1I, the nitride film 90 is subjected to a CMP process using a slurry to expose the ILD oxide film 50. At this time, the slurry is the same slurry used in the CMP process shown in Figure 1b, containing a colloidal silica-based abrasive 0.01 ~ 50.00 wt%, may further comprise 0.1 ~ 99.9 vol% H ₃ PO ₄ . have. In this case, H ₃ PO ₄ (phosphate) may cause a chemical effect to reverse the etching selectivity of the metal layer 80 and the nitride layer 90.

In order to increase the efficiency of the reverse selection ratio, 0.01 to 99.99 vol% of HNO ₃ + HF solution is added, where HNO ₃ : HF is used as a slurry of 0.01 to 99.99: 99.99 to 0.01 vol%, or HF is added to the slurry. : IPA (Isopropyl alcohol) can also be used by adding 0.01-99.99 vol% of HF + IPA (Isopropyl alcohol) solution which becomes 0.01-99.99: 99.99-0.01 vol%.

2 to 5 are graphs showing the effect of the slurry according to the present invention.

2 is a graph showing the polishing rate for the oxide film and the nitride film according to the change of the abrasive content. As the content of the abrasive is lowered, it can be seen that the rate of polishing is greater than that of the oxide film.

3 is a graph showing the change in the etching selectivity of the oxide film and the nitride film according to the change of the abrasive content. It can be seen that the etching selectivity at about 24.3 wt% is 1: 1 by the difference in etching thickness of the graph of FIG. 2.

4 is a graph showing the change of slurry pH according to the dilution ratio of DI water. If the content of the abrasive is 15 to 30 wt%, the acidity is 2.84 to 3.19 pH, indicating that the slurry used in the present invention is strongly acidic. Thus, etching to the metal layer is also possible.

5 is a graph showing the reverse selectivity ratio tendency of the slurry according to chemical addition.

Referring to FIG. 5, it can be seen that as the chemical content increases, the acidity becomes stronger and the etching ratio to the oxide film and the metal layer increases, and as the chemical content decreases, the slurry becomes basic and the selectivity to the nitride film increases.

As described above, a damascene gate composed of the gate dielectric material layer 70, the metal layer 80, the nitride film 90, and the spacer 40 can be efficiently used by using a slurry containing silica abrasive in common in all CMP processes. It can be formed as.

As described above, in the method of forming a semiconductor device according to the present invention, all of the slurries used in the CMP process in forming a damascene gate are acidic slurries using silica abrasive, and thus, different conventional slurries are used. It can solve the inconvenience of using it. In addition, it is possible to prevent dishing of the ILD oxide, to easily etch the metal layer, to increase the polishing rate, and to freely implement the reverse selectivity for etching the nitride film.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (16)

(a) forming an ILD oxide film on a semiconductor substrate on which a gate structure including a gate oxide film, a polysilicon layer, and a spacer is formed; (b) exposing the polysilicon layer by planarizing etching the ILD oxide layer by a CMP process using a slurry containing silica abrasive; (c) removing the polysilicon layer and the gate oxide layer to form a damascene gate region; (d) sequentially forming a gate dielectric material layer over the entire surface, and a metal layer filling the damascene gate region; (e) planarizing etching the metal layer and the gate dielectric material layer by a CMP process using a slurry containing silica abrasive to expose the ILD oxide layer; (f) etching the gate dielectric material layer and the metal layer of the damascene gate region to a predetermined depth; (g) forming a nitride film filling the damascene gate region over the entire surface; And (h) exposing the ILD oxide film to a nitride film by performing a CMP process using a slurry containing a silica abrasive. The method of claim 1, The ILD oxide film is any one of a PE-TEOS oxide film, an O ₃ -TEOS oxide film, a BPSG oxide film, a PSG oxide film, an APL oxide film, an ALD oxide film, an SOG oxide film, and a combination thereof, and is formed to a thickness of 1000 kPa to 10000 kPa. Method of forming a semiconductor device. The method of claim 1, The CMP process of step (b) is a method of forming a semiconductor device, characterized in that using the acidic slurry of the colloidal silica base of 1 to 30 wt% abrasive. The method of claim 1, The CMP process of step (e) is performed by adding 0.1 to 1 wt% of a stabilizer containing 1 to 6 wt% of an oxidizing agent H ₂ O ₂ and -NH ₂ groups to a slurry substantially the same as the slurry used in the step (b). Method for forming a semiconductor device, characterized in that carried out. The method of claim 1, The slurry of step (e) comprises 0.5 to 30 wt% of abrasive having a particle size of 50 to 500 nm, 0.01 to 30 wt% of nitride film polishing rate improving agent, 0.01 to 30 wt% of oxidizing agent and 0.01 to 10 wt% It is a slurry of pH 2-12 containing the pH adjuster of the semiconductor device formation method characterized by the above-mentioned. The method of claim 1, The nitride film is formed using a LPCVD method using DCS and NH ₃ as a source, or using a PE-CVD method using a SiH ₄ or NH ₃ as a source, and forming a semiconductor device having a thickness of 200 to 2000 GPa. . The method of claim 1, The CMP process of step (h) is a method of forming a semiconductor device, characterized in that performed with an acidified slurry of a colloidal silica base containing 0.01 to 50.00 wt% abrasive. The method of claim 7, wherein A method for forming a semiconductor device, comprising adding H ₃ PO ₄ by 0.1 to 99.9 vol% to the slurry of the colloidal silica base. The method of claim 7, wherein Method for forming a semiconductor device, characterized in that for performing the CMP process by adding 0.01 ~ 99.99 vol% HNO ₃ + HF solution to the slurry of the colloidal silica base The method of claim 9, The method of forming a semiconductor device, characterized in that the ratio of HNO ₃ and HF in the HNO ₃ + HF solution is 0.01 ~ 99.99: 99.99 ~ 0.01 vol%. The method of claim 7, wherein Method for forming a semiconductor device, characterized in that the CMP process by adding 0.01 ~ 99.99 vol% HF + Isopropyl alcohol solution to the slurry of the colloidal silica base. The method of claim 11, The method of forming a semiconductor device, characterized in that the ratio of HF and Isopropyl alcohol in HF + Isopropyl alcohol solution is 0.01 ~ 99.99: 99.99 ~ 0.01 vol%. The method of claim 1, And selectively adsorbing a cationic, anionic or nonionic surfactant only on the ILD oxide film after the step (f). (a) forming an ILD oxide film on a semiconductor substrate on which a gate structure having a gate oxide film, a polysilicon layer, and a spacer is formed; (b) exposing the polysilicon layer by planarizing etching the ILD oxide layer by a CMP process using a slurry containing ceria abrasive; (c) removing the polysilicon layer and the gate oxide layer to form a damascene gate region; (d) sequentially forming a gate dielectric material layer over the entire surface, and a metal layer filling the damascene gate region; (e) planarizing etching the metal layer and the gate dielectric material layer by a CMP process using a slurry containing silica abrasive to expose the ILD oxide layer; (f) etching the gate dielectric material layer and the metal layer of the damascene gate region to a predetermined depth; (g) forming a nitride film filling the damascene gate region over the entire surface; And (h) exposing the ILD oxide film to a nitride film by performing a CMP process using a slurry containing a silica abrasive. The method of claim 14, The CMP process of step (b) is a method of forming a semiconductor device, characterized in that using a high selectivity slurry having a selectivity of 10: 1 or more of the oxide film and the nitride film. The method of claim 15, Method of forming a semiconductor device comprising the step of diluting 1 to 200 times by adding DI water to the ceria high selectivity slurry.

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