KR20060023062A - Semiconductor device including multiple channel tft and single channel tft - Google Patents

Abstract

Provided is a semiconductor device. The semiconductor device includes a first semiconductor layer disposed in one direction on a substrate and a second semiconductor layer disposed in a direction orthogonal to the first semiconductor layer. A gate electrode crossing one region of the first semiconductor layer, the second semiconductor layer, and another region of the first semiconductor layer is sequentially located.

Multichannel TFT, Single Channel TFT, Organic Light Emitting Display

Description

Semiconductor device including multi-channel thin film transistor and single channel thin film transistor

1 is a layout of a unit pixel driving circuit according to the prior art.

2 is a circuit diagram illustrating a unit pixel of an organic light emitting display device according to an exemplary embodiment of the present invention.

3 is a plan view illustrating a semiconductor device according to an embodiment of the present invention.

4A and 4B are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention, taken along cut lines I-I and II-II of FIG. 3.

(Explanation of symbols for main parts of drawing)

D: multichannel TFT S: single channel TFT

121 and 123: semiconductor layer 145: gate line

The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a multi-channel TFT and a single channel TFT.

In general, a thin film transistor (TFT) includes a semiconductor layer having a channel region and source / drain regions, a gate electrode crossing the semiconductor layer, and source / drain electrodes connected to the source / drain regions, respectively. Such TFTs are classified into single channel TFTs and dual channel TFTs according to the number of channel regions. The dual channel TFTs are characterized by less leakage current than the single channel TFTs.

Such TFTs form a unit pixel driving circuit of a liquid crystal display and an organic light emitting display. In particular, the organic light emitting display device has a disadvantage in that the luminance changes according to a small change in the amount of current. Accordingly, the unit pixel driving circuit of the organic light emitting display device includes a plurality of TFTs to compensate for the change in the amount of current. According to the structure of the unit pixel driving circuit, a dual channel TFT and a single channel TFT may be disposed to share a gate electrode with each other.

FIG. 1 is a plan view of a unit pixel driving circuit according to the prior art, limited to a dual channel TFT and a single channel TFT sharing a gate electrode with each other.

Referring to FIG. 1, a first semiconductor layer 21 having a “c” shape and a second semiconductor layer 23 having a linear shape are positioned on a substrate. The gate electrode 45 crossing the semiconductor layers 21 and 23 is positioned on the semiconductor layers 21 and 23. The gate electrode 45 is straight and overlaps the first semiconductor layer 21 twice, and overlaps the second semiconductor layer 23 once. As a result, the first semiconductor layer 21 and the gate electrode 45 on the first semiconductor layer 21 form a dual channel TFT (A), and the second semiconductor layer 23 and the second semiconductor layer The gate electrode 45 on 23 forms a single channel TFT (B).

However, the semiconductor layer having the "c" shape may cause various problems. One of them is, when the semiconductor layers are crystallized using the MILC method, forming contact holes 61 and 63 exposing both ends of the semiconductor layers and exposing the semiconductor layers within the contact holes 61 and 63. Contacting the metal film to form a MIC region in the semiconductor layer below the metal film, and to form a MILC region by lateral crystallization of the remaining regions from the MIC region, wherein the bent portion of the semiconductor layer 21 Is not easily crystallized due to the growth mechanism of MILC grains and can cause many defects. In addition, when the particles fall on the semiconductor layer having the "c" shape in the manufacturing process, the frequency of failure may be high due to the shape.

SUMMARY OF THE INVENTION The present invention has been made in an effort to solve the above-described problems of the prior art, and to provide a semiconductor device in which a frequency of defects is reduced and a defect density in a semiconductor layer is reduced.

In order to achieve the above technical problem, an aspect of the present invention provides a semiconductor device. The semiconductor device includes a first semiconductor layer disposed in one direction on a substrate and a second semiconductor layer disposed in a direction orthogonal to the first semiconductor layer. A gate electrode crossing one region of the first semiconductor layer, the second semiconductor layer, and another region of the first semiconductor layer is sequentially located.

The semiconductor layers may be polycrystalline silicon semiconductor layers having high charge mobility, and the polycrystalline silicon semiconductor layers may be semiconductor layers crystallized using a metal-induced side crystallization method. The semiconductor layer crystallized using the metal-induced side crystallization method is characterized by low contamination of metal, large grain size, and high charge mobility.

The gate line may be a letter 'C'.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings in order to describe the present invention in more detail. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms.

FIG. 2 is a circuit diagram illustrating a unit pixel of an organic light emitting display device according to an exemplary embodiment of the present invention, and illustrates an Nth unit pixel and an N + 1th unit pixel sequentially connected to one data line.

Referring to FIG. 2, when the n-1 th scan line scan [n-1] is selected, the first switching transistor M11 having a gate connected to the n-1 th scan line scan [n-1] is turned on. On, the node N1 connected to the source is initialized according to the initialization voltage Vinit applied to the drain.

Subsequently, when the n th scan line scan [n] is selected, the second switching transistor M12 having a gate connected to the n th scan line scan [n] has an m th data line data [m] connected to a source. The data signal Vdata applied to the first signal is transferred to the first driving transistor M13 connected to the drain. The first driving transistor M13 has a gate and a drain connected to each other to function as a diode. Accordingly, the first driving transistor M13 transfers the data signal to the node N1 connected to the drain and the gate.

The capacitor C1 connected to the node N1 and one electrode charges a voltage corresponding to a difference between the data signal transmitted to the node N1 and the power supply voltage Vdd, thereby maintaining the data signal for a predetermined period of time. In this case, the second driving transistor M14 connected to the gate of the node N1 supplies a current proportional to the magnitude of the data signal of the node N1 to the organic light emitting diode EL1, and the organic light emitting diode ( EL1) emits light corresponding to the supplied current.

The first switching transistor M11 is off while the data signal is maintained at the node N1. At this time, the leakage current of the first switching transistor M11 may cause a malfunction by leaking the data signal held at the node N1. Therefore, the leakage current of the first switching transistor M11 can be reduced by forming the first switching transistor M11 as a transistor having multiple channels. On the other hand, when the first switching transistor M12 is turned on, it is important to quickly transfer the data signal to the first driving transistor M13. Therefore, the first switching transistor M12 is preferably formed of a transistor having a single channel.

Meanwhile, when the n th scan line scan [n] is selected, the first switching transistor M21 of the N + 1 th unit pixel connected to the n th scan line scan [n] is the N + 1 th unit pixel. Initializes the node N2, and then, when the n + 1 th scan line scan [n + 1] is selected, the second switching transistor M22 and the first driving transistor M23 of the N + 1 th unit pixel. In addition, the second driving transistor M24 and the capacitor C2 perform the same function as the N-th unit pixel to emit the organic light emitting diode EL2.

As described above, the first switching transistor M21 of the N + 1th unit pixel and the second switching transistor M12 of the Nth unit pixel are respectively a multichannel transistor and a single channel transistor, and n is the gate line. Share the first scan line (scan [n]).

FIG. 3 is a plan view illustrating a semiconductor device according to an exemplary embodiment of the present invention. In the unit pixel of the organic light emitting display device described with reference to FIG. The figure shown. 4A and 4B are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention, taken along cut lines I-I and II-II of FIG. 3. The region taken along the cutting line I-I of FIG. 2, that is, the multi-channel TFT region, is indicated by D, and the region taken along the cutting line II-II, i.e., the single channel TFT region, is indicated by S. FIG.

3 and 4A, a buffer layer 110 is formed on a substrate 100 having a multichannel TFT region D and a single channel TFT region S. Referring to FIG. The substrate 100 may be a single crystal silicon, glass, quartz, or plastic substrate, and the buffer layer 110 may be a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a multilayer thereof.

An amorphous silicon film is stacked on the buffer layer 110 and the amorphous silicon film is patterned to form a first semiconductor layer 121 and a second semiconductor on the multi-gate TFT region D and the single gate TFT region S. FIG. Each layer 123 is formed. The first semiconductor layer 121 is disposed in one direction on the substrate, and the second semiconductor layer 123 is orthogonal to the first semiconductor layer 121 at a predetermined interval from the first semiconductor layer 121. Are arranged in the direction. In addition, the semiconductor layers 121 and 123 may have a straight line shape. Therefore, in forming the semiconductor layers 121 and 123, an error occurrence frequency may be low even if particles are dropped.

A gate insulating layer 130 is formed on the semiconductor layers 121 and 123. The gate insulating layer 130 may be formed of at least one layer selected from the group consisting of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

A gate conductive layer is formed on the gate insulating layer 130, and the gate conductive layer is patterned to form a gate line 145. The gate line 145 traverses one region of the first semiconductor layer 121, the second semiconductor layer 123, and another region of the first semiconductor layer 121 in order. To this end, the gate line 145 may have a "c" shape. However, it is not limited thereto.

Conductive impurities are implanted into the semiconductor layers 121 and 123 using the gate line 145 as a mask to form conductive regions 121a_1, 121a_2, 121a_3, 123a_1, and 123a_2 in the semiconductor layers 121 and 123. Form. As a result, first source / drain regions 121a_1 and 121a_3 are formed at both ends of the first semiconductor layer 121, and second source / drain regions are formed at both ends of the second semiconductor layer 123. 123a_1 and 123a_2 are formed.

In addition, first channel regions 121b_1 and 121b_2 are defined between the conductive regions 121a_1, 121a_2 and 121a_3 of the first semiconductor layer, and between the conductive regions 123a_1 and 123a_2 of the second semiconductor layer. The second channel region 123b is defined. In other words, one region where the first semiconductor layer 121 overlaps the gate line 145 and the other region are defined as channel regions 121b_1 and 121b_2 of the first semiconductor layer 121. The region where the second semiconductor layer 123 overlaps with the gate electrode 145 is defined as the channel region 123b of the second semiconductor layer 123. Thus, the first semiconductor layer 121 and the gate electrode 145 form a multi-channel TFT (D), and the second semiconductor layer 123 and the gate electrode 145 are a single channel TFT (S). To form.

Subsequently, an interlayer insulating layer 150 covering the gate line 145 and the gate insulating layer 130 is formed on the gate line 145. Contact holes 151 and 153 exposing the source / drain regions 121a_1, 121a_3, 123a_1 and 123a_2 are formed in the interlayer insulating layer 150. The crystallization inducing material layer 157 is stacked and heat-treated on the source / drain regions 121a_1, 121a_3, 123a_1, and 123a_2 exposed in the contact holes 151 and 153. As a result, a region under the contact holes of the semiconductor layers becomes a MIC region, and other regions become a MILC region where crystallization is induced from the MIC region. The crystallization inducing material layer 157 may include at least one metal selected from the group consisting of Ni, Pd, Ti, Ag, Au, Al, Sn, Sb, Cu, Co, Cr, Mo, Tr, Ru, Rh and Cd. Can be used.

Grains in the MILC region, that is, MILC grains, grow in a straight line with directivity. Therefore, the MILC grains in the linear semiconductor layers 121 and 123 may grow without defects.

3 and 4B, the source / drain regions 121a_1, 121a_3, 123a_1, and 123a_2 are removed from the crystallization-inducing material layer 157 of FIG. 4A to remove the source / drain regions 151 and 153. Expose The source / drain regions 121a_1, 121a_3, 123a_1, and 123a_2 are stacked on the exposed source / drain regions, and the stacked source / drain conductive layers are patterned to form the source / drain regions 121a_1, 121a_3, and 123a_1. , The first source / drain electrodes 161 and the second source / drain electrodes 163, respectively, in contact with each other, 123a_2.

As described above, by forming the first semiconductor layer 121 in a straight line, a semiconductor device having a low crystallization defect density and a low occurrence frequency of defects can be manufactured. Further, the second semiconductor layer 123 is formed in a direction orthogonal to the first semiconductor layer 121, and the first channel region 121b_1 of the first semiconductor layer and the channel region of the second semiconductor layer ( 123b and the gate line 142 overlapping the second channel region 121b_2 of the first semiconductor layer may be formed to easily reduce the area occupied by the semiconductor device. Therefore, when such a semiconductor device is applied to a unit pixel circuit of an organic light emitting display device, the aperture ratio can be improved.

In the above-described embodiment, the semiconductor layer is crystallized using a metal-induced side crystallization method, but is not limited thereto. Various crystallization methods, that is, solid phase crystallization (SPC) and excimer laser annealing (ELA) methods ), Sequential lateral solidification (SLS), metal induced rystallization (MIC), etc. can be used. In addition, the above-described embodiment has been described using the top gate type thin film transistor as an example, but it is also applicable to the bottom gate type thin film transistor.

According to the present invention as described above, in the semiconductor device having a multi-channel transistor and a single channel transistor sharing a gate line with each other, by varying the arrangement of the transistors it is possible to reduce the frequency of defects and the defect density in the semiconductor layer. . Furthermore, when the semiconductor device is applied to the unit pixel of the organic light emitting device, the aperture ratio of the organic light emitting device can be improved.

Although described above with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below I can understand that you can.

Claims (4)

A first semiconductor layer disposed in one direction on the substrate and a second semiconductor layer disposed in a direction orthogonal to the first semiconductor layer; And And a gate electrode crossing one region of the first semiconductor layer, the second semiconductor layer, and the other region of the first semiconductor layer in sequence. The method of claim 1, And the semiconductor layers are polycrystalline silicon semiconductor layers. The method of claim 2, And the polycrystalline silicon semiconductor layer is a semiconductor layer crystallized using a metal induced side crystallization method. The method of claim 1, The gate line is a semiconductor device characterized in that the "c" shape.

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