KR20060019270A - Display substrate and method of manufacturing the same - Google Patents

Abstract

Disclosed are a display substrate and a method of manufacturing the same, which can prevent a malfunction. The first metal film formed on the substrate is patterned to form a gate electrode. Next, a gate insulating film, a first and a second silicon film are sequentially formed on the gate electrode, and a second metal film is formed on the second silicon film. Thereafter, the second metal film, the first and the second silicon film are patterned to form a source / drain electrode, an ohmic contact layer, and an active layer on the gate electrode. The second silicon film formed between the source electrode and the drain electrode is removed to form a plurality of channels, thereby completing a plurality of resistor transistors connected in series. Therefore, the malfunction of the gate driving circuit can be prevented and the reliability of the display substrate can be improved.

Description

DISPLAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME}

1 is a plan view of a display device according to an exemplary embodiment of the present invention.

FIG. 2 is a block diagram of the gate driving circuit shown in FIG. 1.

FIG. 3 is a circuit diagram of the n-th stage shown in FIG. 2.

4A through 4H are cross-sectional views illustrating a manufacturing process of the first display substrate illustrated in FIG. 1.

5A-5C are top views of FIGS. 4C, 4F, and 4H.

* Description of the symbols for the main parts of the drawings *

100: first display substrate 101: first substrate

102: first metal film 103: first photoresist

104: gate insulating film 105: first amorphous silicon film

106: second amorphous silicon film 107: second metal film

108: second photoresist 200: second display substrate

300: display panel 350: gate driving circuit

370: data driving chip 400: flexible circuit board

M1: first mask M2: second mask

The present invention relates to a display substrate and a method for manufacturing the same, and more particularly, to a display substrate and a method for manufacturing the same that can improve the reliability.

In general, a display device includes a display panel, a gate driving circuit for outputting a gate driving signal for driving the display panel, and a source driving circuit for outputting an image signal to the display panel. The gate driving circuit and the source driving circuit may be mounted on the display panel in a chip form, and the gate driving circuit may be directly formed on the display panel.

In the structure in which the gate driving circuit is formed on the display panel, the gate driving circuit is composed of one shift resist having a plurality of stages connected to each other.

Each stage of the shift resist has a configuration in which a plurality of transistors and capacitors are organically coupled. Among many transistors there are resistor transistors that are used as resistors to control the output of the shift register. However, as the mobility of the resistor transistors increases at high temperatures, the resistor transistors do not function properly. Therefore, the gate driving circuit malfunctions at a high temperature, and as a result, the reliability of the display device is degraded.

Accordingly, an object of the present invention is to provide a display substrate for preventing a malfunction of the gate driving circuit.                         

Further, another object of the present invention is to provide a method applied to manufacturing the display substrate described above.

A display substrate according to an aspect of the present invention includes a display area in which a pixel portion displaying an image in response to a driving signal is formed, and a peripheral area in which a driving circuit providing the driving signal to the display portion is formed. The driving circuit includes a driving unit for outputting the driving signal and a resistor unit for controlling the operation of the driving unit.

The forming of the resistor unit in the peripheral region may include forming a first metal layer on a substrate, patterning the first metal layer to form a gate electrode in the peripheral region, a gate insulating layer on the gate electrode, and Sequentially forming a first and a second silicon film, forming a second metal film on the second silicon film, and patterning the second metal film, the first and the second silicon film, and forming a plurality of silicon films on the gate electrode. A plurality of resistors connected in series by forming a source / drain electrode, an ohmic contact layer and an active layer, and removing the second silicon film formed between the plurality of source electrodes and the plurality of drain electrodes to form a plurality of channels. Forming the resistor section made of a transistor.

According to another aspect of the present invention, a display substrate includes a display unit for displaying an image in response to a drive signal, and a driver unit configured to provide a plurality of stages to provide the drive signal to the display unit.

Each stage may include a pull-up unit for converting an output signal to a first clock, a pull-down unit for discharging the output signal to a ground voltage in response to an output signal of one of the following stages, and one of previous stages A pull-up driving unit which turns on the pull-up unit in response to an output signal of a pull-up unit, which turns off the pull-up unit in response to an output signal of one of the following stages, a holding unit which holds the output signal in the ground voltage state, and a series A first room comprising a plurality of resistor transistors connected to the resistor unit for delaying and outputting the first clock for a predetermined time, and a first room for discharging the voltage output from the resistor unit in response to a second clock that is out of phase with the first clock. It consists of all, it comprises a switching unit for switching on / off of the holding unit.

According to the display substrate and the manufacturing method thereof, the resistor unit of the driving circuit is formed of a plurality of resistor transistors connected in series, thereby preventing malfunction of the driving circuit even at high temperatures, thereby ensuring reliability of the display substrate.

Hereinafter, with reference to the accompanying drawings, it will be described in detail a preferred embodiment of the present invention.

1 is a plan view of a display device according to an exemplary embodiment of the present invention, and FIG. 2 is a block diagram of the gate driving circuit illustrated in FIG. 1.

Referring to FIG. 1, a display device 500 according to an exemplary embodiment of the present invention may include a first display substrate 100, a second display substrate 200 facing the first display substrate 100, and the first display substrate 500. And a display panel 300 formed of a liquid crystal layer (not shown) interposed between the display substrate 100 and the second display substrate 200.

The display panel 300 includes a display area DA displaying an image and first and second peripheral areas SA1 and SA2 adjacent to the display area DA.

In the display area DA, a plurality of gate lines GL1 to GLn extending in a first direction D1 and a second direction D2 perpendicular to the first direction D1 extend to the plurality of gate lines. A plurality of data lines DL1 to DLm that are insulated from and intersect the GL1 to GLn are provided to define a pixel area in a matrix form.

Each pixel area includes a pixel including a pixel thin film transistor TFT and a liquid crystal capacitor Clc connected to the pixel thin film transistor TFT. In the pixel thin film transistor 110, a gate electrode is connected to a corresponding gate line, a source electrode is connected to a corresponding data line, and a drain electrode is coupled to the liquid crystal capacitor Clc.

The first peripheral area SA1 is an area adjacent to one end of the plurality of gate lines GL1 to GLn, and gate driving is performed on the plurality of gate lines GL1 to GLn in the first peripheral area SA1. A gate driving circuit 350 for sequentially outputting signals is formed. The second peripheral area SA2 is an area adjacent to one end of the plurality of data lines DL1 to DLm, and the second peripheral area SA2 is an image signal corresponding to the plurality of data lines DL1 to DLm. A data driving chip 370 for outputting the same is mounted.

On one side of the second peripheral area SA2, an external device (not shown) for driving the liquid crystal display panel 300 and a flexible printed circuit board for electrically connecting the liquid crystal display panel 300 to each other. Below, the FPC 400 is further attached. The FPC 400 is electrically connected to the data driving chip 370. The gate driving circuit is connected to the FPC 400 or the FPC 400 directly through the data driving chip 370.

As shown in FIG. 2, the gate driving circuit 350 includes one shift register including a plurality of stages connected dependently to each other. The plurality of stages SRC1 to SRCn + 1 may include a first clock terminal CK1, a second clock terminal CK2, a first input terminal IN1, a second input terminal IN2, an output terminal OUT, and It includes a ground voltage terminal (VSS).

A first clock CKV is provided to the first clock terminal CK1 of odd-numbered stages SRC1, SRC3, and SRCn + 1 of the plurality of stages, and the first clock of even-numbered stages SRC2 and SRCn is provided. The terminal CK2 is provided with a second clock CKVB having a phase inverted with the first clock CKV. Meanwhile, the second clock CKVB is provided to the second clock terminal CK2 of the odd-numbered stages SRC1, SRC3, and SRCn + 1, and the second clock of the even-numbered stages SRC2 and SRCn is provided. Terminal CK2 is provided with the first clock CKV.

The output terminal OUT of the odd-numbered stages SRC1, SRC3, and SRCn + 1 outputs the first clock CKV, and the output terminal OUT of the even-numbered stages SRC2 and SRCn is the second. Output the clock CKVB. The output terminals OUT of the n stages SRC1 to SRCn are electrically connected to corresponding gate lines of the n gate lines GL1 to GLn provided in the display area DA (shown in FIG. 1). . Accordingly, the shift register sequentially drives the n gate lines GL1 to GLn.

The signal output from the output terminal OUT of the previous stage is applied to the first input terminal IN1, and the signal output from the output terminal OUT of the next stage is applied to the second input terminal IN2. do.

In this case, the first input terminal IN1 of the first driving stage SRC1 is provided with a start signal STV, which is not an output signal of the previous stage. In addition, the second input terminal IN2 of the n + 1st stage SRCn + 1 provided to provide an output signal to the second input terminal IN2 of the nth stage SRCn is used instead of the output signal of the next stage. The start signal STV is provided.

FIG. 3 is a circuit diagram of the n-th stage shown in FIG. 2. However, the n-th stage SRCn shown in FIG. 3 has the same configuration as the remaining stages. Therefore, by describing the configuration of the n-th stage SRCn with reference to FIG. 3, the description of the remaining stages is omitted.

Referring to FIG. 3, the n-th stage SRCn includes a pull-up unit 351 for pulling up an output signal output from the output terminal OUTn to the first clock CKV, and an n + 1th stage SRCn + 1. And a pull-down unit 352 which pulls down the output signal pulled up in response to the output signal of FIG. 2.

The pull-up unit 351 has a first transistor NT1 having a gate electrode connected to the first node N1, a drain electrode connected to the first clock terminal CK1, and a source electrode connected to the output terminal OUTn. ). The pull-down unit 352 includes a second transistor NT2 having a gate electrode connected to a second input terminal IN2, a drain electrode connected to the output terminal OUTn, and a ground voltage VSS provided to a source electrode. ).

The n-th stage SRCn turns on the pull-up unit 351 in response to the output signal OUTn-1 (shown in FIG. 2) of the n-th stage SRCn-1 (shown in FIG. 2). The apparatus further includes a pull-up driving unit which turns off the pull-up unit 351 in response to an output signal of the n + 1th stage SRCn + 1. The pull-up driving unit includes a buffer unit 353, a first charging unit 354, and a first discharge unit 355.

The buffer unit 353 includes a third transistor NT3 having a gate and a drain electrode commonly connected to the first input terminal IN1, and a source electrode connected to the first node N1. The first charging unit 354 includes a first capacitor C1 having a first electrode connected to the first node N1 and a second electrode connected to the second node N2. In the first discharge unit 355, a gate electrode is connected to the second input terminal IN2, a drain electrode is connected to the first node N1, and the ground voltage VSS is provided to a source electrode. A fourth transistor NT4 is included.

When the third transistor NT3 is turned on in response to an output signal of the n−1 th stage SRCn-1 (shown in FIG. 2), the n−1 th stage SRCn−1 (shown in FIG. 2) The output signal of is charged in the first capacitor C1. When the first capacitor C1 is charged with a charge higher than or equal to the threshold voltage of the first transistor NT1, the first transistor NT1 is bootstraped and provided to the first clock terminal CK1. One clock (CKV, shown in FIG. 1) is output to the output terminal OUTn. Subsequently, when the fourth transistor NT4 is turned on in response to the output signal of the n + 1 th stage SRCn + 1, the charge charged in the first capacitor C1 is discharged to the ground voltage VSS.

The n-th stage SRCn further includes a holding part 356 for holding the output signal OUTn at the ground voltage VSS and a switching part 357 for controlling driving of the holding part 356. do.

The holding part 356 includes fifth and sixth transistors NT5 and NT6. The gate electrode of the fifth transistor NT5 is connected to the third node N3, the drain electrode is connected to the second node N2, and the source electrode is provided with the ground voltage VSS. The gate electrode of the sixth transistor NT6 is connected to the second clock terminal CK2, the drain electrode is connected to the second node N2, and the source electrode is provided with the ground voltage VSS.

The switching unit 357 includes a resistor unit and a second discharge unit. The resistor unit includes first, second and third resistor transistors NT7-1, NT7-2, and NT7-3 connected in series. Gate electrodes of the first to third resistance transistors NT7-1, NT7-2, and NT7-3 are connected to the first clock terminal CK1 and drain electrodes of the first resistance transistor NT7-1. Is connected to the first clock terminal CK1 and a source electrode of the third resistance transistor NT7-3 is connected to the third node N3.

In addition, the resistor unit includes an eighth transistor NT8, second and third capacitors C2 and C3. A drain electrode of the eighth transistor NT8 is connected to the first clock terminal CK1, a gate electrode is connected to the first clock terminal CK1 through the second capacitor C2, and a source electrode is It is connected to the third node N33. The third capacitor C3 is connected between the gate electrode and the source electrode of the eighth transistor NT8.                     

Meanwhile, the second discharge part includes ninth and tenth transistors NT9 and NT10. A gate electrode of the ninth transistor NT9 is connected to the second node N2, a drain electrode is connected to a source electrode of the third resistance transistor NT7-3, and a source electrode VSS is connected to the source electrode. ) Is provided. The gate electrode of the tenth transistor NT10 is connected to the second node, the drain electrode is connected to the third node N3, and the source electrode is provided with the ground voltage VSS.

The first to third resistance transistors NT7-1 to NT7-3 and the eighth transistor NT8 are turned on by the first clock CKV provided to the first clock terminal CK1. At this time, when the first clock CKV is output to the output terminal OUTn, the potential of the second node N2 rises to a high state. As the potential of the second node N2 is increased, the ninth and tenth transistors NT7 are turned on, and the first to third resistance transistors NT7-1 to NT7-3 and the eighth transistor are turned on. The voltage output from NT8 is discharged to the ground voltage VSS through the ninth and tenth transistors NT9 and NT10, respectively. Therefore, the potential of the third node N3 is kept low, and the fifth transistor NT5 of the holding part 356 is turned off.

Thereafter, when the output signal of the output terminal OUTn is discharged to the ground voltage VSS by the output signal of the n + 1th stage SRCn + 1 (shown in FIG. 2), the second node N2. The potential of is gradually lowered to the low state. Accordingly, the ninth and tenth transistors NT9 and NT10 are turned off and are turned off from the first to third resistor transistors NT7-1 to NT7-3 and the eighth transistors NT7 and NT8. The potential of the third node N3 gradually increases due to the output voltage. As the potential of the third node N3 rises, the fifth transistor NT5 is turned on. The potential of the second node N2 is rapidly lowered to the ground voltage VSS by the turned-on fifth transistor NT5.

In this state, when the sixth transistor NT6 of the holding part 356 is turned on by the second clock CKVB provided to the second clock terminal CK2, the second node N2 is turned on. ) Is surely discharged to the ground voltage VSS. That is, the fifth and sixth transistors NT5 and NT6 hold the potential of the second node N2 in the ground voltage VSS state.

As described above, the first to third resistance transistors NT7-1 to NT7-3 play a role of determining a turn-on time of the fifth transistor NT5. Therefore, even when the mobility of the first to third resistance transistors NT7-1 to NT7-3 is high in a high temperature state, the first to third resistance transistors NT7-1 to NT7-3 are connected in series. , The total channel resistance of the resistor increases. That is, the total sum of the channel lengths of the first to third resistance transistors NT7-1 to NT7-3 is maintained at 15 μm or more. As a result, reliability of the gate driving circuit 350 may be secured even at a high temperature, thereby preventing malfunction of the gate driving circuit 350.

The n-th stage SRCn further includes a ripple prevention unit 358 and a reset unit 359.

The ripple prevention unit 358 includes eleventh and twelfth transistors NT11 and NT12. The gate electrode of the eleventh transistor NT12 is connected to the first clock terminal CK1, the drain electrode is connected to the source electrode of the twelfth transistor NT12, and the source electrode is connected to the second node N2. do. The gate electrode of the twelfth transistor NT12 is connected to the second clock terminal CK2, the drain electrode is connected to the first input terminal IN2, and the source electrode is connected to the drain electrode of the eleventh transistor NT11. Connected.

When the output terminal OUTn starts to be discharged while the eleventh transistor NT11 is turned on by the first clock CKV provided to the first clock terminal CK1, the first node N1 is discharged. Is applied to the discharge terminal through the output terminal OUTn via the eleventh transistor NT11. In addition, when the twelfth transistor NT12 is turned on by the second clock CKVB provided to the second clock terminal CK2, the potential applied to the first node N2 is set to the twelfth transistor NT12. Through the first input terminal IN1 is discharged through.

Therefore, the ripple prevention unit 358 may discharge the eleventh transistor NT11 when the first clock CK1 rises to a high state after the output terminal OUTn is discharged to the ground voltage VSS. The potential of the first node N1 is maintained at the ground voltage VSS. In addition, when the first clock CK1 falls to a low state, the potential of the first node N1 is maintained at the ground voltage VSS through the twelfth transistor NT12. As such, even after the output signal is switched to the low state, the potential of the first node N1 is maintained at the ground voltage VSS state, thereby changing the state of the first and second clocks CK1 and CK2. Ripple of the output signal can be prevented.                     

The reset part 359 includes a thirteenth transistor NT13 having a gate electrode connected to the rear terminal RE, a drain electrode connected to the first node N1, and the ground voltage VSS provided to a source electrode. It includes. When the output signal of the n + 1 th stage SRCn + 1 is provided to the relet terminal RE, the thirteenth transistor NT13 is turned on to supply the potential of the first node N1 to the ground voltage VSS. To discharge). Therefore, the output signal of the nth stage SRCn is more reliably discharged to the ground voltage VSS by the output signal of the n + 1st stage SECn + 1.

4A to 4H are cross-sectional views illustrating a manufacturing process of the first display substrate illustrated in FIG. 1, and FIGS. 5A to 5C are plan views of FIGS. 4C, 4F, and 4H.

Referring to FIG. 4A, a method of sputtering a first metal film 102 made of aluminum (Al), chromium (Cr), or molybdenum tungsten (MoW) on a first substrate 101 made of an insulating material such as glass or ceramic. By deposition.

4B, a first photoresist 103 is formed on the first metal film 102. The first mask M1 is disposed on the first photoresist 103, and an exposure process is performed. The first photoresist 103 is exposed to correspond to the open area of the first mask M1.

Thereafter, when the exposed first photoresist 103 is removed, only the first photoresist 103 that is not exposed remains on the first metal film 102. Next, the first metal layer 102 which is not covered by the first photoresist 103 is etched through an etchant. Thereafter, the first metal film 102 that is not covered by the first photoresist 103 and the first photoresist 103 covering the first metal film 102 are removed.

4C and 5A, the first gate electrode GE1 is formed in the display area DA of the first substrate 101, and the second gate electrode is formed in the first peripheral area SA1. GE2 is formed.

Referring to FIG. 4D, silicon nitride is deposited on the first substrate 101 on which the first and second gate electrodes GE1 and GE2 are formed by plasma-enhanced chemical vapor deposition (PECVD). The gate insulating film 104 is formed. Thereafter, a first amorphous silicon film 105 is deposited on the gate insulating film 104 by a plasma chemical vapor deposition method, and a second amorphous silicon film 106 doped with n + is deposited on the gate insulating film 104 by a plasma chemical vapor deposition method. do. In this case, the first amorphous silicon film 105 and the second amorphous silicon film 106 are deposited in-situ in the same chamber of the plasma chemical vapor deposition facility.

Referring to FIG. 4E, a second metal film 107 made of chromium (Cr) is deposited on the second amorphous silicon film 106 by a sputtering method.

4F and 5B, a second photoresist 108 is formed on the second metal film 107. The second mask M2 is disposed on the second photoresist 108, and an exposure process is performed. Then, the second photoresist 108 is exposed to correspond to the area where the second mask M2 is opened.

First, second, third, and fourth slits SL1, SL2, SL3, and SL4 are formed in the second mask M2. The first slit SL1 is formed to correspond to the central portion of the first gate electrode GE1, and the second to fourth slits SL2 to SL4 are formed by dividing the second gate electrode GE2 into three equal parts. Are formed on each.

Accordingly, the second photoresist 108 is completely exposed in correspondence to the portion where the second mask M2 is completely opened, but corresponding to the portion in which the first to fourth slits SL1 to SL4 are formed. The second photoresist 108 is partially exposed.

Thereafter, developing the exposed second photoresist 108 completely removes the completely exposed second photoresist 108, as shown in FIG. 4G, but partially exposes the second photoresist. The resist 108 remains partially. Next, the second metal film 107 is etched through the etching solution. Accordingly, the second metal film 102, the first and second amorphous silicon films 105 and 106, which are not covered by the first photoresist 103, are completely removed and the first photoresist ( Corresponding to the region where 108 remains partially, only the second amorphous silicon film 106 is removed.

Subsequently, when the first photoresist 103 covering the second metal film 102 is removed, the display area DA of the first substrate 101 is removed as shown in FIGS. 4H and 5C. First source / drain electrodes SE1 and DE1 are formed, and second source / drain electrodes SE2 and DE2, and first and second common source / drain electrodes CE1 and CE2 are disposed in the first peripheral area SA1. Is formed. In addition, a first ohmic contact layer OC1 and a first active layer A1 are formed between the first gate electrode GE1 and the first source / drain electrodes SE1 and DE1. A plurality of second ohmic contact layers OC2 and a second active layer A2 are formed on the second gate electrode GE2.

Accordingly, the pixel thin film transistor TFT is completed in the display area DA of the first substrate 101, and used in the gate driving circuit 350 (shown in FIG. 1) in the first peripheral area SA1. The first to third resistance transistors NT7-1 to NT7-3 (shown in FIG. 3) are completed.

As shown in FIG. 5C, a first channel C1 is formed between the first source electrode SE1 and the first drain electrode DE1.

Meanwhile, a second channel C2 is formed between the second source electrode SE2 and the first common source / drain electrode CE1, and between the first and second common source / drain electrodes CE1. A third channel C3 is formed in CE2, and a fourth channel C4 is formed between the second common source / drain electrode CE2 and the second drain electrode DE2. Each of the second to fourth channels C2 to C4 has the same channel length L and channel width W. Therefore, the sum of the channel lengths of the first to third resistance transistors NT7-1 to NT7-3 is 3L. As an example of the present invention, the 3L is 15 μm or more.

As such, when the sum 3L of the channel lengths of the first to third resistance transistors NT7-1 to NT7-3 is increased to 15 μm or more, reliability of the gate driving circuit 350 is secured even at a high temperature. Malfunction of the gate driving circuit 350 can be prevented.

Although not shown in FIGS. 4A to 4H, the passivation layer and the passivation layer may be disposed on the first display substrate 100 to cover the pixel thin film transistor TFT and the first to third resistance transistors NT7-1 to NT7-3. The pixel electrode formed on the substrate may be provided. A contact hole exposing the first drain electrode DE1 of the pixel thin film transistor TFT is formed in the passivation layer. Therefore, a third mask (not shown) for patterning the passivation layer is further used to manufacture the first display substrate 100.

In addition, the pixel electrode formed on the passivation layer is patterned in units of pixels. Therefore, a fourth mask (not shown) for patterning the pixel electrode is further used to manufacture the first display substrate 100. As a result, a total of four masks are used to manufacture the first display substrate 100.

Although not shown in the drawing, the channel length of each of the resistor transistors constituting the resistor unit may be increased to reduce the number of series connected resistor transistors. That is, in addition to increasing the number of resistance transistors having the same channel length in order to obtain a desired channel length, the channel length of each resistance transistor is increased. As one method of increasing the channel length of each of the resistor transistors, a method of extending a slit region in the second mask M2 may be used.

According to such a display substrate and a method of manufacturing the same, since the resistance portion of the driving circuit is formed of a plurality of resistance transistors connected in series, malfunction of the driving circuit can be prevented even at a high temperature, and as a result, the reliability of the display substrate can be ensured.

In addition, since the mask may be formed using a plurality of resistor transistors connected in series, an existing mask may be applied directly, thereby facilitating the manufacturing process of the display substrate.

Although described with reference to the above embodiments, those skilled in the art will understand that various modifications and changes can be made without departing from the spirit and scope of the invention as set forth in the claims below. Could be.

Claims (8)

A method of manufacturing a display substrate comprising a display area in which a pixel portion displaying an image in response to a drive signal is formed, and a peripheral region in which a driving circuit providing the drive signal to the display portion is formed. The driving circuit includes a driving unit for outputting the driving signal and a resistor unit for controlling the operation of the driving unit, Forming the resistor in the peripheral area, Forming a first metal film on the substrate; Patterning the first metal layer to form a gate electrode in the peripheral region; Sequentially forming a gate insulating film, first and second silicon films on the gate electrode; Forming a second metal film on the second silicon film; And Patterning the second metal layer, the first and the second silicon layers to form a plurality of source / drain electrodes, an ohmic contact layer, and an active layer on the gate electrode, and the plurality of source electrodes and the plurality of drain electrodes And forming the plurality of channels by removing the second silicon layer formed therebetween to form the plurality of channels, thereby forming the resistor unit formed of a plurality of series of resistor transistors connected in series. The method of claim 1, wherein the plurality of resistance transistors are formed using a first mask for patterning the first metal film and a second mask for patterning the second metal film, the first and the second silicon film. Method of manufacturing display substrate. The method of claim 2, wherein a slit is formed in the second mask in correspondence between the plurality of source electrodes and the plurality of drain electrodes. The method of claim 1, wherein the sum of the total lengths of the plurality of channels is 15 μm or more. A display substrate comprising a display unit for displaying an image in response to a drive signal and a driver unit configured to provide a plurality of stages to provide the drive signal to the display unit. Each stage, A pull-up unit for converting an output signal to a first clock; A pull-down unit configured to discharge the output signal to a ground voltage in response to an output signal of one of next stages; A pull-up driving unit turning on the pull-up unit in response to an output signal of one of previous stages and turning off the pull-up unit in response to an output signal of one of the next stages; A holding unit holding the output signal in the ground voltage state; And A first resistor configured to include a plurality of resistor transistors connected in series to discharge the first clock for a predetermined time and to discharge the voltage output from the resistor in response to a second clock that is out of phase with the first clock; And a switching unit for switching on / off of the holding unit. The display substrate of claim 5, wherein a sum of channel lengths of each of the plurality of resistance transistors connected in series is 15 μm or more. The display substrate of claim 5, wherein the holding part comprises a holding transistor configured to hold the output signal to the ground voltage state in response to the voltage output from the resistor part. The method of claim 5, wherein the pull-up driving unit, A buffer unit which receives an output signal of one of the previous stages; A charging unit for charging an output signal of one of the previous stages passing through the buffer unit; And And a second discharge unit configured to discharge the charge charged in the second charging unit in response to an output signal of one of the next stages.

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