KR101441384B1 - Liquid crystal display device and method for fabricating the same - Google Patents

Abstract

The present invention relates to a liquid crystal display device and a method of manufacturing the same, and a liquid crystal display device according to the present invention includes a gate conductive layer formed on an insulating substrate, a data conductive layer formed to overlap the gate conductive layer, And a bridge electrode connected to the data conductive layer overlapped with the gate conductive layer via the contact hole.

Bridge electrode, jumping portion

Description

[0001] The present invention relates to a liquid crystal display device and a manufacturing method thereof,

The present invention relates to a liquid crystal display and a method of manufacturing the same.

A liquid crystal display displays an image by adjusting the light transmittance of a liquid crystal having dielectric anisotropy using an electric field. A liquid crystal display device is formed by a color filter substrate on which a color filter array is formed and a thin film transistor substrate on which a thin film transistor array is formed. A plurality of pixel electrodes, to which data signals are individually supplied, are formed in a matrix form on the thin film transistor substrate. In the thin film transistor substrate, a thin film transistor for driving a plurality of pixel electrodes individually, a gate line for controlling the thin film transistor, and a data line for supplying a data signal to the thin film transistor are formed.

The thin film transistor substrate has a structure in which a plurality of conductive layers and an insulating layer are stacked. For example, the thin film transistor substrate may include a first conductive layer forming a gate line and a gate electrode of the thin film transistor, a second conductive layer forming a source electrode and a drain electrode of the data line and the thin film transistor, And the third conductive layer is stacked with the insulating layers interposed therebetween.

The thin film transistor substrate has a plurality of jumping portions for connecting the first and second conductive layers by using a bridge electrode formed of a third conductive layer.

FIG. 1 is a plan view schematically showing a jumping portion formed on a thin film transistor substrate. As shown in FIG. 1, the jumping portion 1 includes a first conductive layer 10 through at least two insulating films (not shown) And a second contact hole 13 that exposes the second conductive layer 12 through at least one insulating film (not shown) to expose the first and second conductive layers (not shown) 10, and 12 are connected to each other.

However, when the first conductive layer 10 and the second conductive layer 12 are spaced apart from each other by a predetermined distance, the area of the bridge electrode 14 connecting them increases, and thereby the resistance of the bridge electrode also increases There is a problem.

SUMMARY OF THE INVENTION It is an object of the present invention to solve the problems described above and to provide a method of manufacturing a liquid crystal display device capable of reducing a resistance of a third conductive layer by reducing an area of a third conductive layer connecting the first and second conductive layers .

According to an aspect of the present invention, there is provided a liquid crystal display device including a gate conductive layer formed on an insulating substrate, a data conductive layer formed to overlap the gate conductive layer, a contact hole exposing the data conductive layer, And a bridge electrode connected to the data conductive layer overlapped with the gate conductive layer via the contact hole.

Wherein the jumping portion including the bridge electrode connected to the data conductive layer overlapping the gate conductive layer is formed on a thin film transistor substrate including an image display portion composed of a plurality of pixel regions and a driving circuit for driving the image display portion, Wherein the image display section includes a pixel electrode formed in each of the pixel regions, a thin film transistor connected to the pixel electrode, a gate line for controlling the thin film transistor, and a data line for supplying data to the thin film transistor, Includes a gate driving circuit for driving the gate line.

According to another aspect of the present invention, there is provided a method of manufacturing a liquid crystal display device including forming a first conductive layer on an insulating substrate, forming a gate conductive layer using a first mask, Forming a first insulating film on the formed substrate, forming a contact hole exposing the gate conductive layer using a second mask as a diffraction exposure mask, and forming a second conductive layer on the substrate on which the contact hole is formed Forming a data conductive layer which overlaps with the gate conductive layer using a third mask, forming a second insulating film on a substrate on which the data conductive layer is formed, and forming a data conductive layer Forming a third conductive layer on a substrate on which a contact hole for exposing the data conductive layer is formed, And forming a conductive layer and a bridge electrode connecting.

Wherein the jumping portion including the bridge electrode connected to the data conductive layer overlapping the gate conductive layer is formed on a thin film transistor substrate including an image display portion composed of a plurality of pixel regions and a driving circuit for driving the image display portion, Wherein the image display section includes a pixel electrode formed in each of the pixel regions, a thin film transistor connected to the pixel electrode, a gate line for controlling the thin film transistor, and a data line for supplying data to the thin film transistor, Includes a gate driving circuit for driving the gate line.

Forming a gate electrode of the thin film transistor at the same time as the gate conductive layer forming step using the first mask; forming a source / drain electrode of the thin film transistor simultaneously with the data conductive layer forming step using the third mask; Forming a contact hole exposing the data conductive layer using the second mask, and forming a contact hole exposing a drain electrode of the thin film transistor at the same time.

The forming of the contact hole exposing the gate conductive layer using the second mask may include forming a photoresist pattern having the first and second patterns formed on the first insulating layer using the second mask, And forming a contact hole exposing the gate conductive layer by etching the first pattern of the photoresist pattern with an etching mask.

Wherein forming the contact hole exposing the data conductive layer using the second mask and simultaneously exposing the drain electrode of the thin film transistor includes forming a contact hole exposing the drain electrode of the thin film transistor using the second mask, Forming a photoresist pattern in which third and fourth patterns having the same shape as the first and second patterns are formed, removing the fourth pattern of the photoresist pattern by ashing to expose the second insulating film, Forming a contact hole exposing a contact hole and a drain electrode exposing the data conductive layer by etching the exposed photoresist pattern with an etching mask, respectively.

In the method of manufacturing a liquid crystal display device according to the present invention as described above, the third conductive layer is formed to overlap the first conductive layer and the second conductive layer and then connected to the second conductive layer, The resistance of the third conductive layer can be reduced.

Embodiments of a method of manufacturing a liquid crystal display device according to the present invention having the above-described features will now be described in detail with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a plan view schematically showing a liquid crystal display device according to an embodiment of the present invention.

2 includes an image display unit 3, a gate driving IC (Integrated Circuit) 2 for sequentially driving the gate lines GL1 to GLm of the image display unit 3, (1) for supplying data to the data lines (DL1 to DLn) of the data driver (3).

In the image display unit 3, gate lines and data lines are formed in an intersecting structure, and thin film transistors (hereinafter referred to as TFTs) and pixel electrodes are provided in a pixel region defined by the intersection structure.

The thin film transistor TFT supplies a data signal from one of the data lines to the pixel electrode in response to a scan signal from one of the gate lines. The pixel electrode forms an electric field together with the common electrode of the color filter substrate according to the supplied data signal, thereby controlling the liquid crystal in pixel units to display an image.

The gate drive IC 2 is composed of a plurality of stages including shift registers for driving the respective gate lines, and sequentially drives the gate lines in response to the gate start pulse.

The data driving IC 1 includes a shift register and a latch. The data driving IC 1 shifts data bits in response to a data shift clock and simultaneously supplies data for one line to data lines in response to a data output enable signal.

When a gate start pulse is supplied to the gate driving ICs 2, the gate driving IC sequentially supplies gate driving pulses to the m gate lines so that m gate lines are sequentially driven. Then, the thin film transistors (TFT) are sequentially driven by one gate line to sequentially supply the data signals to the pixels of one gate line.

The gate driving IC shown in FIG. 2 includes a plurality of shift registers, and FIG. 3 is a detailed circuit diagram showing one of the shift registers.

The shift register SR1 shown in FIG. 3 includes a first thin film transistor T1 as a pull-up transistor for outputting a clock CPV to the first gate line GL1 under the control of a Q node, And a second thin film transistor T2 which is a pull-down transistor for outputting a low potential voltage VSS to the first gate line GL1 by means of the second to seventh thin film transistors T2, And a control section composed of thin film transistors T3 to T7. The first to seventh thin film transistors T1 to T7 are formed in N type together with the thin film transistor (TFT) of the image display section 16 although they are formed as N type or P type.

The third thin film transistor T3 causes the high potential voltage VDD to be precharged to the Q node in response to the start pulse STV. The precharged Q node is bootstrapped by the coupling action of the capacitor C responsive to the clock CPV so that a high voltage of the clock CPV is applied to the first gate line GL1. Then, the fourth thin film transistor T4 responds to the scan signal of the second gate line GL2, and the fifth thin film transistor T5 discharges the Q node to the low potential voltage VSS in response to the QB node. The sixth thin film transistor T6 is connected in a forward diode type to a high potential supply line VDD to allow the QB node to be charged with the high potential voltage VDD and the seventh thin film transistor T7 responds to the Q node And discharges the QB node to the low potential voltage VSS. When the Q node is discharged to the low voltage through the fourth and fifth thin film transistors T4 and T5, the seventh thin film transistor T7 is turned off to charge the high potential voltage VDD to the QB node.

As a result, the second thin film transistor T2 is turned on and the scan signal of the first gate line GL1 is discharged to the low potential VSS. The second thin film transistor T2 maintains the turn-on state until the start pulse STV is supplied to the third thin film transistor T3 so that the first gate line GL1 maintains the low potential voltage VSS do.

The liquid crystal display according to the present invention incorporates a gate driving IC composed of a plurality of thin film transistors in a thin film transistor substrate of a liquid crystal panel using amorphous silicon. Since the gate driving IC is formed by a plurality of mask processes together with the image display portion of the thin film transistor substrate, at least three conductive layers are stacked with the insulating films interposed therebetween. In the gate driving IC, there are many jumping parts such as the Q node where different conductive layers are connected via the bridge electrode. That is, in the gate driving IC, a gate conductive layer sandwiching the gate insulating film therebetween, and a jumping portion in which the data conductive layer is connected to the protective film via the bridge electrode formed of the transparent conductive layer.

FIG. 4 is a plan view schematically showing a jumper according to the present invention, and FIG. 5I is a part of a process flowchart showing a method of forming a jumper and a method of forming a thin film transistor.

The gate driving IC shown in Figs. 4 and 5i includes a jumping portion 120 connected to a plurality of thin film transistors, and the jumping portion 120 includes a gate conductive layer 130, which is a first conductive layer protruding from a plurality of thin film transistors Layer 100a, a data conductive layer 106d as a second conductive layer, and a bridge electrode 109b as a third conductive layer. Here, the jumping unit 120 is not limited to being connected to a plurality of thin film transistors, but is applied to a structure in which a gate conductive layer and a data conductive layer are connected via a bridge electrode on a thin film transistor substrate.

The thin film transistor includes a gate electrode 100b and a semiconductor layer 105d overlapped with the gate electrode 100b with the gate insulating film 132b therebetween and a source electrode overlapped with the semiconductor layer 105d and spaced apart from each other at regular intervals, And drain electrodes 106b and 106c. This thin film transistor corresponds to any one of the plurality of thin film transistors T1 to T7 shown in FIG.

The jumping portion 120 includes a gate conductive layer 100a protruding from the thin film transistor and a data conductive layer 106d protruding from the thin film transistor and simultaneously overlapping on the gate conductive layer 100a, A contact hole 140 exposing the data conductive layer 106d overlapped with the gate conductive layer 100a and a data conductive layer 106d overlapped with the gate conductive layer 100a via the contact hole 140 And a bridge electrode 109b. The gate conductive layer 100a is formed on the insulating substrate 130 and the gate insulating film 132b is formed thereon and the data conductive layer 106d is formed on the gate insulating film 132b and the protective film 108 is formed thereon .

The data conductive layer 106d overlaps the gate conductive layer 100a exposed by patterning the gate insulating layer 132b and the semiconductor layer 105c and is electrically connected to the bridge electrode 109b The data conductive layer and the gate conductive layer are overlapped with each other so that the area of the connecting bridge electrode connecting them can be reduced and the resistance of the bridge electrode can be reduced.

The method of forming the jumper 120 having the configurations of FIGS. 4 and 5i will be described in conjunction with a method of forming a thin film transistor.

5A to 5I are process flow diagrams illustrating a method A of forming a thin film transistor and a method B of forming a jumper according to the present invention.

As shown in Fig. 5A, a gate electrode 100b of a thin film transistor and a gate conductive layer 100a of a jumping portion are formed on an insulating substrate 130. Fig. The gate electrode 100b and the gate conductive layer 100a are formed by forming a first conductive layer on the insulating substrate 130 through a deposition method such as a sputtering method and then patterning the conductive layer using a photolithography process using a first mask.

5B, a gate insulating layer 132a and a semiconductor layer 105a, which are first insulating layers, are sequentially formed on the insulating substrate 130 on which the gate electrode 100b and the gate conductive layer 100a are formed And a first photoresist pattern 90 is formed on the semiconductor layer 105a. The first photoresist pattern 90 is formed by forming a photoresist pattern on the insulating substrate 130 on which the semiconductor layer 105a is formed and then patterning the photoresist pattern by photolithography using a second mask. The first photoresist pattern 90 is formed with a first pattern 90a for forming a first contact hole for exposing a drain electrode to be formed later and a second pattern 90b for forming a second contact hole for exposing the gate conductive layer. (90b) are formed. The second mask for forming the first photoresist pattern 90 may include a transmissive region through which light is entirely passed, a diffraction exposure region including a plurality of slits that transmit a portion of the light and block a portion thereof, Region is used as the diffraction exposure mask. At this time, the diffraction exposure region corresponds to the region in which the first pattern 90a is defined, and the transmission region corresponds to the region in which the second pattern 90b is defined. Therefore, the photoresist thickness of the first pattern 90a corresponding to the diffraction exposure region is formed to be lower than the photoresist thickness of the second pattern 90b corresponding to the blocking region.

5C, a second contact hole 104b exposing the gate conductive layer 100a is formed by using a first photoresist pattern 90 formed on the insulating substrate 130. Next, as shown in FIG.

The second contact hole 104b is formed by etching the semiconductor layer 105a and the gate insulating film 132a using the first photoresist pattern 90 as an etching mask. At this time, the gate insulating layer 132b and the semiconductor layer 105b corresponding to the first pattern 90a of the first photoresist pattern 90 are not etched due to the remaining photoresist pattern, and the second pattern 90b, The gate insulating film 132a and the semiconductor layer 105a are etched due to the fact that the photoresist pattern does not remain.

5D, a second conductive layer 106a is formed on the insulating substrate 130, and a second photoresist pattern 91 is formed on the second conductive layer 106a.

The second photoresist pattern 91 is formed by forming a photoresist pattern on the insulating substrate 130 on which the second conductive layer 106a is formed, and then patterning the photoresist pattern by photolithography using a third mask. The third photoresist pattern 91 includes a third pattern 91a formed to define a channel region and a fourth pattern 91b corresponding to the second contact hole 104b and simultaneously formed to define source / Is formed. At this time, a diffraction exposure mask is also used as the third mask for forming the second photoresist pattern 91, and the diffraction exposure region corresponds to the third pattern 91a and the blocking region corresponds to the fourth pattern 91b Corresponding. Therefore, the thickness of the photoresist in the third pattern 91a corresponding to the diffraction exposure region is formed to be lower than the thickness of the photoresist in the fourth pattern 91b corresponding to the blocking region.

Next, as shown in FIG. 5E, the first and second semiconductor layer patterns 105c and 105d and the source / drain electrodes 106b and 106b are formed using the second photoresist pattern 91 formed on the insulating substrate 130 , 106c and a data conductive layer 106d are formed.

The first and second semiconductor layer patterns 105c and 105d, the source / drain electrodes 106b and 106c, and the data conductive layer 106d are formed through the following process.

The second conductive layer 106b and the patterned semiconductor layer 105b are etched using the second photoresist pattern 91 as an etching mask so that the first and second semiconductor layer patterns 105c and 105d and the source / A drain pattern and a data conductive layer 106d are formed. Then, the second photoresist pattern 91 is etched to remove a portion of the second photoresist pattern 91, and then the source / drain pattern is etched using the etching mask to form the source electrode 106b and the drain electrode 106c, . At this time, the photoresist of the third pattern 91a is completely removed so that the source / drain pattern is exposed to form a channel region in the ashing process in which a part of the second photoresist pattern is removed. The first semiconductor layer pattern 105c and the data conductive layer 106d are covered with the second contact hole 104b.

5F, a protective film 108 is formed on the entire surface of the insulating substrate 130, and a third photoresist pattern 91 having the same shape as the first photoresist pattern 91 is formed on the protective film 108, A photoresist pattern 92 is formed.

The third photoresist pattern 92 is formed by forming a photoresist pattern on the insulating substrate 130 on which the protective film 108 is formed, and then patterning the photoresist pattern by photolithography using the second mask. The third photoresist pattern 92 is formed with fifth and sixth patterns 92a and 92b which are the same as the first pattern 90a and the second pattern 90b of the first photoresist pattern 90. In other words, the fifth pattern 92a is a pattern for forming a first contact hole for exposing the drain electrode, and the sixth pattern 92b is a pattern for exposing the second contact hole 104b.

Next, as shown in FIG. 5G, a fourth photoresist pattern 93 is formed on the insulating substrate 130. The fourth photoresist pattern 93 is formed by ashing the fourth photoresist pattern 93 such that the protective film 108 of the region where the first contact hole and the data conductive layer 106d are formed is exposed, .

5H, a first contact hole 104a is formed by etching the protective film 108 exposed by the fourth photoresist pattern 93 of the insulating substrate 130 with an etching mask, Thereby exposing the data conductive layer 106d.

Next, as shown in FIG. 5I, a pixel electrode 109a and a bridge electrode 109b are formed in the first contact hole 104a and the exposed data conductive layer 106d of the insulating substrate 130, respectively . The pixel electrode 109a and the bridge electrode 109b are formed by forming a transparent conductive film on the first contact hole 104a of the insulating substrate 130 and the exposed data conductive layer 106d through a deposition method such as a sputtering method And then patterned by a photolithography process using a fourth mask.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Will be clear to those who have knowledge of.

Figure 1 is a plan view schematically illustrating a jumper according to the prior art;

2 is a plan view showing a liquid crystal display device according to the present invention.

3 is a detailed circuit diagram showing one of the shift registers among the plurality of shift registers built in the gate driving IC of FIG.

Figure 4 is a plan view schematically showing a jumper according to the present invention;

5A to 5I are flow charts showing a method of forming a jumper and a method of forming a thin film transistor according to the present invention.

Claims (7)

delete delete Forming a first conductive layer on an insulating substrate and forming a gate conductive layer using the first mask, Forming a first insulating film on a substrate on which the gate conductive layer is formed and forming a contact hole exposing the gate conductive layer using a second mask as a diffraction exposure mask; Forming a second conductive layer on the substrate on which the contact hole is formed, and forming a data conductive layer overlapping the gate conductive layer using a third mask; Forming a second insulating film on the substrate on which the data conductive layer is formed and forming a contact hole exposing the data conductive layer using the second mask, Forming a third conductive layer on a substrate on which the contact hole exposing the data conductive layer is formed, and forming a bridge electrode connected to the data conductive layer using a fourth mask, The step of forming the bridge electrode A pixel electrode is formed on the second insulating layer with the same material as the bridge electrode using the fourth mask together with the bridge electrode,  Wherein the jumping portion including the bridge electrode connected to the data conductive layer overlapping the gate conductive layer is formed on a thin film transistor substrate including an image display portion composed of a plurality of pixel regions and a driving circuit for driving the image display portion, Wherein the image display unit includes a pixel electrode formed in each of the pixel regions, a thin film transistor connected to the pixel electrode, a gate line for controlling the thin film transistor, and a data line for supplying data to the thin film transistor, And a gate driving circuit for driving the gate line, Forming a gate electrode of the thin film transistor simultaneously with the gate conductive layer forming step using the first mask; Forming a source / drain electrode of the thin film transistor simultaneously with the data conductive layer forming step using the third mask; Forming a contact hole exposing the data conductive layer using the second mask, and forming a contact hole exposing a drain electrode of the thin film transistor. delete delete 4. The method of claim 3, wherein forming the contact hole exposing the gate conductive layer using the second mask comprises: Forming a photoresist pattern having first and second patterns formed on the first insulating film by using the second mask; And forming a contact hole exposing the gate conductive layer by etching the first pattern of the photoresist pattern with an etching mask. The method of claim 3, wherein the step of forming the contact hole exposing the drain electrode of the thin film transistor simultaneously with the step of forming the contact hole exposing the data conductive layer using the second mask Forming a photoresist pattern having third and fourth patterns having the same shape as the first and second patterns formed on the second insulating film using a second mask; Removing the fourth pattern of the photoresist pattern to expose the second insulating film; Forming a contact hole exposing a contact hole and a drain electrode exposing the data conductive layer by etching the ashed photoresist pattern with an etch mask, respectively.

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