KR20060017173A - Method of manufacturing dielectric layer of semiconductor devices - Google Patents
Method of manufacturing dielectric layer of semiconductor devices Download PDFInfo
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- KR20060017173A KR20060017173A KR1020040065743A KR20040065743A KR20060017173A KR 20060017173 A KR20060017173 A KR 20060017173A KR 1020040065743 A KR1020040065743 A KR 1020040065743A KR 20040065743 A KR20040065743 A KR 20040065743A KR 20060017173 A KR20060017173 A KR 20060017173A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 37
- 238000004519 manufacturing process Methods 0.000 title description 3
- 238000000034 method Methods 0.000 claims abstract description 42
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 27
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 27
- 239000010703 silicon Substances 0.000 claims abstract description 27
- 239000005380 borophosphosilicate glass Substances 0.000 claims abstract description 15
- 238000009832 plasma treatment Methods 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 4
- 239000012535 impurity Substances 0.000 abstract description 15
- 230000007547 defect Effects 0.000 abstract description 11
- 229910052751 metal Inorganic materials 0.000 abstract description 8
- 239000002184 metal Substances 0.000 abstract description 8
- 239000011229 interlayer Substances 0.000 abstract description 4
- 238000009792 diffusion process Methods 0.000 abstract description 3
- 230000000694 effects Effects 0.000 abstract description 3
- 238000012545 processing Methods 0.000 abstract description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 6
- 229910052796 boron Inorganic materials 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 239000010410 layer Substances 0.000 description 6
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 239000007789 gas Substances 0.000 description 5
- 229910052698 phosphorus Inorganic materials 0.000 description 5
- 239000011574 phosphorus Substances 0.000 description 5
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 4
- 239000004020 conductor Substances 0.000 description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 239000005360 phosphosilicate glass Substances 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 239000002243 precursor Substances 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 239000005388 borosilicate glass Substances 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 229910020818 PH 3 Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 238000000280 densification Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910021645 metal ion Inorganic materials 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 229910001415 sodium ion Inorganic materials 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
- H01L21/0234—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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Abstract
본 발명은 반도체 소자의 절연막 형성 방법에 관한 것으로, 보다 자세하게는 층간절연막인 PMD막의 불순물에 기인한 PMD막의 상부, 하부에 존재하는 다른 막의 손상 및 콘택홀 공정시의 불량 발생을 억제할 수 있는 반도체 소자의 절연막 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming an insulating film of a semiconductor device, and more particularly, to a semiconductor capable of suppressing damage to other films existing on and under a PMD film due to impurities in a PMD film, which is an interlayer insulating film, and defects during contact hole processing. A method of forming an insulating film of a device.
본 발명의 상기목적은 게이트 전극, 소스/드레인 등을 포함한 소정의 구조물이 형성된 반도체 기판 상에 PMD 라이너막을 형성하는 단계; 상기 라이너 산화막 상에 제 1 실리콘 리치 산화막을 형성하는 단계; 상기 제 1 실리콘 리치 산화막 상에 PMD막을 형성하고 평탄화하는 단계; 및 상기 평탄화된 PMD막 상에 제 2 실리콘 리치 산화막을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 절연막 형성 방법에 의해 달성된다.The object of the present invention is to form a PMD liner film on a semiconductor substrate on which a predetermined structure including a gate electrode, a source / drain, etc. is formed; Forming a first silicon rich oxide film on the liner oxide film; Forming and planarizing a PMD film on the first silicon rich oxide film; And forming a second silicon rich oxide film on the planarized PMD film.
따라서, 본 발명의 반도체 소자의 절연막 형성 방법은 PMD막의 상부 및 하부에 실리콘 리치 산화막을 형성하고 콘택 금속 매립 전에 플라즈마 처리를 함으로써 PMD막의 불순물에 의해 야기될 수 있는 반도체 소자의 불량을 방지하여 수율을 향상시키고 소자의 전기적 특성 및 신뢰성을 향상시키는 효과가 있다.Therefore, the method for forming an insulating film of the semiconductor device of the present invention by forming a silicon rich oxide film on the upper and lower portions of the PMD film and performing a plasma treatment before filling the contact metal to prevent the defect of the semiconductor device that may be caused by impurities in the PMD film to improve the yield There is an effect to improve and improve the electrical characteristics and reliability of the device.
실리콘 리치 산화막(SRO), PMD, BPSG, 불순물 확산, 콘택홀, 플라즈마 처리Silicon Rich Oxide (SRO), PMD, BPSG, Impurity Diffusion, Contact Hole, Plasma Treatment
Description
도 1은 종래 기술에 의한 반도체 소자의 절연막 형성시 나타난 불량 사진.1 is a bad photograph when the insulating film formed of a semiconductor device according to the prior art.
도 2는 본 발명에 의한 반도체 소자의 절연막 형성 방법의 흐름도.2 is a flowchart of a method for forming an insulating film of a semiconductor device according to the present invention;
도 3 및 도 4는 본 발명에 의한 반도체 소자의 절연막 형성 공정의 단면도.3 and 4 are cross-sectional views of the insulating film forming process of the semiconductor device according to the present invention.
본 발명은 반도체 소자의 절연막 형성 방법에 관한 것으로, 보다 자세하게는 층간절연막인 PMD막의 불순물에 기인한 PMD막의 상부, 하부에 존재하는 다른 막의 손상 및 콘택홀 공정시의 불량 발생을 억제할 수 있는 반도체 소자의 절연막 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming an insulating film of a semiconductor device, and more particularly, to a semiconductor capable of suppressing damage to other films existing on and under a PMD film due to impurities in a PMD film, which is an interlayer insulating film, and defects during contact hole processing. A method of forming an insulating film of a device.
근래에 컴퓨터와 같은 정보 매체의 급속한 발전에 따라 반도체 소자 제조 기술도 비약적으로 발전하고 있다. 상기 반도체 소자는 집적도, 미세화, 동작속도 등을 향상시키는 방향으로 기술이 발전하고 있으며, 흔히 무어의 법칙(Moore's Law) 으로 알려진 것처럼, 반도체 소자의 집접도는 2년마다 약 2배가 증가하고 있다. 이에 따라 칩 사이즈 및 회로 선폭이 갈수록 작아지고 이로 인해 이전에 존재하지 않던 새로운 문제가 발생하고 있다.In recent years, with the rapid development of information media such as computers, semiconductor device manufacturing technology is also rapidly developing. The semiconductor device has been developed in the direction of improving the degree of integration, miniaturization, operating speed, and the like, and as commonly known as Moore's Law, the degree of integration of the semiconductor device is increasing about two times every two years. As a result, chip size and circuit line width become smaller and smaller, which presents new problems that did not exist previously.
피엠디(Premetal Dielectric, 이하 PMD)막은 폴리실리콘 게이트와 금속배선간을 분리하는 층간절연막으로서, 갭필(Gap fill) 성능, 개더링(Gathering) 성능이 우수하고 평탄화가 용이해야 한다.Premetal Dielectric (PMD) film is an interlayer insulating film that separates a polysilicon gate from a metal wiring, and has to be excellent in gap fill performance, gathering performance, and easy to planarize.
갭필 성능이란 반도체 소자의 패턴에 의한 단차를 메울 수 있는 능력을 의미하며, 개더링 성능은 디바이스의 특성을 저하시키는 모바일 이온(mobile ion), 예를 들어 나트륨 이온 또는 기타 금속 이온을 트랩(trap)하는 능력을 의미한다.Gap fill performance refers to the ability to fill a step due to a pattern of a semiconductor device, and gathering performance is used to trap mobile ions, such as sodium ions or other metal ions, which degrade device characteristics. It means ability.
절연막으로 많이 사용되는 실리콘 산화막(SiO2)은 폴리실리콘 게이트에 의해 형성되는 단차를 메우는 능력이 부족하다. 따라서, 상기 실리콘 산화막으로 형성된 PMD막에는 보이드(void)가 형성되기 때문에 피엠디막이 치밀하지 못하여 소자의 특성을 저하시킬 뿐만 아니라 콘택을 형성하기 위한 이후 공정에서 도전성 물질의 증착시 상기 보이드에도 도전성 물질이 형성됨에 따라 콘택 간에 쇼트(short) 현상이 발생되어 반도체 소자의 생산 수율을 저하시키는 원인이 되고 있다.Silicon oxide film (SiO 2 ), which is frequently used as an insulating film, lacks the ability to fill in the steps formed by the polysilicon gate. Therefore, since voids are formed in the PMD film formed of the silicon oxide film, the PMD film is not dense, thereby degrading the characteristics of the device, and in the subsequent process for forming a contact, the conductive material is also formed on the void during deposition of the conductive material. As a result of this formation, a short phenomenon occurs between the contacts, which causes a decrease in the production yield of the semiconductor device.
따라서, 상기 실리콘 산화막을 대신하는 PMD막용 물질로 갭필 성능이 우수한 보로포스포실리케이트 글래스(Borophosphosilicate Glass, 이하 BPSG)막을 이용한다. 일반적으로, BPSG막은 실리콘 산화막을 형성할 때 도입하는 실리콘, 산소 소스(source)와 더불어 반응 챔버(chamber)에 붕소(B)와 인(P) 소스를 같이 도입하 여 형성한다. 여기서, 붕소는 갭필 성능 향상을 위해서, 인은 모바일 이온의 개더링 성능 향상을 위해서 도핑한다.Therefore, a borophosphosilicate glass (BPSG) film having excellent gap fill performance is used as a material for the PMD film instead of the silicon oxide film. In general, a BPSG film is formed by introducing a boron (B) and a phosphorus (P) source together in a reaction chamber together with a silicon and an oxygen source introduced when a silicon oxide film is formed. Here, boron is doped to improve gap fill performance and phosphorus to improve gathering performance of mobile ions.
그런데 도핑된 붕소 또는 인이 열처리 공정과 같은 후속 공정 진행시 상부 또는 하부로 확산하여 반도체 소자의 전기적 특성을 열화시키고 있다. 또한 증착 장비의 에러 또는 기타 원인에 의해 BPSG막의 불순물 첨가량이 불안정하여 붕소 및 인이 고농도로 함유되어 과포화 상태가 될 수 있다. 이 경우 콘택홀(Contact hole) 공정과 같은 후속 공정 진행시 농도 차이에 의한 식각의 불균형에 의해 반도체 소자의 쇼트(Short) 불량이 발생하거나 콘택홀 공정 이후에도 상기 불순물에 의해 콘택 금속의 손상이 발생할 수도 있다. 도 1은 SRAM(Static Ramdom Access Memeory) 반도체 소자의 단면 SEM(Scanning Electron Microscope) 사진으로서, PMD막(10)에 형성된 고농도의 불순물 영역(12) 및 그로 인한 식각 불균형에 의해 발생한 콘택 금속(14)과 측벽 질화막(16)의 쇼트 불량(18)을 확인할 수 있다.However, doped boron or phosphorus diffuses to the upper or lower portion during the subsequent process such as heat treatment process, thereby deteriorating the electrical characteristics of the semiconductor device. In addition, the amount of impurity added to the BPSG film may be unstable due to an error or other cause of the deposition equipment, so that boron and phosphorus may be contained in high concentrations, resulting in a supersaturated state. In this case, short defects in the semiconductor device may occur due to an imbalance in etching due to a difference in concentration during a subsequent process such as a contact hole process, or damage of the contact metal may occur due to the impurities even after the contact hole process. have. FIG. 1 is a scanning electron microscope (SEM) photograph of a cross-section of a static ramdom access mechanism (SRAM) semiconductor device, and the
상기와 같은 문제를 해결하기 위해 대한민국 공개특허공보 특허 제2001-26808호, 대한민국 공개특허공보 제1997-77328호는 BPSG막의 하부에 실리콘 리치 산화막을 형성하여 반도체 소자의 열화를 방지하는 절연막 형성 방법을 개시하고 있다. 그러나 이와 같은 종래의 절연막 형성 방법은 BPSG막의 불순물에 의해 BPSG막 상부의 금속막 또는 절연막이 손상되는 현상을 방지하지 못하고 있으며 콘택홀 공정시 불순물의 확산에 의한 불량 발생 원인을 제거하지 못하고 있다.In order to solve the above problems, Korean Patent Laid-Open Publication No. 2001-26808 and Korean Patent Laid-Open Publication No. 1997-77328 provide a method of forming an insulating film to prevent deterioration of a semiconductor device by forming a silicon rich oxide film under a BPSG film. It is starting. However, the conventional method of forming an insulating film does not prevent the metal film or the insulating film on the BPSG film from being damaged by the impurities of the BPSG film, and does not eliminate the cause of defects caused by the diffusion of impurities during the contact hole process.
따라서, 본 발명은 상기와 같은 종래 기술의 문제점을 해결하기 위한 것으로, 층간절연막인 BPSG막의 상부 및 하부에 실리콘 리치 산화막을 형성하고 콘택홀 공정시 콘택 금속 매립 전에 콘택홀을 플라즈마 처리하여 BPSG막의 불순물에 의한 상부 및 하부 막의 손상 및 콘택홀 공정시의 불량 발생을 억제할 수 있는 반도체 소자의 절연막 형성 방법을 제공함에 본 발명의 목적이 있다.
Accordingly, the present invention is to solve the problems of the prior art as described above, by forming a silicon rich oxide film on the upper and lower portions of the BPSG film which is an interlayer insulating film and plasma treatment of the contact hole before contact metal buried in the contact hole process impurities of the BPSG film SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming an insulating film of a semiconductor device capable of suppressing damage to upper and lower films caused by defects and defects during a contact hole process.
본 발명의 상기목적은 게이트 전극, 소스/드레인 등을 포함한 소정의 구조물이 형성된 반도체 기판 상에 PMD 라이너막을 형성하는 단계; 상기 PMD 라이너막 상에 제 1 실리콘 리치 산화막을 형성하는 단계; 상기 제 1 실리콘 리치 산화막 상에 PMD막을 형성하고 평탄화하는 단계; 및 상기 평탄화된 PMD막 상에 제 2 실리콘 리치 산화막을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 절연막 형성 방법에 의해 달성된다.The object of the present invention is to form a PMD liner film on a semiconductor substrate on which a predetermined structure including a gate electrode, a source / drain, etc. is formed; Forming a first silicon rich oxide film on the PMD liner film; Forming and planarizing a PMD film on the first silicon rich oxide film; And forming a second silicon rich oxide film on the planarized PMD film.
본 발명의 상기 목적과 기술적 구성 및 그에 따른 작용효과에 관한 자세한 사항은 본 발명의 바람직한 실시예를 도시하고 있는 도면을 참조한 이하 상세한 설명에 의해 보다 명확하게 이해될 것이다.Details of the above object and technical configuration of the present invention and the effects thereof according to the present invention will be more clearly understood by the following detailed description with reference to the drawings showing preferred embodiments of the present invention.
이하에서는 본 발명에 의한 반도체 소자의 절연막 형성 방법의 흐름도인 도 2와 본 발명에 의한 반도체 소자의 절연막 형성 공정의 단면도인 도 3 및 도 4를 참조하여 설명하도록 한다.Hereinafter, with reference to FIG. 2 which is a flowchart of the insulating film forming method of the semiconductor element by this invention, and FIG. 3 and FIG. 4 which is sectional drawing of the insulating film formation process of the semiconductor element by this invention.
먼저, 반도체 기판(100) 상에 STI(Shallow Trench Isolation) 또는 LOCOS(Local Oxidation of Silicon) 공정을 사용한 소자분리막(102), 게이트 산화막(104), 폴리 실리콘 게이트 전극(106), 소스/드레인(도시하지 않음), 측벽 질화막(Side wall nitride, 108) 및 실리사이드(110)를 포함한 반도체 소자를 공지의 반도체 공정 기술을 사용하여 완성한다.First, the
다음, 상기 반도체 기판 상에 PMD 라이너(Liner)막(112)을 형성한다(S100). 상기 PMD 라이너막(112)은 질화막 또는 플라즈마 인핸스드 TEOS(Plasma Enhanced Tetraethyl Ortho Silicate, 이하 PETEOS) 산화막으로 형성하는 것이 바람직하다. 상기 PETEOS막은 예를 들어, PPECVD 공정을 통해 TEOS 전구체(Precursor)를 산소와 반응시켜 10 내지 200nm 정도의 두께로 형성한다. 이와 같이 형성된 PETEOS막은 이후에 형성되는 제 1 실리콘 리치 산화(SRO: Silicon Rich Oxide)막과 더불어 PMD막(116)에 존재하는 불순물이 하부로 확산하여 반도체 소자를 열화시키는 것을 방지하는 역할을 한다.Next, a
다음, 화학기상증착(Chemical Vapor Deposition, 이하 CVD)법을 통해 제 1 실리콘 리치 산화막(114)을 형성한다(S101). 상기 제 1 실리콘 리치 산화막의 형성은 PECVD(Plasma Enhanced CVD) 공정을 통해 200 내지 450℃의 온도 범위에서 SiH4와 O2 또는 N2O 가스를 챔버 내에서 반응시켜 형성할 수도 있으며 LPCVD(Low Pressure CVD) 공정을 통해 700 내지 800℃의 온도 범위에서 SiH4와 N2O 가스를 반응시켜 형성할 수도 있다.Next, a first silicon
다음, PMD막(116)을 형성한다(S102). 상기 PMD막(116)으로는 BPSG막, 포스포 실리케이트 글래스(Phosphosilicate Glass, 이하 PSG)막 또는 보로실리케이트 글래스(Borosilicate Glass, 이하 BSG)막을 사용할 수 있으나 BPSG막이 보다 바람직하다.Next, a PMD
BPSG막은 PECVD, APCVD(Atmospheric Pressure CVD), SACVD(Sub-Atmospheric Pressure CVD), LPCVD와 같은 CVD 공정을 통해 형성하며 전구체로는 SiH4 또는 TEOS를 사용할 수 있다. BPSG막 내의 붕소는 갭필 능력 및 모바일 이온의 개더링 능력등을 고려하여 붕소(B)의 경우 3 내지 5 wt%, 인(P)의 경우 5 내지 7 wt%가 되도록 하는 것이 바람직하다.The BPSG film is formed through a CVD process such as PECVD, Atmospheric Pressure CVD (APCVD), Sub-Atmospheric Pressure CVD (SACVD), and LPCVD. SiH 4 or TEOS may be used as a precursor. Boron in the BPSG film is preferably 3 to 5 wt% for boron (B) and 5 to 7 wt% for phosphorus (P) in consideration of the gapfill ability and the gathering ability of mobile ions.
PSG막은 PECVD, APCVD 또는 고밀도 플라즈마(HDP : High Density Plasma) CVD를 이용하여 형성할 수 있다. 예들 들어, 반응 챔버에 SiH4, PH3, 산소 및 아르곤을 도입한 후, 온도를 400℃ 내지 650℃, 압력을 1 mTorr 내지 10 mTorr로 유지하고 기판에 고밀도 플라즈마 바이어스(bias)를 인가하는 HDP CVD 방법을 통해 형성하는 것이 가능하다.The PSG film can be formed using PECVD, APCVD or High Density Plasma (HDP) CVD. For example, after introducing SiH 4 , PH 3 , oxygen and argon into the reaction chamber, the HDP maintains the temperature at 400 ° C. to 650 ° C., the pressure at 1 mTorr to 10 mTorr and applies a high density plasma bias to the substrate. It is possible to form through the CVD method.
상기 PMD막(116) 내에 형성된 보이드(도시하지 않음)는 PMD막의 치밀화를 방해하고 이후의 도전성 물질 형성시 도전성 물질이 매입되어 불량을 유발하는 원인이 된다. 이를 방지하기 위해 상기 PMD막을 열처리하여 치밀화한다. 상기 열처리 공정은, 예를 들어 급속 열공정(RTP : Rapid Thermal Process)로 700℃ 내지 1100℃로 20초 내지 60초 동안 진행하거나 노(furnace)를 이용하여 700℃ 내지 1100℃로 20분 내지 60분간 어닐링한다.Voids (not shown) formed in the
다음, 화학적 기계적 연마(CMP: Chemical Mechanical Polishing) 공정을 통해 PMD막(116)을 평탄화하고(S103) 제 2 실리콘 리치 산화막(118)을 형성한다(S104). 상기 제 2 실리콘 리치 산화막(118)의 형성 방법은 제 1 실리콘 리치 산화막(114)의 형성 방법과 동일하다.Next, the
다음, 포토레지스트를 코팅하고 노광 및 현상하여 콘택홀(120)을 형성하기 위한 부분을 노출시킨 후 PMD 라이너막(112), 제 1 실리콘 리치 산화막(114), PMD막(116) 및 제 2 실리콘 리치 산화막(118)을 식각하여 콘택홀(120)을 형성한다(S105).Next, after the photoresist is coated, exposed, and developed to expose a portion for forming the
다음, 상기 콘택홀(120)에 의해 노출된 PMD막(116)의 측면을 플라즈마 처리하여 불순물이 없는 얇은 버퍼막(122)을 형성한다(S106). 상기 플라즈마 처리를 위해 N2O 가스 또는 NH3와 N2 혼합가스에 의한 플라즈마를 사용할 수 있으며 N2O 가스를 사용한 플라즈마 처리가 보다 바람직하다. 상기 N2O 플라즈마 처리에 의해 콘택홀 형성시 노출된 PMD막(116)의 표면에 존재하는 Si-H기를 SiO2로 변화시킴으로써 표면에 얇은 버퍼막(122)을 형성할 수 있다. 이와 같은 플라즈마 처리에 의해 PMD막 내의 국부적인 불순물 농도의 불균일에 의한 식각 속도의 차이, 불순물 확산에 의한 쇼트 불량 등을 방지할 수 있다.Next, a side surface of the
이후, Ti/TiN과 같은 배리어 메탈과 텅스텐(W)과 같은 콘택 전극을 증착한 후 공지의 반도체 공정 기술을 이용하여 SRAM, DRAM과 같은 반도체 소자를 완성한다.Thereafter, a barrier metal such as Ti / TiN and a contact electrode such as tungsten (W) are deposited, and then a semiconductor device such as SRAM or DRAM is completed using a known semiconductor process technology.
본 발명은 이상에서 살펴본 바와 같이 바람직한 실시 예를 들어 도시하고 설명하였으나, 상기한 실시 예에 한정되지 아니하며 본 발명의 정신을 벗어나지 않는 범위 내에서 당해 발명이 속하는 기술분야에서 통상의 지식을 가진 자에 의해 다양한 변경과 수정이 가능할 것이다.Although the present invention has been shown and described with reference to preferred embodiments as described above, it is not limited to the above-described embodiments and those skilled in the art without departing from the spirit of the present invention. Various changes and modifications will be possible.
따라서, 본 발명의 반도체 소자의 절연막 형성 방법은 PMD막의 상부 및 하부에 실리콘 리치 산화막을 형성하고 콘택 금속 매립 전에 플라즈마 처리를 함으로써 PMD막의 불순물에 의해 야기될 수 있는 반도체 소자의 불량을 방지하여 수율을 향상시키고 소자의 전기적 특성 및 신뢰성을 향상시키는 효과가 있다.Therefore, the method for forming an insulating film of the semiconductor device of the present invention by forming a silicon rich oxide film on the upper and lower portions of the PMD film and performing a plasma treatment before filling the contact metal to prevent the defect of the semiconductor device that may be caused by impurities in the PMD film to improve the yield There is an effect to improve and improve the electrical characteristics and reliability of the device.
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| KR100821481B1 (en) * | 2006-12-27 | 2008-04-11 | 동부일렉트로닉스 주식회사 | Method for manufacturing semiconductor device |
| KR100881510B1 (en) * | 2006-12-27 | 2009-02-05 | 동부일렉트로닉스 주식회사 | Method for forming of BPSG liner |
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| KR100763691B1 (en) * | 2006-08-30 | 2007-10-04 | 동부일렉트로닉스 주식회사 | Method for forming pmd-psg thin layer using apcvd |
| KR100821481B1 (en) * | 2006-12-27 | 2008-04-11 | 동부일렉트로닉스 주식회사 | Method for manufacturing semiconductor device |
| KR100881510B1 (en) * | 2006-12-27 | 2009-02-05 | 동부일렉트로닉스 주식회사 | Method for forming of BPSG liner |
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